mirror of
https://github.com/Dev-KATECH/ADM.git
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598 lines
22 KiB
C
598 lines
22 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral :
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file Clock_Ip_Pll.c
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* @version 0.9.0
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*
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* @brief CLOCK driver implementations.
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* @details CLOCK driver implementations.
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*
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* @addtogroup CLOCK_DRIVER Clock Ip Driver
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* @{
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*/
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/**
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* @page misra_violations MISRA-C:2012 violations
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*
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* @section Clock_Ip_Pll_c_REF_1
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* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor
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* directives or comments. AUTOSAR imposes the specification of the sections in which certain parts
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* of the driver must be placed.
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*
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* @section Clock_Ip_Pll_c_REF_2
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* Violates MISRA 2012 Advisory Rule 4.8, This file includes the definition
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* of types but does not use it. Header is common for all files
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*
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*/
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#include "Clock_Ip_Private.h"
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/*==================================================================================================
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SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define CLOCK_IP_PLL_VENDOR_ID_C 43
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#define CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C 4
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#define CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C 4
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#define CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C 0
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#define CLOCK_IP_PLL_SW_MAJOR_VERSION_C 0
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#define CLOCK_IP_PLL_SW_MINOR_VERSION_C 9
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#define CLOCK_IP_PLL_SW_PATCH_VERSION_C 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same vendor */
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#if (CLOCK_IP_PLL_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
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#error "Clock_Ip_Pll.c and Clock_Ip_Private.h have different vendor ids"
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#endif
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/* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Autosar version */
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#if ((CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
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(CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
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(CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
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)
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#error "AutoSar Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
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#endif
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/* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Software version */
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#if ((CLOCK_IP_PLL_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
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(CLOCK_IP_PLL_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
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(CLOCK_IP_PLL_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
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)
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#error "Software Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
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#endif
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/* Clock start section code */
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#define MCU_START_SEC_CODE
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/**
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* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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static void Callback_PllEmpty(Clock_Ip_PllConfigType const* config);
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static clock_pll_status_t Callback_PllEmptyComplete(Clock_Ip_NameType PllName);
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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static void ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config);
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static void SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config);
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static clock_pll_status_t CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName);
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#endif
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN
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static void ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* config);
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static void SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* config);
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static clock_pll_status_t CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName);
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#endif
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#ifdef PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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static void ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config);
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static void SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config);
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static clock_pll_status_t CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName);
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#endif
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#ifdef SPLL_ENABLE
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static status_t SPLLEnable(Clock_Ip_PllConfigType const* config);
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#endif
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#ifdef SPLL_ENABLE
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static void ResetSpll(Clock_Ip_PllConfigType const* config);
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static void SetSpll(Clock_Ip_PllConfigType const* config);
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static clock_pll_status_t CompleteSpll(Clock_Ip_PllConfigType const* config);
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#endif
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/* Clock stop section code */
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#define MCU_STOP_SEC_CODE
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/**
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* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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/* Clock start constant section data */
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#define MCU_START_SEC_CONST_UNSPECIFIED
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/**
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* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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const pllCallback pllCallbacks[PLL_CALLBACKS_COUNT] =
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{
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{
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Callback_PllEmpty, /* Reset */
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Callback_PllEmpty, /* Set */
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Callback_PllEmptyComplete, /* Complete */
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},
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/* Pll with frequency modulation */
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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{
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ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize, /* Reset */
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SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize, /* Set */
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CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize, /* Complete */
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},
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#endif
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/* Pll without frequency modulation */
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN
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{
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ResetPlldigRdivMfiMfnSdmen, /* Reset */
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SetPlldigRdivMfiMfnSdmen, /* Set */
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CompletePlldigRdivMfiMfnSdmen, /* Complete */
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},
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#endif
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/* Pll with frequency modulation and VCO clock post divider for driving the PHI output clocks */
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#ifdef PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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{
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ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize, /* Reset */
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SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize, /* Set */
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CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize, /* Complete */
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},
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#endif
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/* System Pll */
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#ifdef SPLL_ENABLE
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{
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ResetSpll, /* Reset */
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SetSpll, /* Set */
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CompleteSpll, /* Complete */
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},
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#endif
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};
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/* Clock stop constant section data */
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#define MCU_STOP_SEC_CONST_UNSPECIFIED
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/**
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* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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#define MCU_START_SEC_CODE
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/* Clock start section code */
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/**
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* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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static void Callback_PllEmpty(Clock_Ip_PllConfigType const* config)
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{
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(void)config;
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/* No implementation */
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}
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static clock_pll_status_t Callback_PllEmptyComplete(Clock_Ip_NameType PllName)
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{
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(void)PllName;
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/* No implementation */
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return STATUS_PLL_NOT_ENABLED;
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}
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/* Pll with frequency modulation */
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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static void ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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/* Power down PLL */
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pll[instance]->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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static void SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 value;
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if (config->enable != 0U)
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{
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/* Select input reference. */
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pll[instance]->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(config->inputReference);
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/* Configure PLL: predivider and multiplier */
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value = (uint32) (PLLDIG_PLLDV_RDIV(config->predivider) |
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PLLDIG_PLLDV_MFI(config->mulFactorDiv));
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pll[instance]->PLLDV = value;
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/* Set numerator fractional loop divider and sigma delta modulation */
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value = pll[instance]->PLLFD;
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value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
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value |= PLLDIG_PLLFD_MFN(config->numeratorFracLoopDiv);
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value |= PLLDIG_PLLFD_SDMEN(config->sigmaDelta);
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pll[instance]->PLLFD = value;
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/* Configure modulation */
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value = (uint32) (PLLDIG_PLLFM_SSCGBYP((config->modulationFrequency != 0U) ? 0UL : 1UL) |
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PLLDIG_PLLFM_SPREADCTL(config->modulationType) |
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PLLDIG_PLLFM_STEPNO(config->incrementStep) |
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PLLDIG_PLLFM_STEPSIZE(config->modulationPeriod));
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pll[instance]->PLLFM = value;
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/* Send command to enable PLL device. */
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pll[instance]->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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static clock_pll_status_t CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)
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{
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clock_pll_status_t pllStatus = STATUS_PLL_LOCKED;
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 PllLockStatus;
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uint32 instance = clockFeatures[PllName][CLOCK_MODULE_INSTANCE];
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if ((pll[instance]->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) == 0U)
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{
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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/* Wait until this pll is locked */
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do
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{
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Clock_Ip_TimeDelay();
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PllLockStatus = ((pll[instance]->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while ((PllLockStatus == 0U) && (FALSE == TimeoutOccurred));
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if (TRUE == TimeoutOccurred)
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{
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UpdateClockState(PllName, DISABLED_CLOCK);
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pllStatus = STATUS_PLL_UNLOCKED;
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}
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}
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else
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{
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pllStatus = STATUS_PLL_NOT_ENABLED;
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}
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return pllStatus;
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}
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#endif
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/* Pll with frequency modulation and VCO clock post divider for driving the PHI output clocks */
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#ifdef PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
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static void ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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/* Check clock status for PLL */
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if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) != 0U)
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{
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/* Power down PLL */
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pll[instance]->PLLCR |= PLL_PLLCR_PLLPD_MASK;
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}
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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static void SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 value;
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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if (config->enable != 0U)
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{
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/* Check clock status for PLL */
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if (((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U))
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{
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/* Enable clock for PLL device */
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MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ56(1U); /* REQ56: Frequency Modulated Phase-Locked Loop */
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MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
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MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
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MC_ME->CTL_KEY = 0x5AF0; /* Enter key */
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MC_ME->CTL_KEY = 0xA50F; /* Enter inverted key */
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/* Wait until PLL clock is running */
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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do
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{
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while (((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U) && (FALSE == TimeoutOccurred));
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/* timeout notification */
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if (TRUE == TimeoutOccurred)
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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}
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/* Configure PLL: predivider and multiplier */
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value = pll[instance]->PLLDV;
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value &= ~(PLL_PLLDV_RDIV_MASK | PLL_PLLDV_MFI_MASK);
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value |= (uint32) (PLL_PLLDV_RDIV(config->predivider) |
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PLL_PLLDV_MFI(config->mulFactorDiv));
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pll[instance]->PLLDV = value;
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/* Set numerator fractional loop divider and sigma delta modulation */
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value = pll[instance]->PLLFD;
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value &= ~(PLL_PLLFD_MFN_MASK | PLL_PLLFD_SDMEN_MASK);
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value |= PLL_PLLFD_MFN(config->numeratorFracLoopDiv);
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value |= PLL_PLLFD_SDMEN(config->sigmaDelta);
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pll[instance]->PLLFD = value;
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/* Configure modulation */
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value = (uint32) (PLL_PLLFM_SSCGBYP((config->modulationFrequency != 0U) ? 0UL : 1UL) |
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PLL_PLLFM_SPREADCTL(config->modulationType) |
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PLL_PLLFM_STEPNO(config->incrementStep) |
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PLL_PLLFM_STEPSIZE(config->modulationPeriod));
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pll[instance]->PLLFM = value;
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/* Send command to enable PLL device. */
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pll[instance]->PLLCR &= ~PLL_PLLCR_PLLPD_MASK;
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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static clock_pll_status_t CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)
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{
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clock_pll_status_t pllStatus = STATUS_PLL_LOCKED;
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 PllLockStatus;
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uint32 instance = clockFeatures[PllName][CLOCK_MODULE_INSTANCE];
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if ((pll[instance]->PLLCR & PLL_PLLCR_PLLPD_MASK) == 0U)
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{
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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/* Wait until this pll is locked */
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do
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{
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Clock_Ip_TimeDelay();
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PllLockStatus = ((pll[instance]->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT);
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while ((PllLockStatus == 0U) && (FALSE == TimeoutOccurred));
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if (TRUE == TimeoutOccurred)
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{
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UpdateClockState(PllName, DISABLED_CLOCK);
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pllStatus = STATUS_PLL_UNLOCKED;
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}
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}
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else
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{
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pllStatus = STATUS_PLL_NOT_ENABLED;
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}
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return pllStatus;
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}
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#endif
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/* Pll without frequency modulation */
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#ifdef PLLDIG_RDIV_MFI_MFN_SDMEN
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static void ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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/* Power down PLL */
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pll[instance]->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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static void SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 value;
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if (config->enable != 0U)
|
|
{
|
|
/* Select input reference. */
|
|
pll[instance]->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(config->inputReference);
|
|
|
|
/* Configure PLL: predivider and multiplier */
|
|
value = (uint32) (PLLDIG_PLLDV_RDIV(config->predivider) |
|
|
PLLDIG_PLLDV_MFI(config->mulFactorDiv));
|
|
pll[instance]->PLLDV = value;
|
|
|
|
/* Set numerator fractional loop divider and sigma delta modulation */
|
|
value = pll[instance]->PLLFD;
|
|
value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
|
|
value |= PLLDIG_PLLFD_MFN(config->numeratorFracLoopDiv);
|
|
value |= PLLDIG_PLLFD_SDMEN(config->sigmaDelta);
|
|
pll[instance]->PLLFD = value;
|
|
|
|
/* Send command to enable PLL device. */
|
|
pll[instance]->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
|
|
UpdateClockState(config->name, ENABLED_CLOCK);
|
|
}
|
|
}
|
|
static clock_pll_status_t CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName)
|
|
{
|
|
clock_pll_status_t pllStatus = STATUS_PLL_LOCKED;
|
|
boolean TimeoutOccurred = FALSE;
|
|
uint32 StartTime;
|
|
uint32 ElapsedTime;
|
|
uint32 TimeoutTicks;
|
|
uint32 PllLockStatus;
|
|
uint32 instance = clockFeatures[PllName][CLOCK_MODULE_INSTANCE];
|
|
|
|
if ((pll[instance]->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) == 0U)
|
|
{
|
|
ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
|
|
/* Wait until this pll is locked */
|
|
do
|
|
{
|
|
Clock_Ip_TimeDelay();
|
|
PllLockStatus = ((pll[instance]->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
|
|
TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
|
|
}
|
|
while ((PllLockStatus == 0U) && (FALSE == TimeoutOccurred));
|
|
|
|
if(TRUE == TimeoutOccurred)
|
|
{
|
|
UpdateClockState(PllName, DISABLED_CLOCK);
|
|
pllStatus = STATUS_PLL_UNLOCKED;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pllStatus = STATUS_PLL_NOT_ENABLED;
|
|
}
|
|
return pllStatus;
|
|
}
|
|
#endif
|
|
|
|
#ifdef SPLL_ENABLE
|
|
static void ResetSpll(Clock_Ip_PllConfigType const* config)
|
|
{
|
|
/* Power down PLL */
|
|
|
|
/* Clear LK bit field */
|
|
SCG->SPLLCSR &= (uint32)(~(SCG_SPLLCSR_LK_MASK));
|
|
|
|
/* Disable clock */
|
|
SCG->SPLLCSR &= (uint32)(~(SCG_SPLLCSR_SPLLEN_MASK));
|
|
|
|
UpdateClockState(config->name, DISABLED_CLOCK);
|
|
}
|
|
static void SetSpll(Clock_Ip_PllConfigType const* config)
|
|
{
|
|
/* Configure SPLL. */
|
|
if (config->enable)
|
|
{
|
|
/* Set frequency range. Calculate based on the frequency range */
|
|
uint32 range = 0U; /* TODO update these fields */
|
|
|
|
/* Set PLL configuration. */
|
|
SPLL->SPLLCFG = SCG_SPLLCFG_PREDIV(config->predivider) |
|
|
SCG_SPLLCFG_MULT(config->multiplier);
|
|
|
|
/* Step 3. Enable clock, configure monitor, lock register. */
|
|
switch (SPLLCfg->monitorMode)
|
|
{
|
|
case SCG_SPLL_MONITOR_DISABLE:
|
|
{
|
|
value = SCG_SPLLCSR_SPLLEN(0UL) |
|
|
SCG_SPLLCSR_SPLLCM(0UL) |
|
|
SCG_SPLLCSR_SPLLCMRE(0UL));
|
|
}
|
|
break;
|
|
case SCG_SPLL_MONITOR_INT:
|
|
{
|
|
value = SCG_SPLLCSR_SPLLEN(1UL) |
|
|
SCG_SPLLCSR_SPLLCM(0UL) |
|
|
SCG_SPLLCSR_SPLLCMRE(0UL));
|
|
}
|
|
break;
|
|
case SCG_SPLL_MONITOR_RESET:
|
|
{
|
|
value = SCG_SPLLCSR_SPLLEN(1UL) |
|
|
SCG_SPLLCSR_SPLLCM(1UL) |
|
|
SCG_SPLLCSR_SPLLCMRE(0UL));
|
|
}
|
|
break;
|
|
default:
|
|
/* Invalid monitor mode */
|
|
DEV_ASSERT(false);
|
|
break;
|
|
}
|
|
|
|
SCG->SPLLCSR = value;
|
|
}
|
|
}
|
|
static clock_pll_status_t CompleteSpll(Clock_Ip_PllConfigType const* config)
|
|
{
|
|
clock_pll_status_t pllStatus = STATUS_PLL_LOCKED;
|
|
boolean TimeoutOccurred = FALSE;
|
|
uint32 StartTime;
|
|
uint32 ElapsedTime;
|
|
uint32 TimeoutTicks;
|
|
|
|
|
|
/* Configure SPLL. */
|
|
if ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLEN_MASK) == 0U)
|
|
{
|
|
ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
|
|
/* Wait until ircosc is locked */
|
|
do
|
|
{
|
|
Clock_Ip_TimeDelay();
|
|
SPLLStatus = (((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) >> SCG_SPLLCSR_SPLLVLD_SHIFT));
|
|
TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
|
|
}
|
|
while ((SPLLStatus == 0U) && (FALSE == TimeoutOccurred));
|
|
|
|
if (FALSE == TimeoutOccurred)
|
|
{
|
|
UpdateClockState(config->name, ENABLED_CLOCK);
|
|
pllStatus = STATUS_PLL_UNLOCKED;
|
|
}
|
|
else
|
|
{
|
|
/* Report timeout error */
|
|
ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pllStatus = STATUS_PLL_DISABLED;
|
|
}
|
|
return pllStatus;
|
|
}
|
|
#endif
|
|
|
|
|
|
/* Clock stop section code */
|
|
#define MCU_STOP_SEC_CODE
|
|
/**
|
|
* @violates @ref Clock_Ip_Pll_c_REF_1 #include directives should only be preceded by preprocessor
|
|
* directives or comments.
|
|
*/
|
|
#include "Mcu_MemMap.h"
|
|
|
|
/*! @}*/
|
|
|
|
/*******************************************************************************
|
|
* EOF
|
|
******************************************************************************/
|
|
|