ADM/[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/html/data/data.js

var dataJson = {"arch":{"ispc":true,"isunix":false,"ismac":false},"build":"ADM_Integrated_Logic","ref":false,"files":[{"name":"ert_main.c","type":"source","group":"main","path":"C:\\Users\\MSI\\Documents\\WorkSpace\\git\\ADM\\[ADM] Integrated Logic\\ADM_Integrated_Logic_ert_rtw","tag":"","groupDisplay":"Main file","code":"/*\r\n * Academic License - for use in teaching, academic research, and meeting\r\n * course requirements at degree granting institutions only.  Not for\r\n * government, commercial, or other organizational use.\r\n *\r\n * File: ert_main.c\r\n *\r\n * Code generated for Simulink model 'ADM_Integrated_Logic'.\r\n *\r\n * Model version                  : 14.26\r\n * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024\r\n * C/C++ source code generated on : Tue Oct 14 20:08:12 2025\r\n *\r\n * Target selection: ert.tlc\r\n * Embedded hardware selection: NXP->Cortex-M4\r\n * Code generation objectives:\r\n *    1. Execution efficiency\r\n *    2. RAM efficiency\r\n *    3. Debugging\r\n * Validation result: Not run\r\n */\r\n\r\n#include <stddef.h>\r\n#include <stdio.h>            /* This example main program uses printf/fflush */\r\n#include \"ADM_Integrated_Logic.h\"      /* Model header file */\r\n\r\n/*\r\n * Associating rt_OneStep with a real-time clock or interrupt service routine\r\n * is what makes the generated code \"real-time\".  The function rt_OneStep is\r\n * always associated with the base rate of the model.  Subrates are managed\r\n * by the base rate from inside the generated code.  Enabling/disabling\r\n * interrupts and floating point context switches are target specific.  This\r\n * example code indicates where these should take place relative to executing\r\n * the generated code step function.  Overrun behavior should be tailored to\r\n * your application needs.  This example simply sets an error status in the\r\n * real-time model and returns from rt_OneStep.\r\n */\r\nvoid rt_OneStep(void);\r\nvoid rt_OneStep(void)\r\n{\r\n  static bool OverrunFlag = false;\r\n\r\n  /* Disable interrupts here */\r\n\r\n  /* Check for overrun */\r\n  if (OverrunFlag) {\r\n    rtmSetErrorStatus(ADM_Integrated_Logic_M, \"Overrun\");\r\n    return;\r\n  }\r\n\r\n  OverrunFlag = true;\r\n\r\n  /* Save FPU context here (if necessary) */\r\n  /* Re-enable timer or interrupt here */\r\n  /* Set model inputs here */\r\n\r\n  /* Step the model */\r\n  ADM_Integrated_Logic_step();\r\n\r\n  /* Get model outputs here */\r\n\r\n  /* Indicate task complete */\r\n  OverrunFlag = false;\r\n\r\n  /* Disable interrupts here */\r\n  /* Restore FPU context here (if necessary) */\r\n  /* Enable interrupts here */\r\n}\r\n\r\n/*\r\n * The example main function illustrates what is required by your\r\n * application code to initialize, execute, and terminate the generated code.\r\n * Attaching rt_OneStep to a real-time clock is target specific. This example\r\n * illustrates how you do this relative to initializing the model.\r\n */\r\nint main(int argc, const char *argv[])\r\n{\r\n  /* Unused arguments */\r\n  (void)(argc);\r\n  (void)(argv);\r\n\r\n  /* Initialize model */\r\n  ADM_Integrated_Logic_initialize();\r\n\r\n  /* Attach rt_OneStep to a timer or interrupt service routine with\r\n   * period 0.002 seconds (base rate of the model) here.\r\n   * The call syntax for rt_OneStep is\r\n   *\r\n   *  rt_OneStep();\r\n   */\r\n  printf(\"Warning: The simulation will run forever. \"\r\n         \"Generated ERT main won't simulate model step behavior. \"\r\n         \"To change this behavior select the 'MAT-file logging' option.\\n\");\r\n  fflush((NULL));\r\n  while (rtmGetErrorStatus(ADM_Integrated_Logic_M) == (NULL)) {\r\n    /*  Perform application tasks here */\r\n  }\r\n\r\n  return 0;\r\n}\r\n\r\n/*\r\n * File trailer for generated code.\r\n *\r\n * [EOF]\r\n */\r\n"},{"name":"ADM_Integrated_Logic.c","type":"source","group":"model","path":"C:\\Users\\MSI\\Documents\\WorkSpace\\git\\ADM\\[ADM] Integrated Logic\\ADM_Integrated_Logic_ert_rtw","tag":"","groupDisplay":"Model files","code":"/*\r\n * Academic License - for use in teaching, academic research, and meeting\r\n * course requirements at degree granting institutions only.  Not for\r\n * government, commercial, or other organizational use.\r\n *\r\n * File: ADM_Integrated_Logic.c\r\n *\r\n * Code generated for Simulink model 'ADM_Integrated_Logic'.\r\n *\r\n * Model version                  : 14.26\r\n * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024\r\n * C/C++ source code generated on : Tue Oct 14 20:08:12 2025\r\n *\r\n * Target selection: ert.tlc\r\n * Embedded hardware selection: NXP->Cortex-M4\r\n * Code generation objectives:\r\n *    1. Execution efficiency\r\n *    2. RAM efficiency\r\n *    3. Debugging\r\n * Validation result: Not run\r\n */\r\n\r\n#include \"ADM_Integrated_Logic.h\"\r\n#include <stdint.h>\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdbool.h>\r\n#include <stddef.h>\r\n\r\n/* Named constants for Chart: '<S12>/Chart' */\r\n#define IN_HAC_OFF                     ((uint8_t)1U)\r\n#define IN_HAC_ON                      ((uint8_t)2U)\r\n#define NumBitsPerChar                 8U\r\n\r\n/* Block signals and states (default storage) */\r\nDW_ADM_Integrated_Logic_T ADM_Integrated_Logic_DW;\r\n\r\n/* External inputs (root inport signals with default storage) */\r\nExtU_ADM_Integrated_Logic_T ADM_Integrated_Logic_U;\r\n\r\n/* External outputs (root outports fed by signals with default storage) */\r\nExtY_ADM_Integrated_Logic_T ADM_Integrated_Logic_Y;\r\n\r\n/* Real-time model */\r\nstatic RT_MODEL_ADM_Integrated_Logic_T ADM_Integrated_Logic_M_;\r\nRT_MODEL_ADM_Integrated_Logic_T *const ADM_Integrated_Logic_M =\r\n  &ADM_Integrated_Logic_M_;\r\nstatic void ADM_Integrated_Lo_Calculate_F_c(double rtu_W, double rtu_theta,\r\n  double *rty_F_c);\r\nstatic void ADM_Integrated__MATLABFunction1(double rtu_u, double *rty_y);\r\nstatic void ADM_Integrated__MATLABFunction2(double rtu_u, double *rty_y);\r\n\r\n/* Forward declaration for local functions */\r\nstatic void ADM_Integrated_Logic_mrdiv(const double A[6], const double B[4],\r\n  double Y[6]);\r\n\r\n#define NOT_USING_NONFINITE_LITERALS   1\r\n\r\nextern double rtInf;\r\nextern double rtMinusInf;\r\nextern double rtNaN;\r\nextern float rtInfF;\r\nextern float rtMinusInfF;\r\nextern float rtNaNF;\r\nstatic void rt_InitInfAndNaN(size_t realSize);\r\nstatic bool rtIsInf(double value);\r\nstatic bool rtIsInfF(float value);\r\nstatic bool rtIsNaN(double value);\r\nstatic bool rtIsNaNF(float value);\r\ntypedef struct {\r\n  struct {\r\n    uint32_t wordH;\r\n    uint32_t wordL;\r\n  } words;\r\n} BigEndianIEEEDouble;\r\n\r\ntypedef struct {\r\n  struct {\r\n    uint32_t wordL;\r\n    uint32_t wordH;\r\n  } words;\r\n} LittleEndianIEEEDouble;\r\n\r\ntypedef struct {\r\n  union {\r\n    float wordLreal;\r\n    uint32_t wordLuint;\r\n  } wordL;\r\n} IEEESingle;\r\n\r\ndouble rtInf;\r\ndouble rtMinusInf;\r\ndouble rtNaN;\r\nfloat rtInfF;\r\nfloat rtMinusInfF;\r\nfloat rtNaNF;\r\nstatic double rtGetInf(void);\r\nstatic float rtGetInfF(void);\r\nstatic double rtGetMinusInf(void);\r\nstatic float rtGetMinusInfF(void);\r\nstatic double rtGetNaN(void);\r\nstatic float rtGetNaNF(void);\r\n\r\n/*\r\n * Initialize the rtInf, rtMinusInf, and rtNaN needed by the\r\n * generated code. NaN is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic void rt_InitInfAndNaN(size_t realSize)\r\n{\r\n  (void) (realSize);\r\n  rtNaN = rtGetNaN();\r\n  rtNaNF = rtGetNaNF();\r\n  rtInf = rtGetInf();\r\n  rtInfF = rtGetInfF();\r\n  rtMinusInf = rtGetMinusInf();\r\n  rtMinusInfF = rtGetMinusInfF();\r\n}\r\n\r\n/* Test if value is infinite */\r\nstatic bool rtIsInf(double value)\r\n{\r\n  return (bool)((value==rtInf || value==rtMinusInf) ? 1U : 0U);\r\n}\r\n\r\n/* Test if single-precision value is infinite */\r\nstatic bool rtIsInfF(float value)\r\n{\r\n  return (bool)(((value)==rtInfF || (value)==rtMinusInfF) ? 1U : 0U);\r\n}\r\n\r\n/* Test if value is not a number */\r\nstatic bool rtIsNaN(double value)\r\n{\r\n  bool result = (bool) 0;\r\n  size_t bitsPerReal = sizeof(double) * (NumBitsPerChar);\r\n  if (bitsPerReal == 32U) {\r\n    result = rtIsNaNF((float)value);\r\n  } else {\r\n    union {\r\n      LittleEndianIEEEDouble bitVal;\r\n      double fltVal;\r\n    } tmpVal;\r\n\r\n    tmpVal.fltVal = value;\r\n    result = (bool)((tmpVal.bitVal.words.wordH & 0x7FF00000) == 0x7FF00000 &&\r\n                    ( (tmpVal.bitVal.words.wordH & 0x000FFFFF) != 0 ||\r\n                     (tmpVal.bitVal.words.wordL != 0) ));\r\n  }\r\n\r\n  return result;\r\n}\r\n\r\n/* Test if single-precision value is not a number */\r\nstatic bool rtIsNaNF(float value)\r\n{\r\n  IEEESingle tmp;\r\n  tmp.wordL.wordLreal = value;\r\n  return (bool)( (tmp.wordL.wordLuint & 0x7F800000) == 0x7F800000 &&\r\n                (tmp.wordL.wordLuint & 0x007FFFFF) != 0 );\r\n}\r\n\r\n/*\r\n * Initialize rtInf needed by the generated code.\r\n * Inf is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic double rtGetInf(void)\r\n{\r\n  size_t bitsPerReal = sizeof(double) * (NumBitsPerChar);\r\n  double inf = 0.0;\r\n  if (bitsPerReal == 32U) {\r\n    inf = rtGetInfF();\r\n  } else {\r\n    union {\r\n      LittleEndianIEEEDouble bitVal;\r\n      double fltVal;\r\n    } tmpVal;\r\n\r\n    tmpVal.bitVal.words.wordH = 0x7FF00000U;\r\n    tmpVal.bitVal.words.wordL = 0x00000000U;\r\n    inf = tmpVal.fltVal;\r\n  }\r\n\r\n  return inf;\r\n}\r\n\r\n/*\r\n * Initialize rtInfF needed by the generated code.\r\n * Inf is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic float rtGetInfF(void)\r\n{\r\n  IEEESingle infF;\r\n  infF.wordL.wordLuint = 0x7F800000U;\r\n  return infF.wordL.wordLreal;\r\n}\r\n\r\n/*\r\n * Initialize rtMinusInf needed by the generated code.\r\n * Inf is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic double rtGetMinusInf(void)\r\n{\r\n  size_t bitsPerReal = sizeof(double) * (NumBitsPerChar);\r\n  double minf = 0.0;\r\n  if (bitsPerReal == 32U) {\r\n    minf = rtGetMinusInfF();\r\n  } else {\r\n    union {\r\n      LittleEndianIEEEDouble bitVal;\r\n      double fltVal;\r\n    } tmpVal;\r\n\r\n    tmpVal.bitVal.words.wordH = 0xFFF00000U;\r\n    tmpVal.bitVal.words.wordL = 0x00000000U;\r\n    minf = tmpVal.fltVal;\r\n  }\r\n\r\n  return minf;\r\n}\r\n\r\n/*\r\n * Initialize rtMinusInfF needed by the generated code.\r\n * Inf is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic float rtGetMinusInfF(void)\r\n{\r\n  IEEESingle minfF;\r\n  minfF.wordL.wordLuint = 0xFF800000U;\r\n  return minfF.wordL.wordLreal;\r\n}\r\n\r\n/*\r\n * Initialize rtNaN needed by the generated code.\r\n * NaN is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic double rtGetNaN(void)\r\n{\r\n  size_t bitsPerReal = sizeof(double) * (NumBitsPerChar);\r\n  double nan = 0.0;\r\n  if (bitsPerReal == 32U) {\r\n    nan = rtGetNaNF();\r\n  } else {\r\n    union {\r\n      LittleEndianIEEEDouble bitVal;\r\n      double fltVal;\r\n    } tmpVal;\r\n\r\n    tmpVal.bitVal.words.wordH = 0xFFF80000U;\r\n    tmpVal.bitVal.words.wordL = 0x00000000U;\r\n    nan = tmpVal.fltVal;\r\n  }\r\n\r\n  return nan;\r\n}\r\n\r\n/*\r\n * Initialize rtNaNF needed by the generated code.\r\n * NaN is initialized as non-signaling. Assumes IEEE.\r\n */\r\nstatic float rtGetNaNF(void)\r\n{\r\n  IEEESingle nanF = { { 0.0F } };\r\n\r\n  nanF.wordL.wordLuint = 0xFFC00000U;\r\n  return nanF.wordL.wordLreal;\r\n}\r\n\r\n/*\r\n * Output and update for atomic system:\r\n *    '<S54>/Calculate_F_c'\r\n *    '<S54>/Calculate_F_c1'\r\n */\r\nstatic void ADM_Integrated_Lo_Calculate_F_c(double rtu_W, double rtu_theta,\r\n  double *rty_F_c)\r\n{\r\n  *rty_F_c = rtu_W * sin(rtu_theta);\r\n}\r\n\r\n/*\r\n * Output and update for atomic system:\r\n *    '<S1>/MATLAB Function1'\r\n *    '<S1>/MATLAB Function5'\r\n */\r\nstatic void ADM_Integrated__MATLABFunction1(double rtu_u, double *rty_y)\r\n{\r\n  *rty_y = rtu_u;\r\n  if (rtu_u < 140.0) {\r\n    *rty_y = 140.0;\r\n  }\r\n}\r\n\r\n/*\r\n * Output and update for atomic system:\r\n *    '<S1>/MATLAB Function2'\r\n *    '<S1>/MATLAB Function6'\r\n */\r\nstatic void ADM_Integrated__MATLABFunction2(double rtu_u, double *rty_y)\r\n{\r\n  *rty_y = rtu_u;\r\n  if (rtu_u > -140.0) {\r\n    *rty_y = -140.0;\r\n  }\r\n}\r\n\r\n/* Function for MATLAB Function: '<S1>/MATLAB Function' */\r\nstatic void ADM_Integrated_Logic_mrdiv(const double A[6], const double B[4],\r\n  double Y[6])\r\n{\r\n  double a21;\r\n  double a22;\r\n  double a22_tmp;\r\n  int32_t Y_tmp;\r\n  int32_t Y_tmp_0;\r\n  int32_t r1;\r\n  int32_t r2;\r\n  if (fabs(B[1]) > fabs(B[0])) {\r\n    r1 = 1;\r\n    r2 = 0;\r\n  } else {\r\n    r1 = 0;\r\n    r2 = 1;\r\n  }\r\n\r\n  a21 = B[r2] / B[r1];\r\n  a22_tmp = B[r1 + 2];\r\n  a22 = B[r2 + 2] - a22_tmp * a21;\r\n  Y[3 * r1] = A[0] / B[r1];\r\n  Y[3 * r2] = (A[3] - Y[3 * r1] * a22_tmp) / a22;\r\n  Y[3 * r1] -= Y[3 * r2] * a21;\r\n  Y_tmp = 3 * r1 + 1;\r\n  Y[Y_tmp] = A[1] / B[r1];\r\n  Y_tmp_0 = 3 * r2 + 1;\r\n  Y[Y_tmp_0] = (A[4] - Y[Y_tmp] * a22_tmp) / a22;\r\n  Y[Y_tmp] -= Y[Y_tmp_0] * a21;\r\n  Y_tmp = 3 * r1 + 2;\r\n  Y[Y_tmp] = A[2] / B[r1];\r\n  Y_tmp_0 = 3 * r2 + 2;\r\n  Y[Y_tmp_0] = (A[5] - Y[Y_tmp] * a22_tmp) / a22;\r\n  Y[Y_tmp] -= Y[Y_tmp_0] * a21;\r\n}\r\n\r\n/* Model step function */\r\nvoid ADM_Integrated_Logic_step(void)\r\n{\r\n  double P[9];\r\n  double P_last[9];\r\n  double P_pred[9];\r\n  double Q[9];\r\n  double b_I_0[9];\r\n  double P_pred_0[6];\r\n  double tmp_1[6];\r\n  double R[4];\r\n  double tmp_2[4];\r\n  double x_hat_pred[3];\r\n  double tmp[2];\r\n  double tmp_0[2];\r\n  double rtb_Add;\r\n  double rtb_Add1;\r\n  double rtb_Add3;\r\n  double rtb_BrakeTorque;\r\n  double rtb_Brake_Torque_Cmd;\r\n  double rtb_Desired_Torque;\r\n  double rtb_Error_m;\r\n  double rtb_Gain;\r\n  double rtb_Gain2_j;\r\n  double rtb_Gain_c;\r\n  double rtb_MotorTorque;\r\n  double rtb_Pitch_Angle;\r\n  double rtb_Product1_c;\r\n  double rtb_Product1_dc;\r\n  double rtb_Product1_h;\r\n  double rtb_Product1_j;\r\n  double rtb_Product1_lo;\r\n  double rtb_Product1_nu;\r\n  double rtb_Product1_p;\r\n  double rtb_RateLimiter;\r\n  double rtb_Sum1_aj;\r\n  double rtb_Sum1_i2;\r\n  double rtb_Sum1_lm;\r\n  double rtb_Sum1_o1;\r\n  double rtb_Sum1_p;\r\n  double rtb_Switch2;\r\n  double rtb_TSamp;\r\n  double rtb_Target_RPM;\r\n  double rtb_UkYk1_j;\r\n  double rtb_Vx_Cmd_R;\r\n  double rtb_y_c;\r\n  int32_t H;\r\n  int32_t H_0;\r\n  int32_t P_pred_tmp;\r\n  int32_t d_k;\r\n  int32_t idx;\r\n  int32_t j;\r\n  int8_t b_I[9];\r\n  int8_t K_ss_tmp[6];\r\n  int8_t K_ss_tmp_0;\r\n  int8_t K_ss_tmp_1;\r\n  int8_t K_ss_tmp_2;\r\n  bool rtb_Compare;\r\n  bool rtb_Compare_d;\r\n  static const double b[9] = { 1.0, 0.0, 0.0, 0.002, 1.0, 0.0,\r\n    -0.019620000000000002, 0.0, 1.0 };\r\n\r\n  static const int8_t c[6] = { 1, 0, 0, 1, 0, 0 };\r\n\r\n  double rtb_Add1_tmp;\r\n  bool exitg1;\r\n  bool exitg2;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function' */\r\n  if (!ADM_Integrated_Logic_DW.K_ss_not_empty) {\r\n    memcpy(&ADM_Integrated_Logic_DW.A[0], &b[0], 9U * sizeof(double));\r\n    for (idx = 0; idx < 6; idx++) {\r\n      ADM_Integrated_Logic_DW.H[idx] = c[idx];\r\n    }\r\n\r\n    memset(&Q[0], 0, 9U * sizeof(double));\r\n    Q[0] = 0.01;\r\n    Q[4] = 0.1;\r\n    Q[8] = 0.001;\r\n    R[1] = 0.0;\r\n    R[2] = 0.0;\r\n    R[0] = 0.1;\r\n    R[3] = 0.1;\r\n    memset(&P[0], 0, 9U * sizeof(double));\r\n    P[0] = 1.0;\r\n    P[4] = 1.0;\r\n    P[8] = 1.0;\r\n    j = 0;\r\n    exitg1 = false;\r\n    while ((!exitg1) && (j < 100)) {\r\n      memcpy(&P_last[0], &P[0], 9U * sizeof(double));\r\n      for (idx = 0; idx < 3; idx++) {\r\n        rtb_Gain = ADM_Integrated_Logic_DW.A[idx + 3];\r\n        rtb_Switch2 = ADM_Integrated_Logic_DW.A[idx];\r\n        rtb_Gain2_j = ADM_Integrated_Logic_DW.A[idx + 6];\r\n        for (d_k = 0; d_k < 3; d_k++) {\r\n          b_I_0[idx + 3 * d_k] = (P[3 * d_k + 1] * rtb_Gain + P[3 * d_k] *\r\n            rtb_Switch2) + P[3 * d_k + 2] * rtb_Gain2_j;\r\n        }\r\n\r\n        rtb_Add = b_I_0[idx + 3];\r\n        rtb_Gain = b_I_0[idx];\r\n        rtb_Switch2 = b_I_0[idx + 6];\r\n        for (d_k = 0; d_k < 3; d_k++) {\r\n          P_pred_tmp = 3 * d_k + idx;\r\n          P_pred[P_pred_tmp] = ((ADM_Integrated_Logic_DW.A[d_k + 3] * rtb_Add +\r\n            rtb_Gain * ADM_Integrated_Logic_DW.A[d_k]) +\r\n                                ADM_Integrated_Logic_DW.A[d_k + 6] * rtb_Switch2)\r\n            + Q[P_pred_tmp];\r\n        }\r\n      }\r\n\r\n      for (idx = 0; idx < 9; idx++) {\r\n        b_I[idx] = 0;\r\n      }\r\n\r\n      b_I[0] = 1;\r\n      b_I[4] = 1;\r\n      b_I[8] = 1;\r\n      for (idx = 0; idx < 2; idx++) {\r\n        P_pred_tmp = (int32_t)ADM_Integrated_Logic_DW.H[idx + 2];\r\n        H = (int32_t)ADM_Integrated_Logic_DW.H[idx];\r\n        H_0 = (int32_t)ADM_Integrated_Logic_DW.H[idx + 4];\r\n        for (d_k = 0; d_k < 3; d_k++) {\r\n          tmp_1[idx + (d_k << 1)] = (P_pred[3 * d_k + 1] * (double)P_pred_tmp +\r\n            P_pred[3 * d_k] * (double)H) + P_pred[3 * d_k + 2] * (double)H_0;\r\n        }\r\n      }\r\n\r\n      for (idx = 0; idx < 3; idx++) {\r\n        rtb_Switch2 = P_pred[idx + 3];\r\n        rtb_Gain = P_pred[idx];\r\n        rtb_Gain2_j = P_pred[idx + 6];\r\n        for (d_k = 0; d_k < 2; d_k++) {\r\n          P_pred_0[idx + 3 * d_k] = (ADM_Integrated_Logic_DW.H[d_k + 2] *\r\n            rtb_Switch2 + rtb_Gain * ADM_Integrated_Logic_DW.H[d_k]) +\r\n            ADM_Integrated_Logic_DW.H[d_k + 4] * rtb_Gain2_j;\r\n        }\r\n      }\r\n\r\n      for (idx = 0; idx < 2; idx++) {\r\n        rtb_Add = tmp_1[idx + 2];\r\n        rtb_Gain = tmp_1[idx];\r\n        rtb_Switch2 = tmp_1[idx + 4];\r\n        for (d_k = 0; d_k < 2; d_k++) {\r\n          P_pred_tmp = (d_k << 1) + idx;\r\n          tmp_2[P_pred_tmp] = ((ADM_Integrated_Logic_DW.H[d_k + 2] * rtb_Add +\r\n                                rtb_Gain * ADM_Integrated_Logic_DW.H[d_k]) +\r\n                               ADM_Integrated_Logic_DW.H[d_k + 4] * rtb_Switch2)\r\n            + R[P_pred_tmp];\r\n        }\r\n      }\r\n\r\n      ADM_Integrated_Logic_mrdiv(P_pred_0, tmp_2, tmp_1);\r\n      for (idx = 0; idx < 3; idx++) {\r\n        rtb_Add = tmp_1[idx + 3];\r\n        rtb_Gain = tmp_1[idx];\r\n        for (d_k = 0; d_k < 3; d_k++) {\r\n          P_pred_tmp = d_k << 1;\r\n          H = 3 * d_k + idx;\r\n          b_I_0[H] = (double)b_I[H] - (ADM_Integrated_Logic_DW.H[P_pred_tmp + 1]\r\n            * rtb_Add + ADM_Integrated_Logic_DW.H[P_pred_tmp] * rtb_Gain);\r\n        }\r\n\r\n        rtb_Gain = b_I_0[idx + 3];\r\n        rtb_Switch2 = b_I_0[idx];\r\n        rtb_Gain2_j = b_I_0[idx + 6];\r\n        for (d_k = 0; d_k < 3; d_k++) {\r\n          P[idx + 3 * d_k] = (P_pred[3 * d_k + 1] * rtb_Gain + P_pred[3 * d_k] *\r\n                              rtb_Switch2) + P_pred[3 * d_k + 2] * rtb_Gain2_j;\r\n        }\r\n      }\r\n\r\n      for (idx = 0; idx < 9; idx++) {\r\n        rtb_Gain = P[idx] - P_last[idx];\r\n        P_last[idx] = rtb_Gain;\r\n        P_pred[idx] = fabs(rtb_Gain);\r\n      }\r\n\r\n      if (!rtIsNaN(P_pred[0])) {\r\n        idx = 1;\r\n      } else {\r\n        idx = 0;\r\n        d_k = 2;\r\n        exitg2 = false;\r\n        while ((!exitg2) && (d_k < 10)) {\r\n          if (!rtIsNaN(P_pred[d_k - 1])) {\r\n            idx = d_k;\r\n            exitg2 = true;\r\n          } else {\r\n            d_k++;\r\n          }\r\n        }\r\n      }\r\n\r\n      if (idx == 0) {\r\n        rtb_Gain = P_pred[0];\r\n      } else {\r\n        rtb_Gain = P_pred[idx - 1];\r\n        for (d_k = idx + 1; d_k < 10; d_k++) {\r\n          rtb_Switch2 = P_pred[d_k - 1];\r\n          if (rtb_Gain < rtb_Switch2) {\r\n            rtb_Gain = rtb_Switch2;\r\n          }\r\n        }\r\n      }\r\n\r\n      if (rtb_Gain < 1.0E-6) {\r\n        exitg1 = true;\r\n      } else {\r\n        j++;\r\n      }\r\n    }\r\n\r\n    for (idx = 0; idx < 3; idx++) {\r\n      rtb_Gain = ADM_Integrated_Logic_DW.A[idx + 3];\r\n      rtb_Switch2 = ADM_Integrated_Logic_DW.A[idx];\r\n      rtb_Gain2_j = ADM_Integrated_Logic_DW.A[idx + 6];\r\n      for (d_k = 0; d_k < 3; d_k++) {\r\n        b_I_0[idx + 3 * d_k] = (P[3 * d_k + 1] * rtb_Gain + P[3 * d_k] *\r\n          rtb_Switch2) + P[3 * d_k + 2] * rtb_Gain2_j;\r\n      }\r\n\r\n      rtb_Add = b_I_0[idx + 3];\r\n      rtb_Gain = b_I_0[idx];\r\n      rtb_Switch2 = b_I_0[idx + 6];\r\n      for (d_k = 0; d_k < 3; d_k++) {\r\n        P_pred_tmp = 3 * d_k + idx;\r\n        P_pred[P_pred_tmp] = ((ADM_Integrated_Logic_DW.A[d_k + 3] * rtb_Add +\r\n          rtb_Gain * ADM_Integrated_Logic_DW.A[d_k]) +\r\n                              ADM_Integrated_Logic_DW.A[d_k + 6] * rtb_Switch2)\r\n          + Q[P_pred_tmp];\r\n      }\r\n    }\r\n\r\n    for (idx = 0; idx < 2; idx++) {\r\n      for (d_k = 0; d_k < 3; d_k++) {\r\n        j = (d_k << 1) + idx;\r\n        K_ss_tmp[d_k + 3 * idx] = (int8_t)ADM_Integrated_Logic_DW.H[j];\r\n        tmp_1[j] = (P_pred[3 * d_k + 1] * ADM_Integrated_Logic_DW.H[idx + 2] +\r\n                    P_pred[3 * d_k] * ADM_Integrated_Logic_DW.H[idx]) + P_pred[3\r\n          * d_k + 2] * ADM_Integrated_Logic_DW.H[idx + 4];\r\n      }\r\n\r\n      K_ss_tmp_0 = K_ss_tmp[3 * idx + 1];\r\n      K_ss_tmp_1 = K_ss_tmp[3 * idx];\r\n      K_ss_tmp_2 = K_ss_tmp[3 * idx + 2];\r\n      for (d_k = 0; d_k < 3; d_k++) {\r\n        P_pred_0[d_k + 3 * idx] = (P_pred[d_k + 3] * (double)K_ss_tmp_0 +\r\n          (double)K_ss_tmp_1 * P_pred[d_k]) + P_pred[d_k + 6] * (double)\r\n          K_ss_tmp_2;\r\n      }\r\n    }\r\n\r\n    for (idx = 0; idx < 2; idx++) {\r\n      rtb_Add = tmp_1[idx + 2];\r\n      rtb_Gain = tmp_1[idx];\r\n      rtb_Switch2 = tmp_1[idx + 4];\r\n      for (d_k = 0; d_k < 2; d_k++) {\r\n        P_pred_tmp = (d_k << 1) + idx;\r\n        tmp_2[P_pred_tmp] = (((double)K_ss_tmp[3 * d_k + 1] * rtb_Add + (double)\r\n                              K_ss_tmp[3 * d_k] * rtb_Gain) + (double)K_ss_tmp[3\r\n                             * d_k + 2] * rtb_Switch2) + R[P_pred_tmp];\r\n      }\r\n    }\r\n\r\n    ADM_Integrated_Logic_mrdiv(P_pred_0, tmp_2, ADM_Integrated_Logic_DW.K_ss);\r\n    ADM_Integrated_Logic_DW.K_ss_not_empty = true;\r\n    ADM_Integrated_Logic_DW.x_hat[0] = 0.0;\r\n    ADM_Integrated_Logic_DW.x_hat[1] = 0.0;\r\n    ADM_Integrated_Logic_DW.x_hat[2] = 0.0;\r\n  }\r\n\r\n  rtb_Gain = ADM_Integrated_Logic_DW.x_hat[1];\r\n  rtb_Switch2 = ADM_Integrated_Logic_DW.x_hat[0];\r\n  rtb_Gain2_j = ADM_Integrated_Logic_DW.x_hat[2];\r\n  for (idx = 0; idx < 3; idx++) {\r\n    x_hat_pred[idx] = (ADM_Integrated_Logic_DW.A[idx + 3] * rtb_Gain +\r\n                       ADM_Integrated_Logic_DW.A[idx] * rtb_Switch2) +\r\n      ADM_Integrated_Logic_DW.A[idx + 6] * rtb_Gain2_j;\r\n  }\r\n\r\n  /* SignalConversion generated from: '<S15>/ SFunction ' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   *  MATLAB Function: '<S1>/MATLAB Function'\r\n   */\r\n  tmp[0] = ADM_Integrated_Logic_U.GV_Vx_Fbk;\r\n  tmp[1] = ADM_Integrated_Logic_U.GV_IMU_AX_Val;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function' */\r\n  rtb_Gain = x_hat_pred[1];\r\n  rtb_Switch2 = x_hat_pred[0];\r\n  rtb_Gain2_j = x_hat_pred[2];\r\n  for (idx = 0; idx < 2; idx++) {\r\n    tmp_0[idx] = tmp[idx] - ((ADM_Integrated_Logic_DW.H[idx + 2] * rtb_Gain +\r\n      ADM_Integrated_Logic_DW.H[idx] * rtb_Switch2) +\r\n      ADM_Integrated_Logic_DW.H[idx + 4] * rtb_Gain2_j);\r\n  }\r\n\r\n  rtb_Add = tmp_0[1];\r\n  rtb_Gain = tmp_0[0];\r\n  for (idx = 0; idx < 3; idx++) {\r\n    ADM_Integrated_Logic_DW.x_hat[idx] = (ADM_Integrated_Logic_DW.K_ss[idx + 3] *\r\n      rtb_Add + ADM_Integrated_Logic_DW.K_ss[idx] * rtb_Gain) + x_hat_pred[idx];\r\n  }\r\n\r\n  /* RelationalOperator: '<S4>/Compare' incorporates:\r\n   *  Constant: '<S4>/Constant'\r\n   *  Inport: '<Root>/GV_Drive_Mode'\r\n   */\r\n  rtb_Compare = (ADM_Integrated_Logic_U.GV_Drive_Mode == 2.0);\r\n\r\n  /* Gain: '<S2>/Gain' incorporates:\r\n   *  Inport: '<Root>/GV_Drive_ACC_Cmd'\r\n   */\r\n  rtb_Gain = 9.80665 * ADM_Integrated_Logic_U.GV_Drive_ACC_Cmd;\r\n\r\n  /* Switch: '<S27>/Switch2' incorporates:\r\n   *  Gain: '<S2>/Gain2'\r\n   *  Inport: '<Root>/GV_VCU_Acc_Limit'\r\n   *  RelationalOperator: '<S27>/LowerRelop1'\r\n   *  RelationalOperator: '<S27>/UpperRelop'\r\n   *  Switch: '<S27>/Switch'\r\n   */\r\n  if (rtb_Gain > ADM_Integrated_Logic_U.GV_VCU_Acc_Limit) {\r\n    rtb_Switch2 = ADM_Integrated_Logic_U.GV_VCU_Acc_Limit;\r\n  } else if (rtb_Gain < -ADM_Integrated_Logic_U.GV_VCU_Acc_Limit) {\r\n    /* Switch: '<S27>/Switch' incorporates:\r\n     *  Gain: '<S2>/Gain2'\r\n     */\r\n    rtb_Switch2 = -ADM_Integrated_Logic_U.GV_VCU_Acc_Limit;\r\n  } else {\r\n    rtb_Switch2 = rtb_Gain;\r\n  }\r\n\r\n  /* End of Switch: '<S27>/Switch2' */\r\n\r\n  /* Gain: '<S25>/Gain' */\r\n  rtb_Switch2 *= 1300.0;\r\n\r\n  /* Product: '<S14>/Product1' incorporates:\r\n   *  Constant: '<S14>/Constant'\r\n   *  Gain: '<S14>/gain'\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   *  Product: '<S14>/Product11'\r\n   *  Sum: '<S14>/Sum1'\r\n   *  Sum: '<S14>/Sum2'\r\n   *  Sum: '<S14>/Sum3'\r\n   *  Sum: '<S14>/Sum4'\r\n   *  UnitDelay: '<S14>/d'\r\n   *  UnitDelay: '<S14>/d1'\r\n   */\r\n  rtb_Gain = ((ADM_Integrated_Logic_U.GV_IMU_AX_Val +\r\n               ADM_Integrated_Logic_DW.d1_DSTATE) * 0.002 + 0.63461977236758138 *\r\n              ADM_Integrated_Logic_DW.d_DSTATE) / 0.63861977236758138;\r\n\r\n  /* Sum: '<S25>/Subtract' incorporates:\r\n   *  Gain: '<S25>/Gain1'\r\n   *  Gain: '<S2>/Gain1'\r\n   */\r\n  rtb_Gain2_j = rtb_Switch2 - 9.80665 * rtb_Gain * 1300.0;\r\n\r\n  /* SampleTimeMath: '<S28>/TSamp'\r\n   *\r\n   * About '<S28>/TSamp':\r\n   *  y = u * K where K = 1 / ( w * Ts )\r\n   *   */\r\n  rtb_TSamp = rtb_Gain2_j * 500.0;\r\n\r\n  /* Sum: '<S25>/Sum1' incorporates:\r\n   *  Constant: '<S1>/Constant10'\r\n   *  Constant: '<S1>/Constant11'\r\n   *  Constant: '<S1>/Constant13'\r\n   *  DiscreteIntegrator: '<S25>/Discrete-Time Integrator'\r\n   *  Gain: '<S25>/Gain2'\r\n   *  Product: '<S25>/D controller'\r\n   *  Product: '<S25>/I controller'\r\n   *  Product: '<S25>/P controller'\r\n   *  Sum: '<S25>/Subtract1'\r\n   *  Sum: '<S28>/Diff'\r\n   *  UnitDelay: '<S28>/UD'\r\n   *\r\n   * Block description for '<S28>/Diff':\r\n   *\r\n   *  Add in CPU\r\n   *\r\n   * Block description for '<S28>/UD':\r\n   *\r\n   *  Store in Global RAM\r\n   */\r\n  rtb_Switch2 = ((0.05 * rtb_Gain2_j +\r\n                  ADM_Integrated_Logic_DW.DiscreteTimeIntegrator_DSTATE * 0.1) +\r\n                 (rtb_TSamp - ADM_Integrated_Logic_DW.UD_DSTATE) * 0.0) + 0.0 *\r\n    rtb_Switch2;\r\n\r\n  /* RateLimiter: '<S2>/Rate Limiter' */\r\n  rtb_Product1_c = rtb_Switch2 - ADM_Integrated_Logic_DW.PrevY;\r\n  if (rtb_Product1_c > 1.0) {\r\n    rtb_RateLimiter = ADM_Integrated_Logic_DW.PrevY + 1.0;\r\n  } else if (rtb_Product1_c < -0.3) {\r\n    rtb_RateLimiter = ADM_Integrated_Logic_DW.PrevY - 0.3;\r\n  } else {\r\n    rtb_RateLimiter = rtb_Switch2;\r\n  }\r\n\r\n  ADM_Integrated_Logic_DW.PrevY = rtb_RateLimiter;\r\n\r\n  /* End of RateLimiter: '<S2>/Rate Limiter' */\r\n\r\n  /* MATLAB Function: '<S2>/MATLAB Function' */\r\n  if (rtb_RateLimiter >= 0.0) {\r\n    rtb_MotorTorque = rtb_RateLimiter;\r\n    rtb_BrakeTorque = 0.0;\r\n  } else {\r\n    rtb_MotorTorque = 0.0;\r\n    rtb_BrakeTorque = -rtb_RateLimiter;\r\n  }\r\n\r\n  /* End of MATLAB Function: '<S2>/MATLAB Function' */\r\n\r\n  /* RelationalOperator: '<S50>/Compare' incorporates:\r\n   *  Constant: '<S50>/Constant'\r\n   *  Inport: '<Root>/GV_BrakeTorqueCommand'\r\n   */\r\n  rtb_Compare_d = (ADM_Integrated_Logic_U.GV_BrakeTorqueCommand >= 100.0);\r\n\r\n  /* Delay: '<S11>/Memory' */\r\n  rtb_RateLimiter = ADM_Integrated_Logic_DW.Memory_DSTATE;\r\n\r\n  /* MATLAB Function: '<S11>/Gear_FUNCTION1' incorporates:\r\n   *  Inport: '<Root>/GV_VCU_GearSelStat'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   */\r\n  if (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 0.0) {\r\n    if ((ADM_Integrated_Logic_U.GV_Vx_Fbk <= 0.0) && rtb_Compare_d) {\r\n      rtb_RateLimiter = 0.0;\r\n    }\r\n  } else {\r\n    switch ((int32_t)rtb_RateLimiter) {\r\n     case 0:\r\n      if ((ADM_Integrated_Logic_U.GV_Vx_Fbk <= 0.0) &&\r\n          ((ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 1.0) ||\r\n           (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 3.0) ||\r\n           (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 2.0))) {\r\n        rtb_RateLimiter = 2.0;\r\n      }\r\n      break;\r\n\r\n     case 1:\r\n      if (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 2.0) {\r\n        rtb_RateLimiter = 2.0;\r\n      }\r\n      break;\r\n\r\n     case 2:\r\n      if ((ADM_Integrated_Logic_U.GV_Vx_Fbk <= 0.0) && rtb_Compare_d) {\r\n        if (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 1.0) {\r\n          rtb_RateLimiter = 1.0;\r\n        } else if (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 3.0) {\r\n          rtb_RateLimiter = 3.0;\r\n        }\r\n      }\r\n      break;\r\n\r\n     case 3:\r\n      if (ADM_Integrated_Logic_U.GV_VCU_GearSelStat == 2.0) {\r\n        rtb_RateLimiter = 2.0;\r\n      }\r\n      break;\r\n    }\r\n  }\r\n\r\n  /* End of MATLAB Function: '<S11>/Gear_FUNCTION1' */\r\n\r\n  /* MATLAB Function: '<S24>/Vx_OutPut_Function' incorporates:\r\n   *  Constant: '<S69>/Constant'\r\n   *  Inport: '<Root>/GV_BrakeTorqueCommand'\r\n   *  Inport: '<Root>/GV_Vx_Command'\r\n   *  Inport: '<Root>/GV_Vx_Limit'\r\n   *  RelationalOperator: '<S69>/Compare'\r\n   */\r\n  if (!(ADM_Integrated_Logic_U.GV_BrakeTorqueCommand >= 50.0)) {\r\n    if (ADM_Integrated_Logic_U.GV_Vx_Limit <=\r\n        ADM_Integrated_Logic_U.GV_Vx_Command) {\r\n      rtb_Add = ADM_Integrated_Logic_U.GV_Vx_Limit;\r\n    } else {\r\n      rtb_Add = ADM_Integrated_Logic_U.GV_Vx_Command;\r\n    }\r\n  } else {\r\n    rtb_Add = 0.0;\r\n  }\r\n\r\n  /* Product: '<S24>/Product' incorporates:\r\n   *  MATLAB Function: '<S24>/Vx_OutPut_Function'\r\n   *  Switch: '<S24>/Switch'\r\n   */\r\n  rtb_Switch2 = rtb_Add * (double)!rtb_Compare;\r\n\r\n  /* RateLimiter: '<S24>/Input_Vx_RateLimiter' */\r\n  rtb_Product1_c = rtb_Switch2 - ADM_Integrated_Logic_DW.PrevY_a;\r\n  if (rtb_Product1_c > 0.004) {\r\n    rtb_Vx_Cmd_R = ADM_Integrated_Logic_DW.PrevY_a + 0.004;\r\n  } else if (rtb_Product1_c < -0.008) {\r\n    rtb_Vx_Cmd_R = ADM_Integrated_Logic_DW.PrevY_a - 0.008;\r\n  } else {\r\n    rtb_Vx_Cmd_R = rtb_Switch2;\r\n  }\r\n\r\n  ADM_Integrated_Logic_DW.PrevY_a = rtb_Vx_Cmd_R;\r\n\r\n  /* End of RateLimiter: '<S24>/Input_Vx_RateLimiter' */\r\n\r\n  /* MATLAB Function: '<S7>/Target_RPM' */\r\n  if (rtb_RateLimiter == 0.0) {\r\n    idx = 0;\r\n  } else if (rtb_RateLimiter == 2.0) {\r\n    idx = 0;\r\n  } else if (rtb_RateLimiter == 1.0) {\r\n    idx = -1;\r\n  } else {\r\n    idx = (rtb_RateLimiter == 3.0);\r\n  }\r\n\r\n  rtb_Target_RPM = rtb_Vx_Cmd_R * 1000.0 / 3600.0 * 11.93 * 60.0 /\r\n    1.7013672006633955 * (double)idx;\r\n\r\n  /* End of MATLAB Function: '<S7>/Target_RPM' */\r\n\r\n  /* RateLimiter: '<S7>/TargetSpd_RateLimiter' */\r\n  rtb_Product1_c = rtb_Target_RPM - ADM_Integrated_Logic_DW.PrevY_ak;\r\n  if (rtb_Product1_c > 0.4) {\r\n    rtb_Target_RPM = ADM_Integrated_Logic_DW.PrevY_ak + 0.4;\r\n  } else if (rtb_Product1_c < -0.8) {\r\n    rtb_Target_RPM = ADM_Integrated_Logic_DW.PrevY_ak - 0.8;\r\n  }\r\n\r\n  ADM_Integrated_Logic_DW.PrevY_ak = rtb_Target_RPM;\r\n\r\n  /* End of RateLimiter: '<S7>/TargetSpd_RateLimiter' */\r\n\r\n  /* Product: '<S34>/Product1' incorporates:\r\n   *  Constant: '<S34>/Constant'\r\n   *  Gain: '<S34>/gain'\r\n   *  Product: '<S34>/Product11'\r\n   *  Sum: '<S34>/Sum1'\r\n   *  Sum: '<S34>/Sum2'\r\n   *  Sum: '<S34>/Sum3'\r\n   *  Sum: '<S34>/Sum4'\r\n   *  UnitDelay: '<S34>/d'\r\n   *  UnitDelay: '<S34>/d1'\r\n   */\r\n  rtb_Product1_j = ((rtb_Target_RPM + ADM_Integrated_Logic_DW.d1_DSTATE_c) *\r\n                    0.002 + 0.1041032953945969 *\r\n                    ADM_Integrated_Logic_DW.d_DSTATE_l) / 0.1081032953945969;\r\n\r\n  /* Sum: '<S44>/Sum1' incorporates:\r\n   *  Gain: '<S44>/gain'\r\n   *  Sum: '<S44>/Sum2'\r\n   *  UnitDelay: '<S44>/d'\r\n   *  UnitDelay: '<S44>/d1'\r\n   */\r\n  rtb_Sum1_i2 = (rtb_Product1_j - ADM_Integrated_Logic_DW.d_DSTATE_i) * 1000.0 -\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_p;\r\n\r\n  /* Sum: '<S45>/Sum1' incorporates:\r\n   *  Gain: '<S45>/gain'\r\n   *  Sum: '<S45>/Sum2'\r\n   *  UnitDelay: '<S45>/d'\r\n   *  UnitDelay: '<S45>/d1'\r\n   */\r\n  rtb_Sum1_o1 = (rtb_Sum1_i2 - ADM_Integrated_Logic_DW.d_DSTATE_c) * 1000.0 -\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_h;\r\n\r\n  /* Sum: '<S46>/Sum1' incorporates:\r\n   *  Gain: '<S46>/gain'\r\n   *  Sum: '<S46>/Sum2'\r\n   *  UnitDelay: '<S46>/d'\r\n   *  UnitDelay: '<S46>/d1'\r\n   */\r\n  rtb_Sum1_lm = (rtb_Sum1_o1 - ADM_Integrated_Logic_DW.d_DSTATE_d) * 1000.0 -\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_l;\r\n\r\n  /* Gain: '<S42>/Gain' incorporates:\r\n   *  Constant: '<S42>/Constant3'\r\n   *  Constant: '<S42>/Constant4'\r\n   *  Constant: '<S42>/Constant5'\r\n   *  Product: '<S42>/Product'\r\n   *  Product: '<S42>/Product1'\r\n   *  Product: '<S42>/Product2'\r\n   *  Sum: '<S42>/Add5'\r\n   */\r\n  rtb_Gain_c = (((156.8 * rtb_Product1_j + 212.8 * rtb_Sum1_i2) + 21.8 *\r\n                 rtb_Sum1_o1) + rtb_Sum1_lm) * 9.44822373393802E-6;\r\n\r\n  /* Product: '<S48>/Product1' incorporates:\r\n   *  Constant: '<S48>/Constant1'\r\n   *  Constant: '<S48>/Constant2'\r\n   *  Delay: '<S48>/Delay'\r\n   *  Delay: '<S48>/Delay1'\r\n   *  Delay: '<S48>/Delay2'\r\n   *  Delay: '<S48>/Delay3'\r\n   *  Gain: '<S48>/gain1'\r\n   *  Gain: '<S48>/gain3'\r\n   *  Product: '<S48>/x(n), x(n-1), x(n-2)'\r\n   *  Product: '<S48>/y(n-1)'\r\n   *  Product: '<S48>/y(n-2)'\r\n   *  Sum: '<S48>/Sum1'\r\n   *  Sum: '<S48>/Sum2'\r\n   *  Sum: '<S48>/Sum3'\r\n   *  Sum: '<S48>/Sum4'\r\n   *  Sum: '<S48>/Sum5'\r\n   *  Sum: '<S48>/Sum6'\r\n   */\r\n  rtb_Product1_dc = ((((2.0 * ADM_Integrated_Logic_DW.Delay1_DSTATE + rtb_Gain_c)\r\n                       + ADM_Integrated_Logic_DW.Delay_DSTATE[0]) *\r\n                      0.39478417604357435 - -7.2104316479128512 *\r\n                      ADM_Integrated_Logic_DW.Delay2_DSTATE) -\r\n                     2.6178993711731877 * ADM_Integrated_Logic_DW.Delay3_DSTATE\r\n                     [0]) / 6.1716689809139611;\r\n\r\n  /* Product: '<S47>/Product1' incorporates:\r\n   *  Constant: '<S47>/Constant'\r\n   *  Gain: '<S47>/gain'\r\n   *  Product: '<S47>/Product11'\r\n   *  Sum: '<S47>/Sum1'\r\n   *  Sum: '<S47>/Sum2'\r\n   *  Sum: '<S47>/Sum3'\r\n   *  Sum: '<S47>/Sum4'\r\n   *  UnitDelay: '<S47>/d'\r\n   *  UnitDelay: '<S47>/d1'\r\n   */\r\n  rtb_Product1_h = ((rtb_Product1_dc + ADM_Integrated_Logic_DW.d1_DSTATE_e) *\r\n                    0.002 + 0.00861032953945969 *\r\n                    ADM_Integrated_Logic_DW.d_DSTATE_ij) / 0.01261032953945969;\r\n\r\n  /* Sum: '<S7>/Subtract' incorporates:\r\n   *  Inport: '<Root>/GV_MCU_RPM'\r\n   *  MultiPortSwitch: '<S41>/Multiport Switch1'\r\n   */\r\n  rtb_Error_m = rtb_Product1_j - ADM_Integrated_Logic_U.GV_MCU_RPM;\r\n\r\n  /* Saturate: '<S7>/Error_Saturation' incorporates:\r\n   *  MultiPortSwitch: '<S41>/Multiport Switch1'\r\n   */\r\n  if (rtb_Error_m > 2000.0) {\r\n    rtb_Error_m = 2000.0;\r\n  } else if (rtb_Error_m < -2000.0) {\r\n    rtb_Error_m = -2000.0;\r\n  }\r\n\r\n  /* End of Saturate: '<S7>/Error_Saturation' */\r\n\r\n  /* DeadZone: '<S31>/Dead Zone' incorporates:\r\n   *  MultiPortSwitch: '<S41>/Multiport Switch1'\r\n   */\r\n  if (rtb_Error_m > 50.0) {\r\n    rtb_Add = rtb_Error_m - 50.0;\r\n  } else if (rtb_Error_m >= -50.0) {\r\n    rtb_Add = 0.0;\r\n  } else {\r\n    rtb_Add = rtb_Error_m - -50.0;\r\n  }\r\n\r\n  /* Sum: '<S36>/Sum1' incorporates:\r\n   *  Gain: '<S36>/gain'\r\n   *  Sum: '<S36>/Sum2'\r\n   *  UnitDelay: '<S36>/d'\r\n   *  UnitDelay: '<S36>/d1'\r\n   */\r\n  rtb_Error_m = (rtb_Product1_j - ADM_Integrated_Logic_DW.d_DSTATE_ir) * 1000.0\r\n    - ADM_Integrated_Logic_DW.d1_DSTATE_o;\r\n\r\n  /* Sum: '<S37>/Sum1' incorporates:\r\n   *  Gain: '<S37>/gain'\r\n   *  Sum: '<S37>/Sum2'\r\n   *  UnitDelay: '<S37>/d'\r\n   *  UnitDelay: '<S37>/d1'\r\n   */\r\n  rtb_Sum1_aj = (rtb_Error_m - ADM_Integrated_Logic_DW.d_DSTATE_m) * 1000.0 -\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_hm;\r\n\r\n  /* Sum: '<S38>/Sum1' incorporates:\r\n   *  Gain: '<S38>/gain'\r\n   *  Sum: '<S38>/Sum2'\r\n   *  UnitDelay: '<S38>/d'\r\n   *  UnitDelay: '<S38>/d1'\r\n   */\r\n  rtb_Sum1_p = (rtb_Sum1_aj - ADM_Integrated_Logic_DW.d_DSTATE_mw) * 1000.0 -\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_g;\r\n\r\n  /* Sum: '<S29>/Add3' incorporates:\r\n   *  Constant: '<S29>/Constant3'\r\n   *  Constant: '<S29>/Constant4'\r\n   *  Constant: '<S29>/Constant5'\r\n   *  Gain: '<S29>/Gain'\r\n   *  Memory: '<S7>/Memory'\r\n   *  Product: '<S29>/Product2'\r\n   *  Product: '<S29>/Product3'\r\n   *  Product: '<S29>/Product4'\r\n   *  Sum: '<S29>/Add2'\r\n   */\r\n  rtb_Add3 = (((156.8 * rtb_Product1_j + 212.8 * rtb_Error_m) + 21.8 *\r\n               rtb_Sum1_aj) + rtb_Sum1_p) * 9.44822373393802E-6 -\r\n    ADM_Integrated_Logic_DW.Memory_PreviousInput;\r\n\r\n  /* Product: '<S39>/Product1' incorporates:\r\n   *  Constant: '<S39>/Constant'\r\n   *  Gain: '<S39>/gain'\r\n   *  Product: '<S39>/Product11'\r\n   *  Sum: '<S39>/Sum1'\r\n   *  Sum: '<S39>/Sum2'\r\n   *  Sum: '<S39>/Sum3'\r\n   *  Sum: '<S39>/Sum4'\r\n   *  UnitDelay: '<S39>/d'\r\n   *  UnitDelay: '<S39>/d1'\r\n   */\r\n  rtb_Product1_nu = ((rtb_Add3 + ADM_Integrated_Logic_DW.d1_DSTATE_ej) * 0.002 +\r\n                     0.029830988618379066 * ADM_Integrated_Logic_DW.d_DSTATE_j) /\r\n    0.03383098861837907;\r\n\r\n  /* Product: '<S40>/Product1' incorporates:\r\n   *  Constant: '<S40>/Constant1'\r\n   *  Constant: '<S40>/Constant2'\r\n   *  Delay: '<S40>/Delay'\r\n   *  Delay: '<S40>/Delay1'\r\n   *  Delay: '<S40>/Delay2'\r\n   *  Delay: '<S40>/Delay3'\r\n   *  Gain: '<S40>/gain1'\r\n   *  Gain: '<S40>/gain3'\r\n   *  Product: '<S40>/x(n), x(n-1), x(n-2)'\r\n   *  Product: '<S40>/y(n-1)'\r\n   *  Product: '<S40>/y(n-2)'\r\n   *  Sum: '<S40>/Sum1'\r\n   *  Sum: '<S40>/Sum2'\r\n   *  Sum: '<S40>/Sum3'\r\n   *  Sum: '<S40>/Sum4'\r\n   *  Sum: '<S40>/Sum5'\r\n   *  Sum: '<S40>/Sum6'\r\n   */\r\n  rtb_Product1_p = ((((2.0 * ADM_Integrated_Logic_DW.Delay1_DSTATE_c +\r\n                       rtb_Product1_nu) +\r\n                      ADM_Integrated_Logic_DW.Delay_DSTATE_p[0]) *\r\n                     0.00035530575843921691 - -7.9992893884831213 *\r\n                     ADM_Integrated_Logic_DW.Delay2_DSTATE_n) -\r\n                    3.9470487616123275 *\r\n                    ADM_Integrated_Logic_DW.Delay3_DSTATE_h[0]) /\r\n    4.0536618499045511;\r\n\r\n  /* MATLAB Function: '<S7>/DOB_Gain' incorporates:\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   */\r\n  if (ADM_Integrated_Logic_U.GV_Vx_Fbk < 5.0) {\r\n    rtb_Switch2 = 0.0;\r\n  } else {\r\n    rtb_Switch2 = (ADM_Integrated_Logic_U.GV_Vx_Fbk - 5.0) * 0.2;\r\n  }\r\n\r\n  if (rtb_Switch2 >= 1.0) {\r\n    rtb_Switch2 = 1.0;\r\n  }\r\n\r\n  /* End of MATLAB Function: '<S7>/DOB_Gain' */\r\n\r\n  /* Product: '<S7>/Product1' incorporates:\r\n   *  Constant: '<S7>/DOBFlag'\r\n   *  Product: '<S7>/Product'\r\n   */\r\n  rtb_Product1_c = -(rtb_Product1_p * 0.9);\r\n\r\n  /* Saturate: '<S7>/DOB_Saturation' */\r\n  if (rtb_Product1_c > 30.0) {\r\n    rtb_Product1_c = 30.0;\r\n  } else if (rtb_Product1_c < -30.0) {\r\n    rtb_Product1_c = -30.0;\r\n  }\r\n\r\n  /* Sum: '<S7>/Subtract2' incorporates:\r\n   *  DeadZone: '<S31>/Dead Zone'\r\n   *  MultiPortSwitch: '<S41>/Multiport Switch1'\r\n   *  Product: '<S43>/Product'\r\n   *  Product: '<S7>/Multiply1'\r\n   *  Saturate: '<S7>/DOB_Saturation'\r\n   *  Sum: '<S31>/Add'\r\n   */\r\n  rtb_Add = (rtb_Add * 0.044648264844923756 + rtb_Product1_h) + rtb_Product1_c *\r\n    rtb_Switch2;\r\n\r\n  /* Saturate: '<S7>/Torq_Saturation' */\r\n  if (rtb_Add > 80.0) {\r\n    rtb_Add = 80.0;\r\n  } else if (rtb_Add < -80.0) {\r\n    rtb_Add = -80.0;\r\n  }\r\n\r\n  /* End of Saturate: '<S7>/Torq_Saturation' */\r\n\r\n  /* Switch: '<S1>/Switch1' incorporates:\r\n   *  Constant: '<S2>/Constant'\r\n   *  Inport: '<Root>/GV_VCU_AccControlFlag'\r\n   *  MATLAB Function: '<S7>/Gear_pos_out'\r\n   *  Product: '<S2>/Product1'\r\n   *  Product: '<S7>/Multiply'\r\n   */\r\n  if (ADM_Integrated_Logic_U.GV_VCU_AccControlFlag > 0.0) {\r\n    rtb_Pitch_Angle = rtb_MotorTorque * 0.270798;\r\n  } else {\r\n    if (rtb_RateLimiter == 0.0) {\r\n      /* MATLAB Function: '<S7>/Gear_pos_out' */\r\n      idx = 0;\r\n    } else if (rtb_RateLimiter == 2.0) {\r\n      /* MATLAB Function: '<S7>/Gear_pos_out' */\r\n      idx = 0;\r\n    } else if (rtb_RateLimiter == 1.0) {\r\n      /* MATLAB Function: '<S7>/Gear_pos_out' */\r\n      idx = -1;\r\n    } else {\r\n      /* MATLAB Function: '<S7>/Gear_pos_out' */\r\n      idx = (rtb_RateLimiter == 3.0);\r\n    }\r\n\r\n    rtb_Pitch_Angle = (double)idx * rtb_Add;\r\n  }\r\n\r\n  /* End of Switch: '<S1>/Switch1' */\r\n\r\n  /* MATLAB Function: '<S1>/Emergency_Motor_Func' incorporates:\r\n   *  Inport: '<Root>/GV_IDB_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_RCU_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   *  Saturate: '<S1>/Saturation'\r\n   */\r\n  if (rtb_Compare) {\r\n    if ((ADM_Integrated_Logic_U.GV_IDB_ECU_Fault_Flag == 1.0) &&\r\n        (ADM_Integrated_Logic_U.GV_RCU_ECU_Fault_Flag == 1.0)) {\r\n      if (ADM_Integrated_Logic_U.GV_Vx_Fbk / 3.6 > 0.5) {\r\n        rtb_MotorTorque = -80.0;\r\n      } else {\r\n        rtb_MotorTorque = 0.0;\r\n      }\r\n    } else {\r\n      rtb_MotorTorque = 0.0;\r\n    }\r\n  } else if (rtb_Pitch_Angle > 80.0) {\r\n    /* Saturate: '<S1>/Saturation' */\r\n    rtb_MotorTorque = 80.0;\r\n  } else if (rtb_Pitch_Angle < 0.0) {\r\n    /* Saturate: '<S1>/Saturation' */\r\n    rtb_MotorTorque = 0.0;\r\n  } else {\r\n    /* Saturate: '<S1>/Saturation' */\r\n    rtb_MotorTorque = rtb_Pitch_Angle;\r\n  }\r\n\r\n  /* End of MATLAB Function: '<S1>/Emergency_Motor_Func' */\r\n\r\n  /* MATLAB Function: '<S1>/MCU_Fault_Injection' incorporates:\r\n   *  Inport: '<Root>/GV_MCU_Actuator_Fault_Flag'\r\n   */\r\n  if (ADM_Integrated_Logic_U.GV_MCU_Actuator_Fault_Flag == 1.0) {\r\n    rtb_Switch2 = 0.0;\r\n  } else {\r\n    rtb_Switch2 = rtb_MotorTorque;\r\n  }\r\n\r\n  /* Logic: '<S1>/Logical Operator' incorporates:\r\n   *  Constant: '<S5>/Constant'\r\n   *  Constant: '<S6>/Constant'\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   *  RelationalOperator: '<S5>/Compare'\r\n   *  RelationalOperator: '<S6>/Compare'\r\n   */\r\n  rtb_Compare_d = ((ADM_Integrated_Logic_U.GV_Vx_Fbk >= 1.0) &&\r\n                   (ADM_Integrated_Logic_U.GV_IMU_AX_Val >= 0.5));\r\n\r\n  /* Outputs for Enabled SubSystem: '<S1>/Enabled Subsystem' incorporates:\r\n   *  EnablePort: '<S10>/Enable'\r\n   */\r\n  if (rtb_Compare_d) {\r\n    /* Outport: '<Root>/GV_VCU_EstMass' incorporates:\r\n     *  Constant: '<S1>/Constant9'\r\n     *  Inport: '<Root>/GV_IMU_AZ_Val'\r\n     *  MATLAB Function: '<S10>/MATLAB Function'\r\n     *  MATLAB Function: '<S1>/MATLAB Function'\r\n     */\r\n    ADM_Integrated_Logic_Y.GV_VCU_EstMass = rtb_Switch2 / ((0.01 *\r\n      ADM_Integrated_Logic_U.GV_IMU_AZ_Val + ADM_Integrated_Logic_DW.x_hat[1]) *\r\n      0.022698910310142498);\r\n  }\r\n\r\n  /* End of Outputs for SubSystem: '<S1>/Enabled Subsystem' */\r\n\r\n  /* Outport: '<Root>/GV_VCU_EstMassFlag' */\r\n  ADM_Integrated_Logic_Y.GV_VCU_EstMassFlag = rtb_Compare_d;\r\n\r\n  /* Outport: '<Root>/GV_Motor_Torque_Cmd' */\r\n  ADM_Integrated_Logic_Y.GV_Motor_Torque_Cmd = rtb_Switch2;\r\n\r\n  /* Outport: '<Root>/Target_MCU_Out' incorporates:\r\n   *  MATLAB Function: '<S1>/MCU_Fault_Injection'\r\n   */\r\n  ADM_Integrated_Logic_Y.Target_MCU_Out = rtb_MotorTorque;\r\n\r\n  /* Chart: '<S12>/Chart' incorporates:\r\n   *  Constant: '<S12>/Constant'\r\n   *  Constant: '<S12>/Constant1'\r\n   *  Inport: '<Root>/GV_MCU_RPM'\r\n   */\r\n  if (ADM_Integrated_Logic_DW.is_active_c6_ADM_Integrated_Log == 0) {\r\n    ADM_Integrated_Logic_DW.is_active_c6_ADM_Integrated_Log = 1U;\r\n    ADM_Integrated_Logic_DW.is_c6_ADM_Integrated_Logic = IN_HAC_OFF;\r\n  } else if (ADM_Integrated_Logic_DW.is_c6_ADM_Integrated_Logic == IN_HAC_OFF) {\r\n    if (ADM_Integrated_Logic_U.GV_MCU_RPM < -50.0) {\r\n      ADM_Integrated_Logic_DW.is_c6_ADM_Integrated_Logic = IN_HAC_ON;\r\n    } else {\r\n      /* Outport: '<Root>/Debug_HAC_RPM_Decision' */\r\n      ADM_Integrated_Logic_Y.Debug_HAC_RPM_Decision = 0.0;\r\n    }\r\n\r\n    /* case IN_HAC_ON: */\r\n  } else if (ADM_Integrated_Logic_U.GV_MCU_RPM > 150.0) {\r\n    ADM_Integrated_Logic_DW.is_c6_ADM_Integrated_Logic = IN_HAC_OFF;\r\n  } else {\r\n    /* Outport: '<Root>/Debug_HAC_RPM_Decision' */\r\n    ADM_Integrated_Logic_Y.Debug_HAC_RPM_Decision = 1.0;\r\n  }\r\n\r\n  /* End of Chart: '<S12>/Chart' */\r\n\r\n  /* Saturate: '<S12>/Pitch_Saturation' incorporates:\r\n   *  DiscreteIntegrator: '<S12>/Integrator_2'\r\n   */\r\n  if (ADM_Integrated_Logic_DW.Integrator_2_DSTATE > 8.0) {\r\n    rtb_MotorTorque = 8.0;\r\n  } else if (ADM_Integrated_Logic_DW.Integrator_2_DSTATE < -8.0) {\r\n    rtb_MotorTorque = -8.0;\r\n  } else {\r\n    rtb_MotorTorque = ADM_Integrated_Logic_DW.Integrator_2_DSTATE;\r\n  }\r\n\r\n  /* End of Saturate: '<S12>/Pitch_Saturation' */\r\n\r\n  /* Delay: '<S61>/Delay' */\r\n  if (ADM_Integrated_Logic_DW.icLoad) {\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_o = rtb_MotorTorque;\r\n  }\r\n\r\n  /* Product: '<S61>/delta rise limit' incorporates:\r\n   *  Constant: '<S12>/Angle_Upper'\r\n   *  SampleTimeMath: '<S61>/sample time'\r\n   *\r\n   * About '<S61>/sample time':\r\n   *  y = K where K = ( w * Ts )\r\n   *   */\r\n  rtb_Switch2 = 0.002;\r\n\r\n  /* Sum: '<S61>/Difference Inputs1' incorporates:\r\n   *  Delay: '<S61>/Delay'\r\n   *\r\n   * Block description for '<S61>/Difference Inputs1':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_MotorTorque -= ADM_Integrated_Logic_DW.Delay_DSTATE_o;\r\n\r\n  /* Switch: '<S66>/Switch2' incorporates:\r\n   *  RelationalOperator: '<S66>/LowerRelop1'\r\n   */\r\n  if (!(rtb_MotorTorque > 0.002)) {\r\n    /* Switch: '<S66>/Switch' incorporates:\r\n     *  RelationalOperator: '<S66>/UpperRelop'\r\n     */\r\n    if (rtb_MotorTorque < -0.002) {\r\n      rtb_Switch2 = -0.002;\r\n    } else {\r\n      rtb_Switch2 = rtb_MotorTorque;\r\n    }\r\n\r\n    /* End of Switch: '<S66>/Switch' */\r\n  }\r\n\r\n  /* End of Switch: '<S66>/Switch2' */\r\n\r\n  /* Sum: '<S61>/Difference Inputs2' incorporates:\r\n   *  Delay: '<S61>/Delay'\r\n   *\r\n   * Block description for '<S61>/Difference Inputs2':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_MotorTorque = rtb_Switch2 + ADM_Integrated_Logic_DW.Delay_DSTATE_o;\r\n\r\n  /* MATLAB Function: '<S54>/Calculate_F_c' incorporates:\r\n   *  Gain: '<S54>/Gain'\r\n   */\r\n  ADM_Integrated_Lo_Calculate_F_c(ADM_Integrated_Logic_ConstB.W_value,\r\n    0.017453292519943295 * rtb_MotorTorque, &rtb_Switch2);\r\n\r\n  /* Gain: '<S54>/Gain2' incorporates:\r\n   *  Constant: '<S54>/Radius'\r\n   *  Gain: '<S54>/Gain1'\r\n   *  Gain: '<S54>/Rolling_Gain'\r\n   *  MATLAB Function: '<S54>/Calculate_F_R'\r\n   *  Product: '<S54>/Multiply3'\r\n   *  Sum: '<S54>/Required_Brake_Cal'\r\n   */\r\n  rtb_Pitch_Angle = (cos(0.017453292519943295 * rtb_MotorTorque) *\r\n                     436.7465753424658 * 0.0 + rtb_Switch2) * 0.292 *\r\n    0.083822296730930432;\r\n\r\n  /* Saturate: '<S54>/Saturation' */\r\n  if (rtb_Pitch_Angle > 60.0) {\r\n    rtb_Pitch_Angle = 60.0;\r\n  } else if (rtb_Pitch_Angle < 0.0) {\r\n    rtb_Pitch_Angle = 0.0;\r\n  }\r\n\r\n  /* End of Saturate: '<S54>/Saturation' */\r\n\r\n  /* Delay: '<S60>/Delay' */\r\n  if (ADM_Integrated_Logic_DW.icLoad_e) {\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_i = rtb_Pitch_Angle;\r\n  }\r\n\r\n  /* Product: '<S60>/delta rise limit' incorporates:\r\n   *  Constant: '<S12>/Upper_Torq'\r\n   *  SampleTimeMath: '<S60>/sample time'\r\n   *\r\n   * About '<S60>/sample time':\r\n   *  y = K where K = ( w * Ts )\r\n   *   */\r\n  rtb_Switch2 = 0.016;\r\n\r\n  /* Sum: '<S60>/Difference Inputs1' incorporates:\r\n   *  Delay: '<S60>/Delay'\r\n   *\r\n   * Block description for '<S60>/Difference Inputs1':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_Pitch_Angle -= ADM_Integrated_Logic_DW.Delay_DSTATE_i;\r\n\r\n  /* Switch: '<S65>/Switch2' incorporates:\r\n   *  RelationalOperator: '<S65>/LowerRelop1'\r\n   */\r\n  if (!(rtb_Pitch_Angle > 0.016)) {\r\n    /* Switch: '<S65>/Switch' incorporates:\r\n     *  RelationalOperator: '<S65>/UpperRelop'\r\n     */\r\n    if (rtb_Pitch_Angle < -0.16) {\r\n      rtb_Switch2 = -0.16;\r\n    } else {\r\n      rtb_Switch2 = rtb_Pitch_Angle;\r\n    }\r\n\r\n    /* End of Switch: '<S65>/Switch' */\r\n  }\r\n\r\n  /* End of Switch: '<S65>/Switch2' */\r\n\r\n  /* Sum: '<S60>/Difference Inputs2' incorporates:\r\n   *  Delay: '<S60>/Delay'\r\n   *\r\n   * Block description for '<S60>/Difference Inputs2':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_Pitch_Angle = rtb_Switch2 + ADM_Integrated_Logic_DW.Delay_DSTATE_i;\r\n\r\n  /* Gain: '<S12>/Grade_GAIN' */\r\n  rtb_Desired_Torque = 0.8 * rtb_Pitch_Angle;\r\n\r\n  /* MATLAB Function: '<S12>/HAC_OFF_OK_Func' */\r\n  rtb_Brake_Torque_Cmd = 0.0;\r\n\r\n  /* Outport: '<Root>/Debug_HAC_FLAG' incorporates:\r\n   *  MATLAB Function: '<S12>/HAC_OFF_OK_Func'\r\n   */\r\n  ADM_Integrated_Logic_Y.Debug_HAC_FLAG = 0.0;\r\n\r\n  /* MATLAB Function: '<S12>/HAC_OFF_OK_Func' incorporates:\r\n   *  Constant: '<S12>/Accel_Cmd '\r\n   *  Constant: '<S12>/Brake_Cmd'\r\n   *  Constant: '<S12>/Gear_D'\r\n   *  Inport: '<Root>/GV_BrakeTorqueCommand'\r\n   *  Inport: '<Root>/GV_MCU_EstTrq'\r\n   *  Outport: '<Root>/Debug_HAC_RPM_Decision'\r\n   *  RelationalOperator: '<S12>/Relational Operator'\r\n   *  RelationalOperator: '<S12>/Relational Operator1'\r\n   *  RelationalOperator: '<S12>/Relational Operator2'\r\n   *  Sum: '<S12>/HAC_Flags_Add'\r\n   */\r\n  if ((double)(((ADM_Integrated_Logic_U.GV_BrakeTorqueCommand <= 20.0) +\r\n                (rtb_Vx_Cmd_R <= 2.0)) + (rtb_RateLimiter == 3.0)) +\r\n      ADM_Integrated_Logic_Y.Debug_HAC_RPM_Decision >= 4.0) {\r\n    if (ADM_Integrated_Logic_DW.HAC_ON_FLAG == 0.0) {\r\n      ADM_Integrated_Logic_DW.HAC_ON_Timer = 0.0;\r\n    }\r\n\r\n    ADM_Integrated_Logic_DW.HAC_ON_FLAG = 1.0;\r\n    rtb_Brake_Torque_Cmd = 1000.0;\r\n    ADM_Integrated_Logic_DW.Smoothed_Torque = 1000.0;\r\n    if (ADM_Integrated_Logic_DW.HAC_ON_Timer < 3.0) {\r\n      ADM_Integrated_Logic_DW.HAC_Desired_Torque = rtb_Desired_Torque;\r\n      ADM_Integrated_Logic_DW.HAC_ON_Timer += 0.005;\r\n    }\r\n\r\n    /* Outport: '<Root>/Debug_HAC_FLAG' */\r\n    ADM_Integrated_Logic_Y.Debug_HAC_FLAG = 1.0;\r\n  } else if (ADM_Integrated_Logic_DW.HAC_ON_FLAG == 1.0) {\r\n    if (ADM_Integrated_Logic_U.GV_MCU_EstTrq >=\r\n        ADM_Integrated_Logic_DW.HAC_Desired_Torque) {\r\n      ADM_Integrated_Logic_DW.Smoothed_Torque -= 0.05 *\r\n        ADM_Integrated_Logic_DW.Smoothed_Torque;\r\n      if (ADM_Integrated_Logic_DW.Smoothed_Torque < 0.01) {\r\n        ADM_Integrated_Logic_DW.Smoothed_Torque = 0.0;\r\n        ADM_Integrated_Logic_DW.HAC_ON_FLAG = 0.0;\r\n        ADM_Integrated_Logic_DW.HAC_Desired_Torque = 0.0;\r\n        ADM_Integrated_Logic_DW.HAC_ON_Timer = 0.0;\r\n      }\r\n\r\n      rtb_Brake_Torque_Cmd = ADM_Integrated_Logic_DW.Smoothed_Torque;\r\n    } else {\r\n      rtb_Brake_Torque_Cmd = 1000.0;\r\n      ADM_Integrated_Logic_DW.Smoothed_Torque = 1000.0;\r\n\r\n      /* Outport: '<Root>/Debug_HAC_FLAG' */\r\n      ADM_Integrated_Logic_Y.Debug_HAC_FLAG = 1.0;\r\n    }\r\n  }\r\n\r\n  /* Gain: '<S7>/Brake_GAIN' incorporates:\r\n   *  DiscreteTransferFcn: '<S1>/Discrete Transfer Fcn'\r\n   */\r\n  rtb_Product1_c = 0.0625 * ADM_Integrated_Logic_DW.DiscreteTransferFcn_states *\r\n    -80.0;\r\n\r\n  /* MATLAB Function: '<S7>/GearCondition_Brake' */\r\n  if (rtb_RateLimiter == 1.0) {\r\n    idx = -1;\r\n  } else {\r\n    idx = (rtb_RateLimiter == 3.0);\r\n  }\r\n\r\n  /* Saturate: '<S7>/Saturation' */\r\n  if (rtb_Product1_c > 1000.0) {\r\n    rtb_Product1_c = 1000.0;\r\n  } else if (rtb_Product1_c < 0.0) {\r\n    rtb_Product1_c = 0.0;\r\n  }\r\n\r\n  /* Product: '<S7>/Multiply2' incorporates:\r\n   *  MATLAB Function: '<S7>/GearCondition_Brake'\r\n   *  Saturate: '<S7>/Saturation'\r\n   */\r\n  rtb_Switch2 = (double)idx * rtb_Product1_c;\r\n\r\n  /* RateLimiter: '<S7>/Brake_Out_RateLimiter' */\r\n  rtb_Product1_c = rtb_Switch2 - ADM_Integrated_Logic_DW.PrevY_o;\r\n  if (rtb_Product1_c > 3.0) {\r\n    rtb_Switch2 = ADM_Integrated_Logic_DW.PrevY_o + 3.0;\r\n  } else if (rtb_Product1_c < -3.0) {\r\n    rtb_Switch2 = ADM_Integrated_Logic_DW.PrevY_o - 3.0;\r\n  }\r\n\r\n  ADM_Integrated_Logic_DW.PrevY_o = rtb_Switch2;\r\n\r\n  /* End of RateLimiter: '<S7>/Brake_Out_RateLimiter' */\r\n\r\n  /* Saturate: '<S7>/Brake_Saturation' */\r\n  if (rtb_Switch2 > 1000.0) {\r\n    rtb_Switch2 = 1000.0;\r\n  } else if (rtb_Switch2 < 0.0) {\r\n    rtb_Switch2 = 0.0;\r\n  }\r\n\r\n  /* End of Saturate: '<S7>/Brake_Saturation' */\r\n\r\n  /* MATLAB Function: '<S1>/Emergency_Brake_Func' incorporates:\r\n   *  Inport: '<Root>/GV_VCU_AccControlFlag'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   *  Sum: '<S1>/Add'\r\n   *  Switch: '<S1>/Switch2'\r\n   */\r\n  if (rtb_Compare) {\r\n    rtb_BrakeTorque = ADM_Integrated_Logic_U.GV_Vx_Fbk * 100.0;\r\n  } else {\r\n    if (!(ADM_Integrated_Logic_U.GV_VCU_AccControlFlag > 0.0)) {\r\n      /* Switch: '<S1>/Switch2' */\r\n      rtb_BrakeTorque = rtb_Switch2;\r\n    }\r\n\r\n    rtb_BrakeTorque += rtb_Brake_Torque_Cmd;\r\n  }\r\n\r\n  /* Saturate: '<S1>/Brake_Saturation' incorporates:\r\n   *  MATLAB Function: '<S1>/Emergency_Brake_Func'\r\n   */\r\n  if (rtb_BrakeTorque > 2500.0) {\r\n    rtb_BrakeTorque = 2500.0;\r\n  } else if (rtb_BrakeTorque < 0.0) {\r\n    rtb_BrakeTorque = 0.0;\r\n  }\r\n\r\n  /* End of Saturate: '<S1>/Brake_Saturation' */\r\n\r\n  /* Outport: '<Root>/GV_Brake_Command' incorporates:\r\n   *  MATLAB Function: '<S1>/IDB_Fault_Injection'\r\n   */\r\n  ADM_Integrated_Logic_Y.GV_Brake_Command = rtb_BrakeTorque;\r\n\r\n  /* Outport: '<Root>/Target_IDB_Out' incorporates:\r\n   *  MATLAB Function: '<S1>/IDB_Fault_Injection'\r\n   */\r\n  ADM_Integrated_Logic_Y.Target_IDB_Out = rtb_BrakeTorque;\r\n\r\n  /* Outport: '<Root>/Debug_CC_Brake_Output' */\r\n  ADM_Integrated_Logic_Y.Debug_CC_Brake_Output = rtb_Switch2;\r\n\r\n  /* Outport: '<Root>/Debug_HAC_Brake_Output' */\r\n  ADM_Integrated_Logic_Y.Debug_HAC_Brake_Output = rtb_Brake_Torque_Cmd;\r\n\r\n  /* Outport: '<Root>/GV_Hill_Torque_Assist' */\r\n  ADM_Integrated_Logic_Y.GV_Hill_Torque_Assist = rtb_Desired_Torque;\r\n\r\n  /* Outport: '<Root>/Debug_HAC_Pitch_angle' */\r\n  ADM_Integrated_Logic_Y.Debug_HAC_Pitch_angle = rtb_MotorTorque;\r\n\r\n  /* MATLAB Function: '<S54>/Calculate_F_c1' incorporates:\r\n   *  Gain: '<S54>/Gain3'\r\n   */\r\n  ADM_Integrated_Lo_Calculate_F_c(ADM_Integrated_Logic_ConstB.W_Value_for_Brake,\r\n    0.017453292519943295 * rtb_MotorTorque, &rtb_Switch2);\r\n\r\n  /* Product: '<S55>/Product1' incorporates:\r\n   *  Constant: '<S55>/Constant'\r\n   *  Gain: '<S55>/gain'\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   *  Product: '<S55>/Product11'\r\n   *  Sum: '<S55>/Sum1'\r\n   *  Sum: '<S55>/Sum2'\r\n   *  Sum: '<S55>/Sum3'\r\n   *  Sum: '<S55>/Sum4'\r\n   *  UnitDelay: '<S55>/d'\r\n   *  UnitDelay: '<S55>/d1'\r\n   */\r\n  rtb_BrakeTorque = ((ADM_Integrated_Logic_U.GV_IMU_AX_Val +\r\n                      ADM_Integrated_Logic_DW.d1_DSTATE_ob) * 0.002 +\r\n                     0.061661977236758134 * ADM_Integrated_Logic_DW.d_DSTATE_e) /\r\n    0.065661977236758137;\r\n\r\n  /* Product: '<S56>/Product1' incorporates:\r\n   *  Constant: '<S56>/Constant'\r\n   *  Gain: '<S56>/gain'\r\n   *  Inport: '<Root>/GV_IMU_AY_Val'\r\n   *  Product: '<S56>/Product11'\r\n   *  Sum: '<S56>/Sum1'\r\n   *  Sum: '<S56>/Sum2'\r\n   *  Sum: '<S56>/Sum3'\r\n   *  Sum: '<S56>/Sum4'\r\n   *  UnitDelay: '<S56>/d'\r\n   *  UnitDelay: '<S56>/d1'\r\n   */\r\n  rtb_Product1_c = ((ADM_Integrated_Logic_U.GV_IMU_AY_Val +\r\n                     ADM_Integrated_Logic_DW.d1_DSTATE_i) * 0.002 +\r\n                    0.061661977236758134 * ADM_Integrated_Logic_DW.d_DSTATE_p) /\r\n    0.065661977236758137;\r\n\r\n  /* Product: '<S57>/Product1' incorporates:\r\n   *  Constant: '<S57>/Constant'\r\n   *  Gain: '<S57>/gain'\r\n   *  Inport: '<Root>/GV_IMU_AZ_Val'\r\n   *  Product: '<S57>/Product11'\r\n   *  Sum: '<S57>/Sum1'\r\n   *  Sum: '<S57>/Sum2'\r\n   *  Sum: '<S57>/Sum3'\r\n   *  Sum: '<S57>/Sum4'\r\n   *  UnitDelay: '<S57>/d'\r\n   *  UnitDelay: '<S57>/d1'\r\n   */\r\n  rtb_Desired_Torque = ((ADM_Integrated_Logic_U.GV_IMU_AZ_Val +\r\n    ADM_Integrated_Logic_DW.d1_DSTATE_o1) * 0.002 + 0.061661977236758134 *\r\n                        ADM_Integrated_Logic_DW.d_DSTATE_n) /\r\n    0.065661977236758137;\r\n\r\n  /* MATLAB Function: '<S12>/Pitch_calculate' */\r\n  rtb_Switch2 = sqrt(rtb_Product1_c * rtb_Product1_c + rtb_Desired_Torque *\r\n                     rtb_Desired_Torque);\r\n  if (!(rtb_Switch2 == 0.0)) {\r\n    rtb_Switch2 = atan(rtb_BrakeTorque / rtb_Switch2);\r\n  }\r\n\r\n  /* Sum: '<S12>/Sum' incorporates:\r\n   *  DiscreteIntegrator: '<S12>/Integrator_2'\r\n   *  MATLAB Function: '<S12>/Pitch_calculate'\r\n   */\r\n  rtb_Brake_Torque_Cmd = ADM_Integrated_Logic_DW.Integrator_2_DSTATE -\r\n    rtb_Switch2 * 57.295779513082323;\r\n\r\n  /* Product: '<S58>/Product1' incorporates:\r\n   *  Constant: '<S58>/Constant'\r\n   *  Gain: '<S58>/gain'\r\n   *  Inport: '<Root>/GV_IMU_PitchRtVal'\r\n   *  Product: '<S58>/Product11'\r\n   *  Sum: '<S58>/Sum1'\r\n   *  Sum: '<S58>/Sum2'\r\n   *  Sum: '<S58>/Sum3'\r\n   *  Sum: '<S58>/Sum4'\r\n   *  UnitDelay: '<S58>/d'\r\n   *  UnitDelay: '<S58>/d1'\r\n   */\r\n  rtb_Product1_lo = ((ADM_Integrated_Logic_U.GV_IMU_PitchRtVal +\r\n                      ADM_Integrated_Logic_DW.d1_DSTATE_a) * 0.002 +\r\n                     0.061661977236758134 * ADM_Integrated_Logic_DW.d_DSTATE_d1)\r\n    / 0.065661977236758137;\r\n\r\n  /* Sum: '<S1>/Add2' incorporates:\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   */\r\n  rtb_Vx_Cmd_R -= ADM_Integrated_Logic_U.GV_Vx_Fbk;\r\n\r\n  /* Outport: '<Root>/GV_Gear_Postion_Out' */\r\n  ADM_Integrated_Logic_Y.GV_Gear_Postion_Out = rtb_RateLimiter;\r\n\r\n  /* Sum: '<S1>/Add1' incorporates:\r\n   *  Constant: '<S1>/Constant'\r\n   *  Gain: '<S1>/Gain1'\r\n   *  Inport: '<Root>/GV_Vx_Fbk'\r\n   *  Sum: '<S1>/Add3'\r\n   */\r\n  rtb_Add1_tmp = 400.0 - 6.5 * ADM_Integrated_Logic_U.GV_Vx_Fbk;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function1' incorporates:\r\n   *  Sum: '<S1>/Add1'\r\n   */\r\n  ADM_Integrated__MATLABFunction1(rtb_Add1_tmp, &rtb_y_c);\r\n\r\n  /* Product: '<S22>/delta rise limit' incorporates:\r\n   *  SampleTimeMath: '<S22>/sample time'\r\n   *\r\n   * About '<S22>/sample time':\r\n   *  y = K where K = ( w * Ts )\r\n   *   */\r\n  rtb_Switch2 = rtb_y_c * 0.002;\r\n\r\n  /* Delay: '<S22>/Delay' incorporates:\r\n   *  Inport: '<Root>/GV_RWA_RackAngleCommand'\r\n   */\r\n  if (ADM_Integrated_Logic_DW.icLoad_l) {\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_c =\r\n      ADM_Integrated_Logic_U.GV_RWA_RackAngleCommand;\r\n  }\r\n\r\n  /* Sum: '<S22>/Difference Inputs1' incorporates:\r\n   *  Delay: '<S22>/Delay'\r\n   *  Inport: '<Root>/GV_RWA_RackAngleCommand'\r\n   *\r\n   * Block description for '<S22>/Difference Inputs1':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_UkYk1_j = ADM_Integrated_Logic_U.GV_RWA_RackAngleCommand -\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_c;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function2' incorporates:\r\n   *  Gain: '<S1>/Gain3'\r\n   *  Sum: '<S1>/Add1'\r\n   */\r\n  ADM_Integrated__MATLABFunction2(-rtb_Add1_tmp, &rtb_y_c);\r\n\r\n  /* Switch: '<S67>/Switch2' incorporates:\r\n   *  RelationalOperator: '<S67>/LowerRelop1'\r\n   */\r\n  if (!(rtb_UkYk1_j > rtb_Switch2)) {\r\n    /* Product: '<S22>/delta fall limit' incorporates:\r\n     *  SampleTimeMath: '<S22>/sample time'\r\n     *\r\n     * About '<S22>/sample time':\r\n     *  y = K where K = ( w * Ts )\r\n     *   */\r\n    rtb_Switch2 = 0.002 * rtb_y_c;\r\n\r\n    /* Switch: '<S67>/Switch' incorporates:\r\n     *  RelationalOperator: '<S67>/UpperRelop'\r\n     */\r\n    if (!(rtb_UkYk1_j < rtb_Switch2)) {\r\n      rtb_Switch2 = rtb_UkYk1_j;\r\n    }\r\n\r\n    /* End of Switch: '<S67>/Switch' */\r\n  }\r\n\r\n  /* End of Switch: '<S67>/Switch2' */\r\n\r\n  /* Sum: '<S22>/Difference Inputs2' incorporates:\r\n   *  Delay: '<S22>/Delay'\r\n   *\r\n   * Block description for '<S22>/Difference Inputs2':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_UkYk1_j = rtb_Switch2 + ADM_Integrated_Logic_DW.Delay_DSTATE_c;\r\n\r\n  /* Outport: '<Root>/GV_Master_Rack_Angle_Cmd' incorporates:\r\n   *  MATLAB Function: '<S1>/RWA_Actuator_Fault_Injection'\r\n   */\r\n  ADM_Integrated_Logic_Y.GV_Master_Rack_Angle_Cmd = rtb_UkYk1_j;\r\n\r\n  /* Outport: '<Root>/Target_RWA_Out' incorporates:\r\n   *  MATLAB Function: '<S1>/RWA_Actuator_Fault_Injection'\r\n   */\r\n  ADM_Integrated_Logic_Y.Target_RWA_Out = rtb_UkYk1_j;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function5' */\r\n  ADM_Integrated__MATLABFunction1(rtb_Add1_tmp, &rtb_y_c);\r\n\r\n  /* Product: '<S23>/delta rise limit' incorporates:\r\n   *  SampleTimeMath: '<S23>/sample time'\r\n   *\r\n   * About '<S23>/sample time':\r\n   *  y = K where K = ( w * Ts )\r\n   *   */\r\n  rtb_Switch2 = rtb_y_c * 0.002;\r\n\r\n  /* Delay: '<S23>/Delay' incorporates:\r\n   *  Inport: '<Root>/GV_RWS_RackAngleCommand'\r\n   */\r\n  if (ADM_Integrated_Logic_DW.icLoad_d) {\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_i1 =\r\n      ADM_Integrated_Logic_U.GV_RWS_RackAngleCommand;\r\n  }\r\n\r\n  /* Sum: '<S23>/Difference Inputs1' incorporates:\r\n   *  Delay: '<S23>/Delay'\r\n   *  Inport: '<Root>/GV_RWS_RackAngleCommand'\r\n   *\r\n   * Block description for '<S23>/Difference Inputs1':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_Add1 = ADM_Integrated_Logic_U.GV_RWS_RackAngleCommand -\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_i1;\r\n\r\n  /* MATLAB Function: '<S1>/MATLAB Function6' incorporates:\r\n   *  Gain: '<S1>/Gain5'\r\n   */\r\n  ADM_Integrated__MATLABFunction2(-rtb_Add1_tmp, &rtb_y_c);\r\n\r\n  /* Switch: '<S68>/Switch2' incorporates:\r\n   *  RelationalOperator: '<S68>/LowerRelop1'\r\n   */\r\n  if (!(rtb_Add1 > rtb_Switch2)) {\r\n    /* Product: '<S23>/delta fall limit' incorporates:\r\n     *  SampleTimeMath: '<S23>/sample time'\r\n     *\r\n     * About '<S23>/sample time':\r\n     *  y = K where K = ( w * Ts )\r\n     *   */\r\n    rtb_Switch2 = 0.002 * rtb_y_c;\r\n\r\n    /* Switch: '<S68>/Switch' incorporates:\r\n     *  RelationalOperator: '<S68>/UpperRelop'\r\n     */\r\n    if (!(rtb_Add1 < rtb_Switch2)) {\r\n      rtb_Switch2 = rtb_Add1;\r\n    }\r\n\r\n    /* End of Switch: '<S68>/Switch' */\r\n  }\r\n\r\n  /* End of Switch: '<S68>/Switch2' */\r\n\r\n  /* Sum: '<S23>/Difference Inputs2' incorporates:\r\n   *  Delay: '<S23>/Delay'\r\n   *\r\n   * Block description for '<S23>/Difference Inputs2':\r\n   *\r\n   *  Add in CPU\r\n   */\r\n  rtb_Switch2 += ADM_Integrated_Logic_DW.Delay_DSTATE_i1;\r\n\r\n  /* Outport: '<Root>/GV_RWS_RackAngleCmd1' */\r\n  ADM_Integrated_Logic_Y.GV_RWS_RackAngleCmd1 = rtb_Switch2;\r\n\r\n  /* Outport: '<Root>/Act_Fault_Exist' incorporates:\r\n   *  MATLAB Function: '<S1>/Actuator_Fault_Decision'\r\n   */\r\n  ADM_Integrated_Logic_Y.Act_Fault_Exist = 0.0;\r\n\r\n  /* MATLAB Function: '<S1>/Actuator_Fault_Decision' incorporates:\r\n   *  Inport: '<Root>/GV_ACU_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_ACU_ECU_Fault_Flag1'\r\n   *  Inport: '<Root>/GV_ACU_ECU_Fault_Flag2'\r\n   *  Inport: '<Root>/GV_ACU_ECU_Fault_Flag3'\r\n   *  Inport: '<Root>/GV_ACU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_Drive_Mode'\r\n   *  Inport: '<Root>/GV_IDB_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_MCU_Actuator_Fault_Flag'\r\n   *  Inport: '<Root>/GV_RCU_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_RWA1_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_RWA2_ECU_Fault_Flag'\r\n   *  Inport: '<Root>/GV_RWA_Actuator_Fault'\r\n   */\r\n  if ((ADM_Integrated_Logic_U.GV_ACU_Fault_Flag == 1.0) ||\r\n      (ADM_Integrated_Logic_U.GV_MCU_Actuator_Fault_Flag == 1.0) ||\r\n      (ADM_Integrated_Logic_U.GV_RWA_Actuator_Fault == 1.0)) {\r\n    /* Outport: '<Root>/Act_Fault_Exist' */\r\n    ADM_Integrated_Logic_Y.Act_Fault_Exist = 1.0;\r\n  }\r\n\r\n  if (((ADM_Integrated_Logic_U.GV_ACU_ECU_Fault_Flag == 1.0) ||\r\n       (ADM_Integrated_Logic_U.GV_ACU_ECU_Fault_Flag1 == 1.0) ||\r\n       (ADM_Integrated_Logic_U.GV_ACU_ECU_Fault_Flag2 == 1.0) ||\r\n       (ADM_Integrated_Logic_U.GV_ACU_ECU_Fault_Flag3 == 1.0)) &&\r\n      ((ADM_Integrated_Logic_U.GV_Drive_Mode == 0.0) ||\r\n       (ADM_Integrated_Logic_U.GV_Drive_Mode == 2.0))) {\r\n    /* Outport: '<Root>/Act_Fault_Exist' */\r\n    ADM_Integrated_Logic_Y.Act_Fault_Exist = 1.0;\r\n  }\r\n\r\n  if ((ADM_Integrated_Logic_U.GV_IDB_ECU_Fault_Flag == 1.0) ||\r\n      (ADM_Integrated_Logic_U.GV_RCU_ECU_Fault_Flag == 1.0)) {\r\n    /* Outport: '<Root>/Act_Fault_Exist' */\r\n    ADM_Integrated_Logic_Y.Act_Fault_Exist = 1.0;\r\n  } else if ((ADM_Integrated_Logic_U.GV_RWA1_ECU_Fault_Flag == 1.0) &&\r\n             (ADM_Integrated_Logic_U.GV_RWA2_ECU_Fault_Flag == 1.0)) {\r\n    /* Outport: '<Root>/Act_Fault_Exist' */\r\n    ADM_Integrated_Logic_Y.Act_Fault_Exist = 1.0;\r\n  }\r\n\r\n  /* Update for UnitDelay: '<S14>/d1' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE = ADM_Integrated_Logic_U.GV_IMU_AX_Val;\r\n\r\n  /* Update for UnitDelay: '<S14>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE = rtb_Gain;\r\n\r\n  /* Update for DiscreteIntegrator: '<S25>/Discrete-Time Integrator' */\r\n  ADM_Integrated_Logic_DW.DiscreteTimeIntegrator_DSTATE += 0.002 * rtb_Gain2_j;\r\n\r\n  /* Update for UnitDelay: '<S28>/UD'\r\n   *\r\n   * Block description for '<S28>/UD':\r\n   *\r\n   *  Store in Global RAM\r\n   */\r\n  ADM_Integrated_Logic_DW.UD_DSTATE = rtb_TSamp;\r\n\r\n  /* Update for Delay: '<S11>/Memory' */\r\n  ADM_Integrated_Logic_DW.Memory_DSTATE = rtb_RateLimiter;\r\n\r\n  /* Update for UnitDelay: '<S34>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_c = rtb_Target_RPM;\r\n\r\n  /* Update for UnitDelay: '<S34>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_l = rtb_Product1_j;\r\n\r\n  /* Update for UnitDelay: '<S44>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_i = rtb_Product1_j;\r\n\r\n  /* Update for UnitDelay: '<S44>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_p = rtb_Sum1_i2;\r\n\r\n  /* Update for UnitDelay: '<S45>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_c = rtb_Sum1_i2;\r\n\r\n  /* Update for UnitDelay: '<S45>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_h = rtb_Sum1_o1;\r\n\r\n  /* Update for UnitDelay: '<S46>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_d = rtb_Sum1_o1;\r\n\r\n  /* Update for UnitDelay: '<S46>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_l = rtb_Sum1_lm;\r\n\r\n  /* Update for Delay: '<S48>/Delay1' */\r\n  ADM_Integrated_Logic_DW.Delay1_DSTATE = rtb_Gain_c;\r\n\r\n  /* Update for Delay: '<S48>/Delay' */\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE[0] =\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE[1];\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE[1] = rtb_Gain_c;\r\n\r\n  /* Update for Delay: '<S48>/Delay2' */\r\n  ADM_Integrated_Logic_DW.Delay2_DSTATE = rtb_Product1_dc;\r\n\r\n  /* Update for Delay: '<S48>/Delay3' */\r\n  ADM_Integrated_Logic_DW.Delay3_DSTATE[0] =\r\n    ADM_Integrated_Logic_DW.Delay3_DSTATE[1];\r\n  ADM_Integrated_Logic_DW.Delay3_DSTATE[1] = rtb_Product1_dc;\r\n\r\n  /* Update for UnitDelay: '<S47>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_e = rtb_Product1_dc;\r\n\r\n  /* Update for UnitDelay: '<S47>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_ij = rtb_Product1_h;\r\n\r\n  /* Update for Memory: '<S7>/Memory' */\r\n  ADM_Integrated_Logic_DW.Memory_PreviousInput = rtb_Add;\r\n\r\n  /* Update for UnitDelay: '<S36>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_ir = rtb_Product1_j;\r\n\r\n  /* Update for UnitDelay: '<S36>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_o = rtb_Error_m;\r\n\r\n  /* Update for UnitDelay: '<S37>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_m = rtb_Error_m;\r\n\r\n  /* Update for UnitDelay: '<S37>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_hm = rtb_Sum1_aj;\r\n\r\n  /* Update for UnitDelay: '<S38>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_mw = rtb_Sum1_aj;\r\n\r\n  /* Update for UnitDelay: '<S38>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_g = rtb_Sum1_p;\r\n\r\n  /* Update for UnitDelay: '<S39>/d1' */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_ej = rtb_Add3;\r\n\r\n  /* Update for UnitDelay: '<S39>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_j = rtb_Product1_nu;\r\n\r\n  /* Update for Delay: '<S40>/Delay1' */\r\n  ADM_Integrated_Logic_DW.Delay1_DSTATE_c = rtb_Product1_nu;\r\n\r\n  /* Update for Delay: '<S40>/Delay' */\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_p[0] =\r\n    ADM_Integrated_Logic_DW.Delay_DSTATE_p[1];\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_p[1] = rtb_Product1_nu;\r\n\r\n  /* Update for Delay: '<S40>/Delay2' */\r\n  ADM_Integrated_Logic_DW.Delay2_DSTATE_n = rtb_Product1_p;\r\n\r\n  /* Update for Delay: '<S40>/Delay3' */\r\n  ADM_Integrated_Logic_DW.Delay3_DSTATE_h[0] =\r\n    ADM_Integrated_Logic_DW.Delay3_DSTATE_h[1];\r\n  ADM_Integrated_Logic_DW.Delay3_DSTATE_h[1] = rtb_Product1_p;\r\n\r\n  /* Update for DiscreteIntegrator: '<S12>/Integrator_2' incorporates:\r\n   *  Constant: '<S12>/I_gain'\r\n   *  Constant: '<S12>/P_gain'\r\n   *  DiscreteIntegrator: '<S12>/Integrator_1'\r\n   *  Product: '<S12>/Product'\r\n   *  Product: '<S12>/Product1'\r\n   *  Sum: '<S12>/Sum1'\r\n   *  Sum: '<S12>/Sum2'\r\n   */\r\n  ADM_Integrated_Logic_DW.Integrator_2_DSTATE += (rtb_Product1_lo -\r\n    (ADM_Integrated_Logic_DW.Integrator_1_DSTATE * 5.0 + rtb_Brake_Torque_Cmd *\r\n     100.0)) * 0.002;\r\n\r\n  /* Update for Delay: '<S61>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad = false;\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_o = rtb_MotorTorque;\r\n\r\n  /* Update for Delay: '<S60>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_e = false;\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_i = rtb_Pitch_Angle;\r\n\r\n  /* Update for DiscreteTransferFcn: '<S1>/Discrete Transfer Fcn' */\r\n  ADM_Integrated_Logic_DW.DiscreteTransferFcn_states = rtb_Vx_Cmd_R - -0.9375 *\r\n    ADM_Integrated_Logic_DW.DiscreteTransferFcn_states;\r\n\r\n  /* Update for UnitDelay: '<S55>/d1' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_AX_Val'\r\n   */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_ob = ADM_Integrated_Logic_U.GV_IMU_AX_Val;\r\n\r\n  /* Update for UnitDelay: '<S55>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_e = rtb_BrakeTorque;\r\n\r\n  /* Update for UnitDelay: '<S56>/d1' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_AY_Val'\r\n   */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_i = ADM_Integrated_Logic_U.GV_IMU_AY_Val;\r\n\r\n  /* Update for UnitDelay: '<S56>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_p = rtb_Product1_c;\r\n\r\n  /* Update for UnitDelay: '<S57>/d1' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_AZ_Val'\r\n   */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_o1 = ADM_Integrated_Logic_U.GV_IMU_AZ_Val;\r\n\r\n  /* Update for UnitDelay: '<S57>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_n = rtb_Desired_Torque;\r\n\r\n  /* Update for DiscreteIntegrator: '<S12>/Integrator_1' */\r\n  ADM_Integrated_Logic_DW.Integrator_1_DSTATE += 0.002 * rtb_Brake_Torque_Cmd;\r\n\r\n  /* Update for UnitDelay: '<S58>/d1' incorporates:\r\n   *  Inport: '<Root>/GV_IMU_PitchRtVal'\r\n   */\r\n  ADM_Integrated_Logic_DW.d1_DSTATE_a = ADM_Integrated_Logic_U.GV_IMU_PitchRtVal;\r\n\r\n  /* Update for UnitDelay: '<S58>/d' */\r\n  ADM_Integrated_Logic_DW.d_DSTATE_d1 = rtb_Product1_lo;\r\n\r\n  /* Update for Delay: '<S22>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_l = false;\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_c = rtb_UkYk1_j;\r\n\r\n  /* Update for Delay: '<S23>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_d = false;\r\n  ADM_Integrated_Logic_DW.Delay_DSTATE_i1 = rtb_Switch2;\r\n}\r\n\r\n/* Model initialize function */\r\nvoid ADM_Integrated_Logic_initialize(void)\r\n{\r\n  /* Registration code */\r\n\r\n  /* initialize non-finites */\r\n  rt_InitInfAndNaN(sizeof(double));\r\n\r\n  /* InitializeConditions for Delay: '<S61>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad = true;\r\n\r\n  /* InitializeConditions for Delay: '<S60>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_e = true;\r\n\r\n  /* InitializeConditions for Delay: '<S22>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_l = true;\r\n\r\n  /* InitializeConditions for Delay: '<S23>/Delay' */\r\n  ADM_Integrated_Logic_DW.icLoad_d = true;\r\n}\r\n\r\n/*\r\n * File trailer for generated code.\r\n *\r\n * [EOF]\r\n */\r\n"},{"name":"ADM_Integrated_Logic.h","type":"header","group":"model","path":"C:\\Users\\MSI\\Documents\\WorkSpace\\git\\ADM\\[ADM] Integrated Logic\\ADM_Integrated_Logic_ert_rtw","tag":"","groupDisplay":"Model files","code":"/*\r\n * Academic License - for use in teaching, academic research, and meeting\r\n * course requirements at degree granting institutions only.  Not for\r\n * government, commercial, or other organizational use.\r\n *\r\n * File: ADM_Integrated_Logic.h\r\n *\r\n * Code generated for Simulink model 'ADM_Integrated_Logic'.\r\n *\r\n * Model version                  : 14.26\r\n * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024\r\n * C/C++ source code generated on : Tue Oct 14 20:08:12 2025\r\n *\r\n * Target selection: ert.tlc\r\n * Embedded hardware selection: NXP->Cortex-M4\r\n * Code generation objectives:\r\n *    1. Execution efficiency\r\n *    2. RAM efficiency\r\n *    3. Debugging\r\n * Validation result: Not run\r\n */\r\n\r\n#ifndef ADM_Integrated_Logic_h_\r\n#define ADM_Integrated_Logic_h_\r\n#ifndef ADM_Integrated_Logic_COMMON_INCLUDES_\r\n#define ADM_Integrated_Logic_COMMON_INCLUDES_\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n#endif                               /* ADM_Integrated_Logic_COMMON_INCLUDES_ */\r\n\r\n/* Macros for accessing real-time model data structure */\r\n#ifndef rtmGetErrorStatus\r\n#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)\r\n#endif\r\n\r\n#ifndef rtmSetErrorStatus\r\n#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))\r\n#endif\r\n\r\n/* Forward declaration for rtModel */\r\ntypedef struct tag_RTM_ADM_Integrated_Logic_T RT_MODEL_ADM_Integrated_Logic_T;\r\n\r\n/* Block signals and states (default storage) for system '<Root>' */\r\ntypedef struct {\r\n  double Delay_DSTATE[2];              /* '<S48>/Delay' */\r\n  double Delay3_DSTATE[2];             /* '<S48>/Delay3' */\r\n  double Delay_DSTATE_p[2];            /* '<S40>/Delay' */\r\n  double Delay3_DSTATE_h[2];           /* '<S40>/Delay3' */\r\n  double x_hat[3];                     /* '<S1>/MATLAB Function' */\r\n  double K_ss[6];                      /* '<S1>/MATLAB Function' */\r\n  double A[9];                         /* '<S1>/MATLAB Function' */\r\n  double H[6];                         /* '<S1>/MATLAB Function' */\r\n  double d1_DSTATE;                    /* '<S14>/d1' */\r\n  double d_DSTATE;                     /* '<S14>/d' */\r\n  double DiscreteTimeIntegrator_DSTATE;/* '<S25>/Discrete-Time Integrator' */\r\n  double UD_DSTATE;                    /* '<S28>/UD' */\r\n  double Memory_DSTATE;                /* '<S11>/Memory' */\r\n  double d1_DSTATE_c;                  /* '<S34>/d1' */\r\n  double d_DSTATE_l;                   /* '<S34>/d' */\r\n  double d_DSTATE_i;                   /* '<S44>/d' */\r\n  double d1_DSTATE_p;                  /* '<S44>/d1' */\r\n  double d_DSTATE_c;                   /* '<S45>/d' */\r\n  double d1_DSTATE_h;                  /* '<S45>/d1' */\r\n  double d_DSTATE_d;                   /* '<S46>/d' */\r\n  double d1_DSTATE_l;                  /* '<S46>/d1' */\r\n  double Delay1_DSTATE;                /* '<S48>/Delay1' */\r\n  double Delay2_DSTATE;                /* '<S48>/Delay2' */\r\n  double d1_DSTATE_e;                  /* '<S47>/d1' */\r\n  double d_DSTATE_ij;                  /* '<S47>/d' */\r\n  double d_DSTATE_ir;                  /* '<S36>/d' */\r\n  double d1_DSTATE_o;                  /* '<S36>/d1' */\r\n  double d_DSTATE_m;                   /* '<S37>/d' */\r\n  double d1_DSTATE_hm;                 /* '<S37>/d1' */\r\n  double d_DSTATE_mw;                  /* '<S38>/d' */\r\n  double d1_DSTATE_g;                  /* '<S38>/d1' */\r\n  double d1_DSTATE_ej;                 /* '<S39>/d1' */\r\n  double d_DSTATE_j;                   /* '<S39>/d' */\r\n  double Delay1_DSTATE_c;              /* '<S40>/Delay1' */\r\n  double Delay2_DSTATE_n;              /* '<S40>/Delay2' */\r\n  double Integrator_2_DSTATE;          /* '<S12>/Integrator_2' */\r\n  double Delay_DSTATE_o;               /* '<S61>/Delay' */\r\n  double Delay_DSTATE_i;               /* '<S60>/Delay' */\r\n  double DiscreteTransferFcn_states;   /* '<S1>/Discrete Transfer Fcn' */\r\n  double d1_DSTATE_ob;                 /* '<S55>/d1' */\r\n  double d_DSTATE_e;                   /* '<S55>/d' */\r\n  double d1_DSTATE_i;                  /* '<S56>/d1' */\r\n  double d_DSTATE_p;                   /* '<S56>/d' */\r\n  double d1_DSTATE_o1;                 /* '<S57>/d1' */\r\n  double d_DSTATE_n;                   /* '<S57>/d' */\r\n  double Integrator_1_DSTATE;          /* '<S12>/Integrator_1' */\r\n  double d1_DSTATE_a;                  /* '<S58>/d1' */\r\n  double d_DSTATE_d1;                  /* '<S58>/d' */\r\n  double Delay_DSTATE_c;               /* '<S22>/Delay' */\r\n  double Delay_DSTATE_i1;              /* '<S23>/Delay' */\r\n  double PrevY;                        /* '<S2>/Rate Limiter' */\r\n  double PrevY_a;                      /* '<S24>/Input_Vx_RateLimiter' */\r\n  double PrevY_ak;                     /* '<S7>/TargetSpd_RateLimiter' */\r\n  double Memory_PreviousInput;         /* '<S7>/Memory' */\r\n  double PrevY_o;                      /* '<S7>/Brake_Out_RateLimiter' */\r\n  double HAC_ON_FLAG;                  /* '<S12>/HAC_OFF_OK_Func' */\r\n  double Smoothed_Torque;              /* '<S12>/HAC_OFF_OK_Func' */\r\n  double HAC_Desired_Torque;           /* '<S12>/HAC_OFF_OK_Func' */\r\n  double HAC_ON_Timer;                 /* '<S12>/HAC_OFF_OK_Func' */\r\n  uint8_t is_active_c6_ADM_Integrated_Log;/* '<S12>/Chart' */\r\n  uint8_t is_c6_ADM_Integrated_Logic;  /* '<S12>/Chart' */\r\n  bool icLoad;                         /* '<S61>/Delay' */\r\n  bool icLoad_e;                       /* '<S60>/Delay' */\r\n  bool icLoad_l;                       /* '<S22>/Delay' */\r\n  bool icLoad_d;                       /* '<S23>/Delay' */\r\n  bool K_ss_not_empty;                 /* '<S1>/MATLAB Function' */\r\n} DW_ADM_Integrated_Logic_T;\r\n\r\n/* Invariant block signals (default storage) */\r\ntypedef struct {\r\n  const double W_value;                /* '<S54>/Multiply' */\r\n  const double W_Value_for_Brake;      /* '<S54>/Multiply4' */\r\n} ConstB_ADM_Integrated_Logic_T;\r\n\r\n/* External inputs (root inport signals with default storage) */\r\ntypedef struct {\r\n  double GV_MCU_RPM;                   /* '<Root>/GV_MCU_RPM' */\r\n  double GV_BrakeTorqueCommand;        /* '<Root>/GV_BrakeTorqueCommand' */\r\n  double GV_IMU_AX_Val;                /* '<Root>/GV_IMU_AX_Val' */\r\n  double GV_IMU_AY_Val;                /* '<Root>/GV_IMU_AY_Val' */\r\n  double GV_IMU_AZ_Val;                /* '<Root>/GV_IMU_AZ_Val' */\r\n  double GV_IMU_PitchRtVal;            /* '<Root>/GV_IMU_PitchRtVal' */\r\n  double GV_Vx_Command;                /* '<Root>/GV_Vx_Command' */\r\n  double GV_VCU_GearSelStat;           /* '<Root>/GV_VCU_GearSelStat' */\r\n  double GV_MCU_EstTrq;                /* '<Root>/GV_MCU_EstTrq' */\r\n  double GV_Vx_Limit;                  /* '<Root>/GV_Vx_Limit' */\r\n  double GV_Vx_Fbk;                    /* '<Root>/GV_Vx_Fbk' */\r\n  double GV_RWA_RackAngleCommand;      /* '<Root>/GV_RWA_RackAngleCommand' */\r\n  double GV_RWS_RackAngleCommand;      /* '<Root>/GV_RWS_RackAngleCommand' */\r\n  double GV_Drive_Mode;                /* '<Root>/GV_Drive_Mode' */\r\n  double GV_ACU_Fault_Flag;            /* '<Root>/GV_ACU_Fault_Flag' */\r\n  double GV_MCU_Actuator_Fault_Flag;   /* '<Root>/GV_MCU_Actuator_Fault_Flag' */\r\n  double GV_IDB_ECU_Fault_Flag;        /* '<Root>/GV_IDB_ECU_Fault_Flag' */\r\n  double GV_RCU_ECU_Fault_Flag;        /* '<Root>/GV_RCU_ECU_Fault_Flag' */\r\n  double GV_RWA1_ECU_Fault_Flag;       /* '<Root>/GV_RWA1_ECU_Fault_Flag' */\r\n  double GV_RWA2_ECU_Fault_Flag;       /* '<Root>/GV_RWA2_ECU_Fault_Flag' */\r\n  double GV_RWA_Actuator_Fault;        /* '<Root>/GV_RWA_Actuator_Fault' */\r\n  double GV_ACU_ECU_Fault_Flag;        /* '<Root>/GV_ACU_ECU_Fault_Flag' */\r\n  double GV_ACU_ECU_Fault_Flag1;       /* '<Root>/GV_ACU_ECU_Fault_Flag1' */\r\n  double GV_ACU_ECU_Fault_Flag2;       /* '<Root>/GV_ACU_ECU_Fault_Flag2' */\r\n  double GV_ACU_ECU_Fault_Flag3;       /* '<Root>/GV_ACU_ECU_Fault_Flag3' */\r\n  double GV_Drive_ACC_Cmd;             /* '<Root>/GV_Drive_ACC_Cmd' */\r\n  double GV_VCU_AccControlFlag;        /* '<Root>/GV_VCU_AccControlFlag' */\r\n  double GV_VCU_Acc_Limit;             /* '<Root>/GV_VCU_Acc_Limit' */\r\n} ExtU_ADM_Integrated_Logic_T;\r\n\r\n/* External outputs (root outports fed by signals with default storage) */\r\ntypedef struct {\r\n  double GV_Brake_Command;             /* '<Root>/GV_Brake_Command' */\r\n  double GV_Master_Rack_Angle_Cmd;     /* '<Root>/GV_Master_Rack_Angle_Cmd' */\r\n  double GV_Hill_Torque_Assist;        /* '<Root>/GV_Hill_Torque_Assist' */\r\n  double GV_Motor_Torque_Cmd;          /* '<Root>/GV_Motor_Torque_Cmd' */\r\n  double Debug_HAC_FLAG;               /* '<Root>/Debug_HAC_FLAG' */\r\n  double Debug_HAC_RPM_Decision;       /* '<Root>/Debug_HAC_RPM_Decision' */\r\n  double Debug_HAC_Pitch_angle;        /* '<Root>/Debug_HAC_Pitch_angle' */\r\n  double Debug_HAC_Brake_Output;       /* '<Root>/Debug_HAC_Brake_Output' */\r\n  double Debug_CC_Brake_Output;        /* '<Root>/Debug_CC_Brake_Output' */\r\n  double GV_RWS_RackAngleCmd1;         /* '<Root>/GV_RWS_RackAngleCmd1' */\r\n  double GV_Speed_Limit;               /* '<Root>/GV_Speed_Limit' */\r\n  double GV_Gear_Postion_Out;          /* '<Root>/GV_Gear_Postion_Out' */\r\n  double Act_Fault_Exist;              /* '<Root>/Act_Fault_Exist' */\r\n  double Target_RWA_Out;               /* '<Root>/Target_RWA_Out' */\r\n  double Target_IDB_Out;               /* '<Root>/Target_IDB_Out' */\r\n  double Target_MCU_Out;               /* '<Root>/Target_MCU_Out' */\r\n  double GV_VCU_EstMass;               /* '<Root>/GV_VCU_EstMass' */\r\n  bool GV_VCU_EstMassFlag;             /* '<Root>/GV_VCU_EstMassFlag' */\r\n} ExtY_ADM_Integrated_Logic_T;\r\n\r\n/* Real-time Model Data Structure */\r\nstruct tag_RTM_ADM_Integrated_Logic_T {\r\n  const char * volatile errorStatus;\r\n};\r\n\r\n/* Block signals and states (default storage) */\r\nextern DW_ADM_Integrated_Logic_T ADM_Integrated_Logic_DW;\r\n\r\n/* External inputs (root inport signals with default storage) */\r\nextern ExtU_ADM_Integrated_Logic_T ADM_Integrated_Logic_U;\r\n\r\n/* External outputs (root outports fed by signals with default storage) */\r\nextern ExtY_ADM_Integrated_Logic_T ADM_Integrated_Logic_Y;\r\nextern const ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB;/* constant block i/o */\r\n\r\n/* Model entry point functions */\r\nextern void ADM_Integrated_Logic_initialize(void);\r\nextern void ADM_Integrated_Logic_step(void);\r\n\r\n/* Real-time Model object */\r\nextern RT_MODEL_ADM_Integrated_Logic_T *const ADM_Integrated_Logic_M;\r\n\r\n/*-\r\n * These blocks were eliminated from the model due to optimizations:\r\n *\r\n * Block '<S28>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S27>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S27>/Data Type Propagation' : Unused code path elimination\r\n * Block '<S31>/BW_PI' : Unused code path elimination\r\n * Block '<S31>/Constant1' : Unused code path elimination\r\n * Block '<S31>/Constant16' : Unused code path elimination\r\n * Block '<S31>/Constant17' : Unused code path elimination\r\n * Block '<S31>/Constant2' : Unused code path elimination\r\n * Block '<S54>/Brake_Saturation' : Unused code path elimination\r\n * Block '<S54>/Multiply5' : Unused code path elimination\r\n * Block '<S54>/Radius1' : Unused code path elimination\r\n * Block '<S60>/FixPt Data Type Duplicate' : Unused code path elimination\r\n * Block '<S65>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S65>/Data Type Propagation' : Unused code path elimination\r\n * Block '<S61>/FixPt Data Type Duplicate' : Unused code path elimination\r\n * Block '<S66>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S66>/Data Type Propagation' : Unused code path elimination\r\n * Block '<S12>/Scope2' : Unused code path elimination\r\n * Block '<S22>/FixPt Data Type Duplicate' : Unused code path elimination\r\n * Block '<S67>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S67>/Data Type Propagation' : Unused code path elimination\r\n * Block '<S23>/FixPt Data Type Duplicate' : Unused code path elimination\r\n * Block '<S68>/Data Type Duplicate' : Unused code path elimination\r\n * Block '<S68>/Data Type Propagation' : Unused code path elimination\r\n * Block '<S7>/ControlFlag' : Eliminated nontunable gain of 1\r\n * Block '<S31>/FBGain' : Eliminated nontunable gain of 1\r\n * Block '<S42>/FFGain' : Eliminated nontunable gain of 1\r\n * Block '<S1>/Data Type Conversion1' : Eliminate redundant data type conversion\r\n * Block '<S1>/Data Type Conversion3' : Eliminate redundant data type conversion\r\n * Block '<S54>/HAC_Gain' : Eliminated nontunable gain of 1\r\n * Block '<S60>/Zero-Order Hold' : Eliminated since input and output rates are identical\r\n * Block '<S61>/Zero-Order Hold' : Eliminated since input and output rates are identical\r\n * Block '<S22>/Zero-Order Hold' : Eliminated since input and output rates are identical\r\n * Block '<S23>/Zero-Order Hold' : Eliminated since input and output rates are identical\r\n */\r\n\r\n/*-\r\n * The generated code includes comments that allow you to trace directly\r\n * back to the appropriate location in the model.  The basic format\r\n * is <system>/block_name, where system is the system number (uniquely\r\n * assigned by Simulink) and block_name is the name of the block.\r\n *\r\n * Use the MATLAB hilite_system command to trace the generated code back\r\n * to the model.  For example,\r\n *\r\n * hilite_system('<S3>')    - opens system 3\r\n * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3\r\n *\r\n * Here is the system hierarchy for this model\r\n *\r\n * '<Root>' : 'ADM_Integrated_Logic'\r\n * '<S1>'   : 'ADM_Integrated_Logic/Delivery_Mobility'\r\n * '<S2>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Acceleration_Control'\r\n * '<S3>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Actuator_Fault_Decision'\r\n * '<S4>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant'\r\n * '<S5>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant1'\r\n * '<S6>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant2'\r\n * '<S7>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1'\r\n * '<S8>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Brake_Func'\r\n * '<S9>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Motor_Func'\r\n * '<S10>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Enabled Subsystem'\r\n * '<S11>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position'\r\n * '<S12>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1'\r\n * '<S13>'  : 'ADM_Integrated_Logic/Delivery_Mobility/IDB_Fault_Injection'\r\n * '<S14>'  : 'ADM_Integrated_Logic/Delivery_Mobility/LPFM5'\r\n * '<S15>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function'\r\n * '<S16>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function1'\r\n * '<S17>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function2'\r\n * '<S18>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function5'\r\n * '<S19>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function6'\r\n * '<S20>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MCU_Fault_Injection'\r\n * '<S21>'  : 'ADM_Integrated_Logic/Delivery_Mobility/RWA_Actuator_Fault_Injection'\r\n * '<S22>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic'\r\n * '<S23>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1'\r\n * '<S24>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic'\r\n * '<S25>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Acceleration_Control/Controller'\r\n * '<S26>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Acceleration_Control/MATLAB Function'\r\n * '<S27>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Acceleration_Control/Saturation Dynamic'\r\n * '<S28>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Acceleration_Control/Controller/Discrete Derivative'\r\n * '<S29>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB'\r\n * '<S30>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB_Gain'\r\n * '<S31>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller'\r\n * '<S32>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/GearCondition_Brake'\r\n * '<S33>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Gear_pos_out'\r\n * '<S34>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/LPFM'\r\n * '<S35>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Target_RPM'\r\n * '<S36>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot3'\r\n * '<S37>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot4'\r\n * '<S38>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot5'\r\n * '<S39>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/LPFM'\r\n * '<S40>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Second order LPF'\r\n * '<S41>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB'\r\n * '<S42>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF'\r\n * '<S43>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB/P'\r\n * '<S44>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot'\r\n * '<S45>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot2'\r\n * '<S46>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot3'\r\n * '<S47>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/LPFM'\r\n * '<S48>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Second order LPF'\r\n * '<S49>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Enabled Subsystem/MATLAB Function'\r\n * '<S50>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Compare To Constant'\r\n * '<S51>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Gear_FUNCTION1'\r\n * '<S52>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Chart'\r\n * '<S53>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/HAC_OFF_OK_Func'\r\n * '<S54>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2'\r\n * '<S55>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM'\r\n * '<S56>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM1'\r\n * '<S57>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM2'\r\n * '<S58>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM3'\r\n * '<S59>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Pitch_calculate'\r\n * '<S60>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic'\r\n * '<S61>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1'\r\n * '<S62>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_R'\r\n * '<S63>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c'\r\n * '<S64>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c1'\r\n * '<S65>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic/Saturation Dynamic'\r\n * '<S66>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1/Saturation Dynamic'\r\n * '<S67>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic/Saturation Dynamic'\r\n * '<S68>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1/Saturation Dynamic'\r\n * '<S69>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Compare To Constant'\r\n * '<S70>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Vx_OutPut_Function'\r\n */\r\n\r\n/*-\r\n * Requirements for '<Root>': ADM_Integrated_Logic\r\n\r\n */\r\n#endif                                 /* ADM_Integrated_Logic_h_ */\r\n\r\n/*\r\n * File trailer for generated code.\r\n *\r\n * [EOF]\r\n */\r\n"},{"name":"ADM_Integrated_Logic_data.c","type":"source","group":"data","path":"C:\\Users\\MSI\\Documents\\WorkSpace\\git\\ADM\\[ADM] Integrated Logic\\ADM_Integrated_Logic_ert_rtw","tag":"","groupDisplay":"Data files","code":"/*\r\n * Academic License - for use in teaching, academic research, and meeting\r\n * course requirements at degree granting institutions only.  Not for\r\n * government, commercial, or other organizational use.\r\n *\r\n * File: ADM_Integrated_Logic_data.c\r\n *\r\n * Code generated for Simulink model 'ADM_Integrated_Logic'.\r\n *\r\n * Model version                  : 14.26\r\n * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024\r\n * C/C++ source code generated on : Tue Oct 14 20:08:12 2025\r\n *\r\n * Target selection: ert.tlc\r\n * Embedded hardware selection: NXP->Cortex-M4\r\n * Code generation objectives:\r\n *    1. Execution efficiency\r\n *    2. RAM efficiency\r\n *    3. Debugging\r\n * Validation result: Not run\r\n */\r\n\r\n#include \"ADM_Integrated_Logic.h\"\r\n\r\n/* Invariant block signals (default storage) */\r\nconst ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB = {\r\n  12753.0,                             /* '<S54>/Multiply' */\r\n  12753.0                              /* '<S54>/Multiply4' */\r\n};\r\n\r\n/*\r\n * File trailer for generated code.\r\n *\r\n * [EOF]\r\n */\r\n"}],"coverage":[{"id":"SimulinkCoverage","name":"Simulink Coverage","files":[]},{"id":"Bullseye","name":"Bullseye Coverage","files":[]},{"id":"LDRA","name":"LDRA Testbed","files":[]}],"features":{"annotation":false,"coverage":true,"profiling":true,"tooltip":true,"coverageTooltip":true,"showJustificationLinks":true,"useMWTable":false,"showProfilingInfo":true,"showTaskSummary":true,"showProtectedV2Report":true}};