mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 09:53:59 +09:00
556 lines
10 KiB
Plaintext
556 lines
10 KiB
Plaintext
IntCtrl_Ip_SetTargetCores (IRQn_Type eIrqNumber, uint8 u8TargetCores)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_SetTargetCoresPrivileged (eIrqNumber, u8TargetCores);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetActive (IRQn_Type eIrqNumber)
|
|
{
|
|
boolean D.7739;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
D.7739 = IntCtrl_Ip_GetActivePrivileged (eIrqNumber);
|
|
return D.7739;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetPending (IRQn_Type eIrqNumber)
|
|
{
|
|
boolean D.7735;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
D.7735 = IntCtrl_Ip_GetPendingPrivileged (eIrqNumber);
|
|
return D.7735;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_SetPending (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_SetPendingPrivileged (eIrqNumber);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_ClearPending (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_ClearPendingPrivileged (eIrqNumber);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetPriority (IRQn_Type eIrqNumber)
|
|
{
|
|
uint8 D.7731;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
D.7731 = IntCtrl_Ip_GetPriorityPrivileged (eIrqNumber);
|
|
return D.7731;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_SetPriority (IRQn_Type eIrqNumber, uint8 u8Priority)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_SetPriorityPrivileged (eIrqNumber, u8Priority);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_DisableIrq (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_DisableIrqPrivileged (eIrqNumber);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_EnableIrq (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrqPrivileged (eIrqNumber);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_InstallHandler (IRQn_Type eIrqNumber, void (*IntCtrl_Ip_IrqHandlerType) (void) pfNewHandler, void (*IntCtrl_Ip_IrqHandlerType) (void) * const pfOldHandler)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandlerPrivileged (eIrqNumber, pfNewHandler, pfOldHandler);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_ConfigIrqRouting (const struct IntCtrl_Ip_GlobalRouteConfigType * routeConfig)
|
|
{
|
|
uint32 irqIdx;
|
|
IntCtrl_Ip_StatusType D.7727;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = routeConfig != 0B;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = routeConfig->u32ConfigIrqCount;
|
|
_3 = _2 <= 206;
|
|
DevAssert (_3);
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
irqIdx = 0;
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_4 = routeConfig->aIrqConfig;
|
|
_5 = irqIdx * 8;
|
|
_6 = _4 + _5;
|
|
_7 = _6->eIrqNumber;
|
|
_8 = routeConfig->aIrqConfig;
|
|
_9 = irqIdx * 8;
|
|
_10 = _8 + _9;
|
|
_11 = _10->u8TargetCores;
|
|
IntCtrl_Ip_SetTargetCores (_7, _11);
|
|
# DEBUG BEGIN_STMT
|
|
_12 = routeConfig->aIrqConfig;
|
|
_13 = irqIdx * 8;
|
|
_14 = _12 + _13;
|
|
_15 = _14->eIrqNumber;
|
|
_16 = routeConfig->aIrqConfig;
|
|
_17 = irqIdx * 8;
|
|
_18 = _16 + _17;
|
|
_19 = _18->pfHandler;
|
|
IntCtrl_Ip_InstallHandler (_15, _19, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
irqIdx = irqIdx + 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_20 = routeConfig->u32ConfigIrqCount;
|
|
if (irqIdx < _20)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
D.7727 = 0;
|
|
return D.7727;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_Init (const struct IntCtrl_Ip_CtrlConfigType * pIntCtrlCtrlConfig)
|
|
{
|
|
uint32 irqIdx;
|
|
IntCtrl_Ip_StatusType D.7722;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = pIntCtrlCtrlConfig != 0B;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = pIntCtrlCtrlConfig->u32ConfigIrqCount;
|
|
_3 = _2 <= 206;
|
|
DevAssert (_3);
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
irqIdx = 0;
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_4 = pIntCtrlCtrlConfig->aIrqConfig;
|
|
_5 = irqIdx * 4;
|
|
_6 = _4 + _5;
|
|
_7 = _6->eIrqNumber;
|
|
_8 = pIntCtrlCtrlConfig->aIrqConfig;
|
|
_9 = irqIdx * 4;
|
|
_10 = _8 + _9;
|
|
_11 = _10->u8IrqPriority;
|
|
IntCtrl_Ip_SetPriority (_7, _11);
|
|
# DEBUG BEGIN_STMT
|
|
_12 = pIntCtrlCtrlConfig->aIrqConfig;
|
|
_13 = irqIdx * 4;
|
|
_14 = _12 + _13;
|
|
_15 = _14->bIrqEnabled;
|
|
if (_15 != 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_16 = pIntCtrlCtrlConfig->aIrqConfig;
|
|
_17 = irqIdx * 4;
|
|
_18 = _16 + _17;
|
|
_19 = _18->eIrqNumber;
|
|
IntCtrl_Ip_EnableIrq (_19);
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_20 = pIntCtrlCtrlConfig->aIrqConfig;
|
|
_21 = irqIdx * 4;
|
|
_22 = _20 + _21;
|
|
_23 = _22->eIrqNumber;
|
|
IntCtrl_Ip_DisableIrq (_23);
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
irqIdx = irqIdx + 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_24 = pIntCtrlCtrlConfig->u32ConfigIrqCount;
|
|
if (irqIdx < _24)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
D.7722 = 0;
|
|
return D.7722;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_SetTargetCoresPrivileged (IRQn_Type eIrqNumber, uint8 u8TargetCores)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 1076232192B;
|
|
_4 = (int) eIrqNumber;
|
|
_5 = _3->IRSPRC[_4];
|
|
_6 = (signed short) _5;
|
|
_7 = _6 >= 0;
|
|
DevAssert (_7);
|
|
# DEBUG BEGIN_STMT
|
|
_8 = 1076232192B;
|
|
_9 = (int) eIrqNumber;
|
|
_10 = (short unsigned int) u8TargetCores;
|
|
_8->IRSPRC[_9] = _10;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetActivePrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
boolean D.7741;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 3758153728B;
|
|
_4 = (long unsigned int) eIrqNumber;
|
|
_5 = _4 >> 5;
|
|
_6 = _3->IABR[_5];
|
|
eIrqNumber.8_7 = (unsigned short) eIrqNumber;
|
|
_8 = (long unsigned int) eIrqNumber.8_7;
|
|
_9 = _8 & 31;
|
|
_10 = _6 >> _9;
|
|
_11 = _10 & 1;
|
|
D.7741 = _11 != 0;
|
|
return D.7741;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetPendingPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
boolean D.7737;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 3758153728B;
|
|
_4 = (long unsigned int) eIrqNumber;
|
|
_5 = _4 >> 5;
|
|
_6 = _3->ISPR[_5];
|
|
eIrqNumber.7_7 = (unsigned short) eIrqNumber;
|
|
_8 = (long unsigned int) eIrqNumber.7_7;
|
|
_9 = _8 & 31;
|
|
_10 = _6 >> _9;
|
|
_11 = _10 & 1;
|
|
D.7737 = _11 != 0;
|
|
return D.7737;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_SetPendingPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
eIrqNumber.6_3 = (unsigned short) eIrqNumber;
|
|
_4 = (long unsigned int) eIrqNumber.6_3;
|
|
_5 = _4 & 31;
|
|
_6 = 3758153728B;
|
|
_7 = (long unsigned int) eIrqNumber;
|
|
_8 = _7 >> 5;
|
|
_9 = 1 << _5;
|
|
_6->ISPR[_8] = _9;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_ClearPendingPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
eIrqNumber.5_3 = (unsigned short) eIrqNumber;
|
|
_4 = (long unsigned int) eIrqNumber.5_3;
|
|
_5 = _4 & 31;
|
|
_6 = 3758153728B;
|
|
_7 = (long unsigned int) eIrqNumber;
|
|
_8 = _7 >> 5;
|
|
_9 = 1 << _5;
|
|
_6->ICPR[_8] = _9;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_GetPriorityPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
uint8 shift;
|
|
uint8 priority;
|
|
uint8 D.7733;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
shift = 4;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 3758153728B;
|
|
_4 = (long unsigned int) eIrqNumber;
|
|
_5 = _3->IP[_4];
|
|
_6 = (int) _5;
|
|
_7 = (int) shift;
|
|
_8 = _6 >> _7;
|
|
priority = (uint8) _8;
|
|
# DEBUG BEGIN_STMT
|
|
D.7733 = priority;
|
|
return D.7733;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_SetPriorityPrivileged (IRQn_Type eIrqNumber, uint8 u8Priority)
|
|
{
|
|
uint8 shift;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = u8Priority <= 15;
|
|
DevAssert (_3);
|
|
# DEBUG BEGIN_STMT
|
|
shift = 4;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (long unsigned int) u8Priority;
|
|
_5 = (int) shift;
|
|
_6 = _4 << _5;
|
|
_7 = 3758153728B;
|
|
_8 = (long unsigned int) eIrqNumber;
|
|
_9 = (unsigned char) _6;
|
|
_7->IP[_8] = _9;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_DisableIrqPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
eIrqNumber.4_3 = (unsigned short) eIrqNumber;
|
|
_4 = (long unsigned int) eIrqNumber.4_3;
|
|
_5 = _4 & 31;
|
|
_6 = 3758153728B;
|
|
_7 = (long unsigned int) eIrqNumber;
|
|
_8 = _7 >> 5;
|
|
_9 = 1 << _5;
|
|
_6->ICER[_8] = _9;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_EnableIrqPrivileged (IRQn_Type eIrqNumber)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = eIrqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = eIrqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
eIrqNumber.3_3 = (unsigned short) eIrqNumber;
|
|
_4 = (long unsigned int) eIrqNumber.3_3;
|
|
_5 = _4 & 31;
|
|
_6 = 3758153728B;
|
|
_7 = (long unsigned int) eIrqNumber;
|
|
_8 = _7 >> 5;
|
|
_9 = 1 << _5;
|
|
_6->ISER[_8] = _9;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntCtrl_Ip_InstallHandlerPrivileged (IRQn_Type eIrqNumber, void (*IntCtrl_Ip_IrqHandlerType) (void) pfNewHandler, void (*IntCtrl_Ip_IrqHandlerType) (void) * const pfOldHandler)
|
|
{
|
|
uint32 * pVectorRam;
|
|
sint32 dev_irqNumber;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
dev_irqNumber = (sint32) eIrqNumber;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = dev_irqNumber >= 0;
|
|
DevAssert (_1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = dev_irqNumber <= 207;
|
|
DevAssert (_2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 3758153728B;
|
|
_4 = _3->VTOR;
|
|
__INT_SRAM_START.1_5 = (long unsigned int) &__INT_SRAM_START;
|
|
_6 = _4 >= __INT_SRAM_START.1_5;
|
|
DevAssert (_6);
|
|
# DEBUG BEGIN_STMT
|
|
_7 = 3758153728B;
|
|
_8 = _7->VTOR;
|
|
pVectorRam = (uint32 *) _8;
|
|
# DEBUG BEGIN_STMT
|
|
if (pfOldHandler != 0B)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (sizetype) eIrqNumber;
|
|
_10 = _9 + 16;
|
|
_11 = _10 * 4;
|
|
_12 = pVectorRam + _11;
|
|
_13 = *_12;
|
|
_14 = (void (*<T5b7>) (void)) _13;
|
|
*pfOldHandler = _14;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_15 = (sizetype) eIrqNumber;
|
|
_16 = _15 + 16;
|
|
_17 = _16 * 4;
|
|
_18 = pVectorRam + _17;
|
|
pfNewHandler.2_19 = (long unsigned int) pfNewHandler;
|
|
*_18 = pfNewHandler.2_19;
|
|
# DEBUG BEGIN_STMT
|
|
_20 = 3758153728B;
|
|
_20->ICIALLU = 0;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
DevAssert (volatile boolean x)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
x.0_1 = x;
|
|
if (x.0_1 != 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 3>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 3>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|