mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 01:43:59 +09:00
4424 lines
314 KiB
XML
4424 lines
314 KiB
XML
<?xml version="1.0" encoding= "UTF-8" ?>
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<configuration name="S32K344" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_10 http://mcuxpresso.nxp.com/XSD/mex_configuration_10.xsd" uuid="cb0a0571-31b0-4026-b225-2a0da4ce6ac1" version="10" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_10" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<common>
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<processor>S32K344</processor>
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<package>S32K344_172MQFP</package>
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<mcu_data>PlatformSDK_S32K3_2021_03</mcu_data>
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<cores selected="core0">
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<core name="Cortex-M7" id="core0" description=""/>
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</cores>
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<description></description>
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</common>
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<preferences>
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<validate_boot_init_only>true</validate_boot_init_only>
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<generate_extended_information>false</generate_extended_information>
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<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
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<update_include_paths>true</update_include_paths>
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</preferences>
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<tools>
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<pins name="Pins" version="10.0" enabled="true" update_project_code="true">
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<generated_project_files>
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<file path="board/Siul2_Port_Ip_Cfg.c" update_enabled="true"/>
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<file path="board/Siul2_Port_Ip_Cfg.h" update_enabled="true"/>
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</generated_project_files>
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<pins_profile>
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<processor_version>0.0.0</processor_version>
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<pin_labels>
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<pin_label pin_num="145" pin_signal="PTA15" label="DOUT_6" identifier="DOUT_6"/>
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<pin_label pin_num="143" pin_signal="PTA16" label="DOUT_7" identifier="DOUT_7"/>
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<pin_label pin_num="138" pin_signal="PTD30" label="CAN5_EN" identifier="CAN5_EN"/>
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<pin_label pin_num="142" pin_signal="PTE17" label="CAN5_STB_N" identifier="CAN5_STB_N"/>
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<pin_label pin_num="95" pin_signal="PTB0" label="CAN3_EN" identifier="CAN3_EN"/>
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<pin_label pin_num="94" pin_signal="PTB1" label="CAN3_STB_N" identifier="CAN3_STB_N"/>
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<pin_label pin_num="88" pin_signal="PTC24" label="CAN0_EN" identifier="CAN0_EN"/>
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<pin_label pin_num="86" pin_signal="PTC21" label="CAN0_STB_N" identifier="CAN0_STB_N"/>
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<pin_label pin_num="122" pin_signal="PTD23" label="CAN1_EN" identifier="CAN1_EN"/>
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<pin_label pin_num="121" pin_signal="PTD2" label="CAN1_STB_N" identifier="CAN1_STB_N"/>
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<pin_label pin_num="41" pin_signal="PTD13" label="I2C0_SDA" identifier="I2C0_SDA"/>
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<pin_label pin_num="40" pin_signal="PTD14" label="I2C0_SCL" identifier="I2C0_SCL"/>
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<pin_label pin_num="119" pin_signal="PTD4" label="CAN2_EN" identifier="CAN2_EN"/>
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<pin_label pin_num="91" pin_signal="PTC26" label="CAN4_EN" identifier="CAN4_EN"/>
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<pin_label pin_num="118" pin_signal="PTD22" label="CAN2_STB_N" identifier="CAN2_STB_N"/>
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<pin_label pin_num="89" pin_signal="PTC25" label="CAN4_STB_N" identifier="CAN4_STB_N"/>
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<pin_label pin_num="160" pin_signal="PTA11" label="DIN_1" identifier="DIN_1"/>
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<pin_label pin_num="9" pin_signal="PTE11" label="AIN_0" identifier="AIN_0"/>
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<pin_label pin_num="159" pin_signal="PTA12" label="DOUT_2" identifier="DOUT_2"/>
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<pin_label pin_num="117" pin_signal="PTB12" label="PWM_0" identifier="PWM_0"/>
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<pin_label pin_num="116" pin_signal="PTB13" label="PWM_1" identifier="PWM_1"/>
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<pin_label pin_num="114" pin_signal="PTB14" label="PWM_2" identifier="PWM_2"/>
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<pin_label pin_num="113" pin_signal="PTB15" label="PWM_3" identifier="PWM_3"/>
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<pin_label pin_num="163" pin_signal="PTE0" label="AIN_1" identifier="AIN_1"/>
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<pin_label pin_num="153" pin_signal="PTE21" label="AIN_2" identifier="AIN_2"/>
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<pin_label pin_num="154" pin_signal="PTE22" label="AIN_3" identifier="AIN_3"/>
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<pin_label pin_num="156" pin_signal="PTE23" label="AIN_4" identifier="AIN_4"/>
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<pin_label pin_num="13" pin_signal="PTE4" label="SPI1_CS1" identifier="SPI1_CS1"/>
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<pin_label pin_num="6" pin_signal="PTA21" label="SPI1_CS0" identifier="SPI1_CS0"/>
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<pin_label pin_num="30" pin_signal="PTA28" label="SPI1_SCK" identifier="SPI1_SCK"/>
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<pin_label pin_num="32" pin_signal="PTA29" label="SPI1_MOSI" identifier="SPI1_MOSI"/>
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<pin_label pin_num="33" pin_signal="PTA30" label="SPI1_MISO" identifier="SPI1_MISO"/>
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<pin_label pin_num="63" pin_signal="PTD9" label="I2C1_SCL" identifier="I2C1_SCL"/>
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<pin_label pin_num="64" pin_signal="PTD8" label="I2C1_SDA" identifier="I2C1_SDA"/>
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<pin_label pin_num="72" pin_signal="PTB25" label="SPI2_CS0" identifier="SPI2_CS0"/>
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<pin_label pin_num="74" pin_signal="PTB3" label="UART9_TX" identifier="UART9_TX"/>
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<pin_label pin_num="75" pin_signal="PTB27" label="SPI2_MISO" identifier="SPI2_MISO"/>
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<pin_label pin_num="76" pin_signal="PTB28" label="SPI2_MOSI" identifier="SPI2_MOSI"/>
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<pin_label pin_num="79" pin_signal="PTB2" label="UART9_RX" identifier="UART9_RX"/>
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<pin_label pin_num="81" pin_signal="PTC13" label="UART10_TX" identifier="UART10_TX"/>
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<pin_label pin_num="82" pin_signal="PTC18" label="TEST_LED" identifier="TEST_LED"/>
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<pin_label pin_num="137" pin_signal="PTA0" label="DOUT_0" identifier="DOUT_0"/>
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<pin_label pin_num="124" pin_signal="PTA2" label="UART0_RX" identifier="LPUART0_RX;UART0_RX"/>
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<pin_label pin_num="123" pin_signal="PTA3" label="UART0_TX" identifier="LPUART0_TX;UART0_TX"/>
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<pin_label pin_num="170" pin_signal="PTA4" label="JTAG_TMS/SWD_DIO"/>
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<pin_label pin_num="167" pin_signal="PTA5" label="RESET_MCU"/>
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<pin_label pin_num="102" pin_signal="PTA6" label="CAN0_RX" identifier="CAN0_RX"/>
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<pin_label pin_num="100" pin_signal="PTA7" label="CAN0_TX" identifier="CAN0_TX"/>
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<pin_label pin_num="172" pin_signal="PTA8" label="UART2_RX" identifier="UART2_RX"/>
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<pin_label pin_num="171" pin_signal="PTA9" label="UART2_TX" identifier="UART2_TX"/>
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<pin_label pin_num="161" pin_signal="PTA10" label="JTAG_TDO" identifier="JTAG_TDO"/>
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<pin_label pin_num="155" pin_signal="PTA13" label="DOUT_4" identifier="DOUT_4"/>
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<pin_label pin_num="152" pin_signal="PTA14" label="DOUT_5" identifier="DOUT_5"/>
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<pin_label pin_num="14" pin_signal="PTA24" label="PTA21" identifier=""/>
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<pin_label pin_num="39" pin_signal="PTA31" label="PTA31"/>
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<pin_label pin_num="62" pin_signal="PTC0" label="ENET_RMII_RXD0"/>
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<pin_label pin_num="61" pin_signal="PTC1" label="ENET_RMII_RXD1"/>
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<pin_label pin_num="166" pin_signal="PTC4" label="JTAG_TCLK/SWD_CLK"/>
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<pin_label pin_num="165" pin_signal="PTC5" label="JTAG_TDI"/>
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<pin_label pin_num="141" pin_signal="PTC6" label="UART1_RX" identifier="UART1_RX"/>
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<pin_label pin_num="140" pin_signal="PTC7" label="UART1_TX" identifier="UART1_TX"/>
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<pin_label pin_num="98" pin_signal="PTC8" label="CAN1_TX" identifier="CAN1_TX"/>
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<pin_label pin_num="97" pin_signal="PTC9" label="CAN1_RX" identifier="CAN1_RX"/>
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<pin_label pin_num="92" pin_signal="PTC10" label="CAN5_TX" identifier="CAN5_TX"/>
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<pin_label pin_num="90" pin_signal="PTC11" label="CAN5_RX" identifier="CAN5_RX"/>
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<pin_label pin_num="83" pin_signal="PTC12" label="UART10_RX" identifier="UART10_RX"/>
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<pin_label pin_num="71" pin_signal="PTC14" label="ENET_RMII_RX_ER"/>
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<pin_label pin_num="68" pin_signal="PTC15" label="ENET_RMII_CRS_DV"/>
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<pin_label pin_num="84" pin_signal="PTC19" label="SPI2_CS1" identifier="SPI2_CS1"/>
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<pin_label pin_num="85" pin_signal="PTC20" label="CAN0_ERR_N"/>
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<pin_label pin_num="87" pin_signal="PTC23" label="CAN4_ERR_N"/>
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<pin_label pin_num="93" pin_signal="PTC27" label="CAN3_ERR_N"/>
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<pin_label pin_num="96" pin_signal="PTC28" label="CAN3_TX" identifier="CAN3_TX"/>
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<pin_label pin_num="99" pin_signal="PTC29" label="CAN3_RX" identifier="CAN3_RX"/>
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<pin_label pin_num="101" pin_signal="PTC30" label="CAN4_TX" identifier="CAN4_TX"/>
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<pin_label pin_num="103" pin_signal="PTC31" label="CAN4_RX" identifier="CAN4_RX"/>
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<pin_label pin_num="27" pin_signal="PTE3" label="ENET_PPS"/>
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<pin_label pin_num="46" pin_signal="PTE8" label="ENET_RMII_MDC"/>
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<pin_label pin_num="36" pin_signal="PTE9" label="ENET_RMII_TX_EN"/>
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<pin_label pin_num="10" pin_signal="PTE10" label="VRC_CTRL" identifier="VRC_CTRL"/>
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<pin_label pin_num="157" pin_signal="PTE24" label="CAN2_TX" identifier="CAN2_TX"/>
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<pin_label pin_num="158" pin_signal="PTE25" label="CAN2_RX" identifier="CAN2_RX"/>
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<pin_label pin_num="48" pin_signal="PTB4" label="ENET_RMII_TXD1"/>
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<pin_label pin_num="47" pin_signal="PTB5" label="ENET_RMII_TXD0"/>
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<pin_label pin_num="133" pin_signal="PTB8" label="DIN_0" identifier="DIN_0"/>
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<pin_label pin_num="126" pin_signal="PTB11" label="DIN_3" identifier="DIN_3"/>
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<pin_label pin_num="42" pin_signal="PTB18" label="UART13_TX" identifier="UART13_TX"/>
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<pin_label pin_num="43" pin_signal="PTB19" label="UART13_RX" identifier="UART13_RX"/>
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<pin_label pin_num="44" pin_signal="PTB20" label="DIN_4" identifier="DIN_4"/>
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<pin_label pin_num="45" pin_signal="PTB21" label="DIN_5" identifier="DIN_5"/>
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<pin_label pin_num="67" pin_signal="PTB22" label="ENET_RST_N"/>
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<pin_label pin_num="69" pin_signal="PTB23" label="ENET_WAKE_IN_OUT"/>
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<pin_label pin_num="70" pin_signal="PTB24" label="DIN_6" identifier="DIN_6"/>
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<pin_label pin_num="73" pin_signal="PTB26" label="DIN_7" identifier="DIN_7"/>
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<pin_label pin_num="80" pin_signal="PTB29" label="SPI2_SCK" identifier="SPI2_SCK"/>
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<pin_label pin_num="120" pin_signal="PTD3" label="CAN1_ERR_N"/>
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<pin_label pin_num="53" pin_signal="PTD5" label="ENET_INT_N"/>
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<pin_label pin_num="52" pin_signal="PTD6" label="ENET_RMII_REF_CLK"/>
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<pin_label pin_num="34" pin_signal="PTD16" label="ENET_RMII_MDIO"/>
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<pin_label pin_num="115" pin_signal="PTD21" label="CAN2_ERR_N"/>
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<pin_label pin_num="125" pin_signal="PTD24" label="CAN5_ERR_N"/>
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<pin_label pin_num="164" pin_signal="PTE26" label="DOUT_1" identifier="DOUT_1"/>
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<pin_label pin_num="1" pin_signal="PTA18" label="DOUT_3" identifier="DOUT_3"/>
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<pin_label pin_num="162" pin_signal="PTE1" label="DIN_2" identifier="DIN_2"/>
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<pin_label pin_num="11" pin_signal="PTE13" label="AIN_BAT" identifier="AIN_BAT"/>
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<pin_label pin_num="25" pin_signal="PTA26" label="XTAL"/>
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</pin_labels>
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</pins_profile>
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<functions_list>
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<function name="BOARD_InitPins">
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<description>Configures pin routing and optionally pin electrical features.</description>
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<options>
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<callFromInitBoot>true</callFromInitBoot>
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<coreID>core0</coreID>
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</options>
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<dependencies>
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<dependency resourceType="SWComponent" resourceId="platform.driver.pins" description="Pins initialization requires the PINS Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
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<feature name="enabled" evaluation="equal" configuration="core0">
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<data>true</data>
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</feature>
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</dependency>
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</dependencies>
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<pins>
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<pin peripheral="LPUART_0" signal="lpuart_rx" pin_num="124" pin_signal="PTA2">
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<pin_features>
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<pin_feature name="identifier" value="UART0_RX"/>
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</pin_features>
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</pin>
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<pin peripheral="LPUART_0" signal="lpuart_tx" pin_num="123" pin_signal="PTA3">
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<pin_features>
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<pin_feature name="identifier" value="UART0_TX"/>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="FlexCAN_0" signal="rxd" pin_num="102" pin_signal="PTA6"/>
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<pin peripheral="FlexCAN_0" signal="txd" pin_num="100" pin_signal="PTA7"/>
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<pin peripheral="SIUL2" signal="gpio, 88" pin_num="88" pin_signal="PTC24">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 85" pin_num="86" pin_signal="PTC21">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="FlexCAN_1" signal="txd" pin_num="98" pin_signal="PTC8"/>
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<pin peripheral="FlexCAN_1" signal="rxd" pin_num="97" pin_signal="PTC9"/>
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<pin peripheral="SIUL2" signal="gpio, 119" pin_num="122" pin_signal="PTD23">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 98" pin_num="121" pin_signal="PTD2">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="FlexCAN_2" signal="txd" pin_num="157" pin_signal="PTE24"/>
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<pin peripheral="FlexCAN_3" signal="txd" pin_num="96" pin_signal="PTC28"/>
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<pin peripheral="FlexCAN_3" signal="rxd" pin_num="99" pin_signal="PTC29"/>
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<pin peripheral="FlexCAN_4" signal="txd" pin_num="101" pin_signal="PTC30"/>
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<pin peripheral="FlexCAN_4" signal="rxd" pin_num="103" pin_signal="PTC31"/>
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<pin peripheral="FlexCAN_5" signal="txd" pin_num="92" pin_signal="PTC10"/>
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<pin peripheral="FlexCAN_5" signal="rxd" pin_num="90" pin_signal="PTC11"/>
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<pin peripheral="SIUL2" signal="gpio, 100" pin_num="119" pin_signal="PTD4">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 32" pin_num="95" pin_signal="PTB0">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 90" pin_num="91" pin_signal="PTC26">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 126" pin_num="138" pin_signal="PTD30">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 118" pin_num="118" pin_signal="PTD22">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 33" pin_num="94" pin_signal="PTB1">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 89" pin_num="89" pin_signal="PTC25">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 145" pin_num="142" pin_signal="PTE17">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="LPUART_1" signal="lpuart_tx" pin_num="140" pin_signal="PTC7">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="LPUART_1" signal="lpuart_rx" pin_num="141" pin_signal="PTC6"/>
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<pin peripheral="LPUART_10" signal="lpuart_rx" pin_num="83" pin_signal="PTC12"/>
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<pin peripheral="ADC_2" signal="p_in, 3" pin_num="153" pin_signal="PTE21"/>
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<pin peripheral="ADC_2" signal="p_in, 4" pin_num="154" pin_signal="PTE22"/>
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<pin peripheral="ADC_2" signal="p_in, 5" pin_num="156" pin_signal="PTE23"/>
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<pin peripheral="SIUL2" signal="gpio, 12" pin_num="159" pin_signal="PTA12">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="eMIOS_0" signal="ch_g, 1" pin_num="116" pin_signal="PTB13">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="eMIOS_0" signal="ch_g, 2" pin_num="114" pin_signal="PTB14">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="eMIOS_0" signal="ch_g, 3" pin_num="113" pin_signal="PTB15">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="eMIOS_0" signal="ch_x, 0" pin_num="117" pin_signal="PTB12">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="ADC_1" signal="p_in, 2" pin_num="163" pin_signal="PTE0"/>
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<pin peripheral="SIUL2" signal="gpio, 82" pin_num="82" pin_signal="PTC18">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 0" pin_num="137" pin_signal="PTA0">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="LPUART_2" signal="lpuart_rx" pin_num="172" pin_signal="PTA8"/>
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<pin peripheral="LPUART_2" signal="lpuart_tx" pin_num="171" pin_signal="PTA9">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
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<pin peripheral="SIUL2" signal="gpio, 14" pin_num="152" pin_signal="PTA14">
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<pin_features>
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<pin_feature name="direction" value="OUTPUT"/>
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</pin_features>
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</pin>
|
|
<pin peripheral="LPSPI_1" signal="lpspi_pcs, 0" pin_num="6" pin_signal="PTA21">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_1" signal="lpspi_sck, sck" pin_num="30" pin_signal="PTA28">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_1" signal="lpspi_sout" pin_num="33" pin_signal="PTA30">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPUART_10" signal="lpuart_tx" pin_num="81" pin_signal="PTC13">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_2" signal="lpspi_pcs, 1" pin_num="84" pin_signal="PTC19">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_1" signal="lpspi_pcs, 1" pin_num="13" pin_signal="PTE4">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPUART_9" signal="lpuart_rx" pin_num="79" pin_signal="PTB2"/>
|
|
<pin peripheral="LPUART_9" signal="lpuart_tx" pin_num="74" pin_signal="PTB3">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 40" pin_num="133" pin_signal="PTB8">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 43" pin_num="126" pin_signal="PTB11">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPUART_13" signal="lpuart_tx" pin_num="42" pin_signal="PTB18">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPUART_13" signal="lpuart_rx" pin_num="43" pin_signal="PTB19"/>
|
|
<pin peripheral="SIUL2" signal="gpio, 52" pin_num="44" pin_signal="PTB20">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 53" pin_num="45" pin_signal="PTB21">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 56" pin_num="70" pin_signal="PTB24">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_2" signal="lpspi_pcs, 0" pin_num="72" pin_signal="PTB25">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 58" pin_num="73" pin_signal="PTB26">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_2" signal="lpspi_sout" pin_num="75" pin_signal="PTB27">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_2" signal="lpspi_sin" pin_num="76" pin_signal="PTB28">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPSPI_2" signal="lpspi_sck, sck" pin_num="80" pin_signal="PTB29">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPI2C_1" signal="lpi2c_sda, sda" pin_num="64" pin_signal="PTD8">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPI2C_1" signal="lpi2c_scl, scl" pin_num="63" pin_signal="PTD9">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 13" pin_num="155" pin_signal="PTA13">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 15" pin_num="145" pin_signal="PTA15">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 16" pin_num="143" pin_signal="PTA16">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="FlexCAN_2" signal="rxd" pin_num="158" pin_signal="PTE25"/>
|
|
<pin peripheral="LPI2C_0" signal="lpi2c_scl, scl" pin_num="40" pin_signal="PTD14">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="LPI2C_0" signal="lpi2c_sda, sda" pin_num="41" pin_signal="PTD13">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 11" pin_num="160" pin_signal="PTA11">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 18" pin_num="1" pin_signal="PTA18">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 129" pin_num="162" pin_signal="PTE1">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="INPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="SIUL2" signal="gpio, 154" pin_num="164" pin_signal="PTE26">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="ADC_0" signal="p_in, 6" pin_num="9" pin_signal="PTE11"/>
|
|
<pin peripheral="SIUL2" signal="gpio, 138" pin_num="10" pin_signal="PTE10">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
<pin peripheral="ADC_1" signal="s_in, 19" pin_num="11" pin_signal="PTE13"/>
|
|
<pin peripheral="LPSPI_1" signal="lpspi_sin" pin_num="32" pin_signal="PTA29">
|
|
<pin_features>
|
|
<pin_feature name="direction" value="OUTPUT"/>
|
|
</pin_features>
|
|
</pin>
|
|
</pins>
|
|
</function>
|
|
</functions_list>
|
|
</pins>
|
|
<clocks name="Clocks" version="8.0" enabled="true" update_project_code="true">
|
|
<generated_project_files>
|
|
<file path="board/Clock_Ip_Cfg.c" update_enabled="true"/>
|
|
<file path="board/Clock_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="board/Clock_Ip_PBcfg.c" update_enabled="true"/>
|
|
<file path="board/Clock_Ip_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
|
|
</generated_project_files>
|
|
<clocks_profile>
|
|
<processor_version>0.0.0</processor_version>
|
|
</clocks_profile>
|
|
<clock_configurations>
|
|
<clock_configuration name="BOARD_BootClockRUN">
|
|
<description></description>
|
|
<options/>
|
|
<dependencies>
|
|
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: FXOSC_CLK.EXTAL, Clocks tool id: FXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="routed" evaluation="">
|
|
<data>true</data>
|
|
</feature>
|
|
<feature name="direction" evaluation="">
|
|
<data>INPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: FXOSC_CLK.EXTAL, Clocks tool id: FXOSC_CLK.EXTAL) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="direction" evaluation="">
|
|
<data>INPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.XTAL" description="'External pin' (Pins tool id: FXOSC_CLK.XTAL, Clocks tool id: FXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="routed" evaluation="">
|
|
<data>true</data>
|
|
</feature>
|
|
<feature name="direction" evaluation="">
|
|
<data>OUTPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="FXOSC_CLK.XTAL" description="'External pin' (Pins tool id: FXOSC_CLK.XTAL, Clocks tool id: FXOSC_CLK.XTAL) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="direction" evaluation="">
|
|
<data>OUTPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: SXOSC_CLK.EXTAL, Clocks tool id: SXOSC_CLK.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="routed" evaluation="">
|
|
<data>true</data>
|
|
</feature>
|
|
<feature name="direction" evaluation="">
|
|
<data>INPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.EXTAL" description="'External pin' (Pins tool id: SXOSC_CLK.EXTAL, Clocks tool id: SXOSC_CLK.EXTAL) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="direction" evaluation="">
|
|
<data>INPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.XTAL" description="'External pin' (Pins tool id: SXOSC_CLK.XTAL, Clocks tool id: SXOSC_CLK.XTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="routed" evaluation="">
|
|
<data>true</data>
|
|
</feature>
|
|
<feature name="direction" evaluation="">
|
|
<data>OUTPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="PinSignal" resourceId="SXOSC_CLK.XTAL" description="'External pin' (Pins tool id: SXOSC_CLK.XTAL, Clocks tool id: SXOSC_CLK.XTAL) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="direction" evaluation="">
|
|
<data>OUTPUT</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
|
<feature name="enabled" evaluation="equal" configuration="core0">
|
|
<data>true</data>
|
|
</feature>
|
|
</dependency>
|
|
</dependencies>
|
|
<clock_sources>
|
|
<clock_source id="FXOSC_CLK.FXOSC_CLK.outFreq" value="16 MHz" locked="false" enabled="true"/>
|
|
<clock_source id="SXOSC_CLK.SXOSC_CLK.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
|
|
</clock_sources>
|
|
<clock_outputs>
|
|
<clock_output id="ADC0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="ADC1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="ADC2_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="AIPS_PLAT_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="AIPS_SLOW_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="BCTU0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CLKOUT_RUN_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CLKOUT_STANDBY_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CMP0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CMP1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CMP2_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CORE_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="CRC0_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="DCM0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="DCM_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="DMAMUX0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="DMAMUX1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD10_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD11_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD12_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD13_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD14_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD15_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD16_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD17_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD18_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD19_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD20_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD21_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD22_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD23_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD24_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD25_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD26_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD27_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD28_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD29_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD2_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD30_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD31_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD3_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD4_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD5_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD6_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD7_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD8_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EDMA0_TCD9_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EIM0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC0_RX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC0_TS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC0_TX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC_RX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC_TS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMAC_TX_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMIOS0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMIOS1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="EMIOS2_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="ERM0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FIRCOUT.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLASH0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN0_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN1_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN2_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN3_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN4_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCAN5_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCANA_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXCANB_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FLEXIO0_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="FXOSCOUT.outFreq" value="16 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="HSE_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="INTM_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LBIST_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LCU0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LCU1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPI2C0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPI2C1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI0_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI2_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI3_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI4_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPSPI5_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART0_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART10_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART11_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART12_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART13_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART14_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART15_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART2_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART3_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART4_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART5_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART6_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART7_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART8_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="LPUART9_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="MSCM_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="MUA_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="MUB_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="PIT0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="PIT1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="PIT2_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="PLL_PHI0.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="PLL_PHI1.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="QSPI0_RAM_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="QSPI0_SFCK.outFreq" value="16 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="QSPI0_TX_MEM_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="QSPI_MEM_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="QSPI_SFCK_CLK.outFreq" value="16 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="RTC0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="RTC_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="SAI0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="SAI1_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="SEMA42_CLK.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="SIRCOUT.outFreq" value="32 kHz" locked="false" accuracy=""/>
|
|
<clock_output id="SIUL0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="STCU0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="STM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="STM1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="STMA_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="STMB_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="SWT0_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
|
|
<clock_output id="SWT1_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
|
|
<clock_output id="SXOSCOUT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
|
|
<clock_output id="TCM_CM7_0_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="TCM_CM7_1_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="TEMPSENSE_CLK.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="TRACE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="TRGMUX0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="TSENSE0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
<clock_output id="WKPU0_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
|
</clock_outputs>
|
|
<clock_settings>
|
|
<setting id="CORE_MFD.scale" value="120" locked="true"/>
|
|
<setting id="CORE_PLLODIV_0_DE" value="Enabled" locked="false"/>
|
|
<setting id="CORE_PLLODIV_1_DE" value="Enabled" locked="false"/>
|
|
<setting id="CORE_PLL_PD" value="Power_up" locked="false"/>
|
|
<setting id="FXOSC_PM" value="Crystal_mode" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0.sel" value="PHI0" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV0.scale" value="1" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV0_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV1.scale" value="2" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV1_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV2.scale" value="4" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV2_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV3.scale" value="2" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV3_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV4.scale" value="4" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV4_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV5_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_0_DIV6.scale" value="1" locked="true"/>
|
|
<setting id="MC_CGM_MUX_0_DIV6_Trigger" value="Common" locked="false"/>
|
|
<setting id="MC_CGM_MUX_6.sel" value="N/A" locked="false"/>
|
|
<setting id="MC_CGM_MUX_6_DE0" value="Enabled" locked="false"/>
|
|
<setting id="MC_CGM_MUX_6_DIV0.scale" value="2" locked="true"/>
|
|
<setting id="MODULE_CLOCKS.MC_CGM_0_AUX10_DIV0.scale" value="3" locked="true"/>
|
|
<setting id="MODULE_CLOCKS.MC_CGM_0_AUX1_DIV0.scale" value="1" locked="true"/>
|
|
<setting id="MODULE_CLOCKS.MC_CGM_0_AUX3_MUX.sel" value="MC_CGM_MUX_0_DIV1" locked="false"/>
|
|
<setting id="MODULE_CLOCKS.MC_CGM_0_AUX4_MUX.sel" value="MC_CGM_MUX_0_DIV1" locked="false"/>
|
|
<setting id="PHI0.scale" value="3" locked="true"/>
|
|
<setting id="PHI1.scale" value="3" locked="true"/>
|
|
<setting id="PLL_PREDIV.scale" value="2" locked="true"/>
|
|
<setting id="POSTDIV.scale" value="2" locked="true"/>
|
|
<setting id="SXOSC_PM" value="Crystal_mode" locked="false"/>
|
|
</clock_settings>
|
|
<called_from_default_init>true</called_from_default_init>
|
|
</clock_configuration>
|
|
</clock_configurations>
|
|
</clocks>
|
|
<ddr name="DDR" version="1.0" enabled="false" update_project_code="true">
|
|
<generated_project_files/>
|
|
<components/>
|
|
</ddr>
|
|
<dcd name="DCD" version="1.0" enabled="false" update_project_code="true" isSelfTest="false">
|
|
<generated_project_files/>
|
|
<dcdx_profile>
|
|
<processor_version>N/A</processor_version>
|
|
</dcdx_profile>
|
|
<dcdx_configurations/>
|
|
</dcd>
|
|
<ivt name="IVT" version="1.0" enabled="false" update_project_code="true">
|
|
<generated_project_files/>
|
|
<ivt_profile>
|
|
<processor_version>N/A</processor_version>
|
|
</ivt_profile>
|
|
</ivt>
|
|
<quadspi name="QuadSPI" version="1.0" enabled="false" update_project_code="true">
|
|
<generated_project_files/>
|
|
<quadspi_profile>
|
|
<processor_version>N/A</processor_version>
|
|
</quadspi_profile>
|
|
</quadspi>
|
|
<periphs name="Peripherals" version="10.0" enabled="true" update_project_code="true">
|
|
<dependencies>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="osif not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="Unsupported version of the osif in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_port" description="siul2_port not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_port" description="Unsupported version of the siul2_port in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpuart_uart" description="Lpuart_Uart not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpuart_uart" description="Unsupported version of the Lpuart_Uart in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.IntCtrl_Ip" description="IntCtrl_Ip not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.IntCtrl_Ip" description="Unsupported version of the IntCtrl_Ip in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.pit" description="Pit not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.pit" description="Unsupported version of the Pit in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.flexio_mcl" description="flexio_mcl not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.flexio_mcl" description="Unsupported version of the flexio_mcl in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_dio" description="siul2_dio not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.siul2_dio" description="Unsupported version of the siul2_dio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.adc_sar" description="adc_sar not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.adc_sar" description="Unsupported version of the adc_sar in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.FlexCAN" description="FlexCAN not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.FlexCAN" description="Unsupported version of the FlexCAN in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">0.1.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.emios_mcl" description="emios_mcl not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.emios_mcl" description="Unsupported version of the emios_mcl in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.emios_pwm" description="emios_pwm not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.emios_pwm" description="Unsupported version of the emios_pwm in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpi2c" description="Lpi2c not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpi2c" description="Unsupported version of the Lpi2c in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.os" description="Os not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.os" description="Unsupported version of the Os in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.swt_ip" description="swt_ip not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.swt_ip" description="Unsupported version of the swt_ip in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpspi" description="Lpspi not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpspi" description="Unsupported version of the Lpspi in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpuart_lin" description="Lpuart_Lin not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
|
<feature name="enabled" evaluation="equal">
|
|
<data type="Boolean">true</data>
|
|
</feature>
|
|
</dependency>
|
|
<dependency resourceType="SWComponent" resourceId="platform.driver.lpuart_lin" description="Unsupported version of the Lpuart_Lin in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
|
<feature name="version" evaluation="equivalent">
|
|
<data type="Version">1.0.0</data>
|
|
</feature>
|
|
</dependency>
|
|
</dependencies>
|
|
<generated_project_files>
|
|
<file path="generate/include/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Adc_Sar_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Adc_Sar_Ip_CfgDefines.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Mcl_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Mcl_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Mcl_Ip_Cfg_Defines.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Mcl_Ip_Cfg_DeviceRegisters.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Pwm_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Pwm_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Emios_Pwm_Ip_CfgDefines.h" update_enabled="true"/>
|
|
<file path="generate/include/FlexCAN_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/FlexCAN_Ip_Sa_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Flexio_Mcl_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Flexio_Mcl_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Flexio_Mcl_Ip_CfgDefines.h" update_enabled="true"/>
|
|
<file path="generate/include/Flexio_Mcl_Ip_Definitions.h" update_enabled="true"/>
|
|
<file path="generate/include/IntCtrl_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/IntCtrl_Ip_CfgDefines.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpi2c_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpi2c_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpspi_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpspi_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpuart_Lin_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpuart_Lin_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpuart_Uart_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpuart_Uart_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Lpuart_Uart_Ip_Defines.h" update_enabled="true"/>
|
|
<file path="generate/include/OsIf_Cfg.c" update_enabled="true"/>
|
|
<file path="generate/include/OsIf_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Os_cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Pit_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Pit_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Pit_Ip_Cfg_Defines.h" update_enabled="true"/>
|
|
<file path="generate/include/Siul2_Dio_Ip_Cfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Siul2_Port_Ip_Defines.h" update_enabled="true"/>
|
|
<file path="generate/include/Swt_Ip_BOARD_InitPeripherals_PBcfg.h" update_enabled="true"/>
|
|
<file path="generate/include/Swt_Ip_Cfg_Defines.h" update_enabled="true"/>
|
|
<file path="generate/include/modules.h" update_enabled="true"/>
|
|
<file path="generate/src/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Emios_Mcl_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Emios_Pwm_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/FlexCAN_Ip_Sa_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Flexio_Mcl_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/IntCtrl_Ip_Cfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Lpi2c_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Lpspi_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Lpuart_Lin_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Lpuart_Uart_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Pit_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
<file path="generate/src/Swt_Ip_BOARD_InitPeripherals_PBcfg.c" update_enabled="true"/>
|
|
</generated_project_files>
|
|
<peripherals_profile>
|
|
<processor_version>0.0.0</processor_version>
|
|
</peripherals_profile>
|
|
<functional_groups>
|
|
<functional_group name="BOARD_InitPeripherals" uuid="343d8c09-29ab-44df-a8a2-0e35bf16a60f" called_from_default_init="true" id_prefix="" core="core0">
|
|
<description></description>
|
|
<options/>
|
|
<dependencies/>
|
|
<instances>
|
|
<instance name="osif_1" uuid="15b290c3-be99-4491-b203-fbb4ec6a0b2d" type="osif" type_id="osif" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="osif">
|
|
<setting name="OsIfMulticoreSupport" value="false"/>
|
|
<setting name="OsIfUserModeSupport" value="false"/>
|
|
<setting name="OsIfDevErrorDetect" value="true"/>
|
|
<setting name="OsIfUseSystemTimer" value="true"/>
|
|
<setting name="OsIfUseCustomTimer" value="false"/>
|
|
<setting name="OsIfInstanceId" value="255"/>
|
|
<setting name="OsIfOperatingSystemType" value="OsIfBaremetalType"/>
|
|
<setting name="OsIfCounterFreq" value="160000000"/>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Siul2_Port_1" uuid="69597603-f2b6-45e3-8c13-a78d26f1e4f1" type="Siul2_Port" type_id="Siul2_Port" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Siul2_Port">
|
|
<struct name="PortGeneral">
|
|
<setting name="SIUL2PortIPDevErrorDetect" value="false"/>
|
|
<setting name="PortEnableUserModeSupport" value="false"/>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Lpuart_Uart_1" uuid="6da51c1b-a8f4-4635-b84c-3239d5138e87" type="Lpuart_Uart" type_id="Lpuart_Uart" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Lpuart_Uart">
|
|
<struct name="GeneralConfiguration">
|
|
<setting name="Name" value="GeneralConfiguration"/>
|
|
<setting name="UartDevErrorDetect" value="true"/>
|
|
<setting name="UartTimeoutType" value="OSIF_COUNTER_DUMMY"/>
|
|
<setting name="UartTimeoutDuration" value="0"/>
|
|
<setting name="UartDmaEnable" value="false"/>
|
|
</struct>
|
|
<struct name="UartGlobalConfig">
|
|
<setting name="Name" value="UartGlobalConfig"/>
|
|
<array name="UartChannel">
|
|
<struct name="0">
|
|
<setting name="Name" value="UartChannel_0"/>
|
|
<setting name="UartHwUsing" value="LPUART_IP"/>
|
|
<setting name="UartClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<struct name="DetailModuleConfiguration">
|
|
<setting name="Name" value="DetailModuleConfiguration"/>
|
|
<setting name="UartHwChannel" value="LPUART_0"/>
|
|
<setting name="DesireBaudrate" value="LPUART_UART_BAUDRATE_115200"/>
|
|
<setting name="UartInteruptDmaMethod" value="LPUART_UART_IP_USING_INTERRUPTS"/>
|
|
<array name="UartDmaTxChannelRef"/>
|
|
<array name="UartDmaRxChannelRef"/>
|
|
<setting name="UartParityType" value="LPUART_UART_IP_PARITY_DISABLED"/>
|
|
<setting name="UartStopBitNumber" value="LPUART_UART_IP_ONE_STOP_BIT"/>
|
|
<setting name="UartWordLength" value="LPUART_UART_IP_8_BITS_PER_CHAR"/>
|
|
<array name="UartCallbackRx">
|
|
<setting name="0" value="UART0_RX_Callback"/>
|
|
</array>
|
|
<array name="UartRxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackTx">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartTxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackError">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartErrCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
</struct>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="UartChannel_1"/>
|
|
<setting name="UartHwUsing" value="LPUART_IP"/>
|
|
<setting name="UartClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<struct name="DetailModuleConfiguration">
|
|
<setting name="Name" value="DetailModuleConfiguration"/>
|
|
<setting name="UartHwChannel" value="LPUART_2"/>
|
|
<setting name="DesireBaudrate" value="LPUART_UART_BAUDRATE_115200"/>
|
|
<setting name="UartInteruptDmaMethod" value="LPUART_UART_IP_USING_INTERRUPTS"/>
|
|
<array name="UartDmaTxChannelRef"/>
|
|
<array name="UartDmaRxChannelRef"/>
|
|
<setting name="UartParityType" value="LPUART_UART_IP_PARITY_DISABLED"/>
|
|
<setting name="UartStopBitNumber" value="LPUART_UART_IP_ONE_STOP_BIT"/>
|
|
<setting name="UartWordLength" value="LPUART_UART_IP_8_BITS_PER_CHAR"/>
|
|
<array name="UartCallbackRx">
|
|
<setting name="0" value="UART2_RX_Callback"/>
|
|
</array>
|
|
<array name="UartRxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackTx">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartTxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackError">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartErrCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
</struct>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="UartChannel_2_REAR_CON"/>
|
|
<setting name="UartHwUsing" value="LPUART_IP"/>
|
|
<setting name="UartClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<struct name="DetailModuleConfiguration">
|
|
<setting name="Name" value="DetailModuleConfiguration"/>
|
|
<setting name="UartHwChannel" value="LPUART_10"/>
|
|
<setting name="DesireBaudrate" value="LPUART_UART_BAUDRATE_115200"/>
|
|
<setting name="UartInteruptDmaMethod" value="LPUART_UART_IP_USING_INTERRUPTS"/>
|
|
<array name="UartDmaTxChannelRef"/>
|
|
<array name="UartDmaRxChannelRef"/>
|
|
<setting name="UartParityType" value="LPUART_UART_IP_PARITY_DISABLED"/>
|
|
<setting name="UartStopBitNumber" value="LPUART_UART_IP_ONE_STOP_BIT"/>
|
|
<setting name="UartWordLength" value="LPUART_UART_IP_8_BITS_PER_CHAR"/>
|
|
<array name="UartCallbackRx">
|
|
<setting name="0" value="UART10_RX_Callback"/>
|
|
</array>
|
|
<array name="UartRxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackTx">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartTxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackError">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartErrCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
</struct>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="UartChannel_3_REAR_CON"/>
|
|
<setting name="UartHwUsing" value="LPUART_IP"/>
|
|
<setting name="UartClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<struct name="DetailModuleConfiguration">
|
|
<setting name="Name" value="DetailModuleConfiguration"/>
|
|
<setting name="UartHwChannel" value="LPUART_13"/>
|
|
<setting name="DesireBaudrate" value="LPUART_UART_BAUDRATE_115200"/>
|
|
<setting name="UartInteruptDmaMethod" value="LPUART_UART_IP_USING_INTERRUPTS"/>
|
|
<array name="UartDmaTxChannelRef"/>
|
|
<array name="UartDmaRxChannelRef"/>
|
|
<setting name="UartParityType" value="LPUART_UART_IP_PARITY_DISABLED"/>
|
|
<setting name="UartStopBitNumber" value="LPUART_UART_IP_ONE_STOP_BIT"/>
|
|
<setting name="UartWordLength" value="LPUART_UART_IP_8_BITS_PER_CHAR"/>
|
|
<array name="UartCallbackRx">
|
|
<setting name="0" value="UART13_RX_Callback"/>
|
|
</array>
|
|
<array name="UartRxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackTx">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartTxCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartCallbackError">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
<array name="UartErrCallbackParam">
|
|
<setting name="0" value="NULL_PTR"/>
|
|
</array>
|
|
</struct>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="IntCtrl_Ip_1" uuid="f1143c1a-f1ee-41f8-920a-244054d9ffb0" type="IntCtrl_Ip" type_id="IntCtrl_Ip" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="IntCtrl_Ip">
|
|
<setting name="Name" value="IntCtrl_Ip"/>
|
|
<struct name="ConfigTimeSupport">
|
|
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
|
|
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VariantPreCompile"/>
|
|
</struct>
|
|
<struct name="IntCtrlConfigGeneral">
|
|
<setting name="IntCtrlDevErrorDetect" value="true"/>
|
|
<setting name="PlatformEnableUserModeSupport" value="false"/>
|
|
</struct>
|
|
<array name="IntCtrlConfig">
|
|
<struct name="0">
|
|
<setting name="Name" value="IntCtrlConfig_0"/>
|
|
<array name="PlatformIsrConfig">
|
|
<struct name="0">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="INT0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="INT1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="INT2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="INT3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="6">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="7">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="8">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="9">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="10">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD6_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="11">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD7_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="12">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD8_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="13">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD9_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="14">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD10_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="15">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD11_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="16">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD12_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="17">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD13_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="18">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD14_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="19">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD15_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="20">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD16_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="21">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD17_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="22">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD18_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="23">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD19_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="24">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD20_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="25">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD21_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="26">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD22_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="27">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD23_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="28">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD24_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="29">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD25_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="30">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD26_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="31">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD27_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="32">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD28_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="33">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD29_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="34">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD30_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="35">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="DMATCD31_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="36">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="ERM_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="37">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="ERM_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="38">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MCM_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="39">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="STM0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="40">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="STM1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="41">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SWT0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="42">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SWT1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="43">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="CTI0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="44">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="CTI1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="45">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FLASH_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="46">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FLASH_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="47">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FLASH_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="48">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="RGM_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="49">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="PMC_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="50">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SIUL_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="51">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SIUL_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="52">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SIUL_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="53">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SIUL_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="54">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="55">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="56">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="57">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="58">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="59">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS0_5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="60">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="61">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="62">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="63">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="64">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="65">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS1_5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="66">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="67">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="68">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="69">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="70">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="71">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMIOS2_5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="72">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="WKPU_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="73">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="CMU0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="74">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="CMU1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="75">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="CMU2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="76">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="BCTU_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="77">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LCU0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="78">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LCU1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="79">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="PIT0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="80">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="PIT1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="81">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="PIT2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="82">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="RTC_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="83">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMAC_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="84">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMAC_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="85">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMAC_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="86">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="EMAC_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="87">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN0_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="88">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN0_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="89">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN0_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="90">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN0_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="91">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN1_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="92">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN1_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="93">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN1_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="94">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN2_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="95">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN2_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="96">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN2_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="97">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN3_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="98">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN3_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="99">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN4_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="100">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN4_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="101">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN5_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="102">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FlexCAN5_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="1"/>
|
|
</struct>
|
|
<struct name="103">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FLEXIO_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="104">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="105">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="106">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART2_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="107">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="108">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="109">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="110">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART6_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="111">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART7_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="112">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART8_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="113">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART9_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="114">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART10_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="115">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART11_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="116">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART12_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="117">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART13_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="118">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART14_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="119">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPUART15_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="120">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPI2C0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="121">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPI2C1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="3"/>
|
|
</struct>
|
|
<struct name="122">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="123">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="124">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="125">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="126">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="127">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPSPI5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="128">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="QSPI_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="129">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SAI0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="130">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="SAI1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="131">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="JDC_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="132">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="ADC0_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="133">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="ADC1_IRQn"/>
|
|
<setting name="IsrEnabled" value="true"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="134">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="ADC2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="2"/>
|
|
</struct>
|
|
<struct name="135">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPCMP0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="136">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPCMP1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="137">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="LPCMP2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="138">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FCCU_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="139">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="FCCU_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="140">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="STCU_LBIST_MBIST_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="141">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="142">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="143">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="144">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_3_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="145">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_4_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="146">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="HSE_B_5_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="147">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_A_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="148">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_A_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="149">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_A_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="150">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_B_0_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="151">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_B_1_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
<struct name="152">
|
|
<setting name="Name" value=""/>
|
|
<setting name="IsrName" value="MU_B_2_IRQn"/>
|
|
<setting name="IsrEnabled" value="false"/>
|
|
<setting name="IsrPriority" value="0"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</array>
|
|
<struct name="MscmConfig">
|
|
<setting name="Name" value="intRouteConfig"/>
|
|
<array name="PlatformIsrConfig">
|
|
<struct name="0">
|
|
<setting name="Name" value="PlatformIsrConfig_0"/>
|
|
<setting name="IsrName" value="INT0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="PlatformIsrConfig_1"/>
|
|
<setting name="IsrName" value="INT1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="PlatformIsrConfig_2"/>
|
|
<setting name="IsrName" value="INT2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="PlatformIsrConfig_3"/>
|
|
<setting name="IsrName" value="INT3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="Name" value="PlatformIsrConfig_4"/>
|
|
<setting name="IsrName" value="DMATCD0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="Name" value="PlatformIsrConfig_5"/>
|
|
<setting name="IsrName" value="DMATCD1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="6">
|
|
<setting name="Name" value="PlatformIsrConfig_6"/>
|
|
<setting name="IsrName" value="DMATCD2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="7">
|
|
<setting name="Name" value="PlatformIsrConfig_7"/>
|
|
<setting name="IsrName" value="DMATCD3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="8">
|
|
<setting name="Name" value="PlatformIsrConfig_8"/>
|
|
<setting name="IsrName" value="DMATCD4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="9">
|
|
<setting name="Name" value="PlatformIsrConfig_9"/>
|
|
<setting name="IsrName" value="DMATCD5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="10">
|
|
<setting name="Name" value="PlatformIsrConfig_10"/>
|
|
<setting name="IsrName" value="DMATCD6_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="11">
|
|
<setting name="Name" value="PlatformIsrConfig_11"/>
|
|
<setting name="IsrName" value="DMATCD7_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="12">
|
|
<setting name="Name" value="PlatformIsrConfig_12"/>
|
|
<setting name="IsrName" value="DMATCD8_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="13">
|
|
<setting name="Name" value="PlatformIsrConfig_13"/>
|
|
<setting name="IsrName" value="DMATCD9_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="14">
|
|
<setting name="Name" value="PlatformIsrConfig_14"/>
|
|
<setting name="IsrName" value="DMATCD10_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="15">
|
|
<setting name="Name" value="PlatformIsrConfig_15"/>
|
|
<setting name="IsrName" value="DMATCD11_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="16">
|
|
<setting name="Name" value="PlatformIsrConfig_16"/>
|
|
<setting name="IsrName" value="DMATCD12_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="17">
|
|
<setting name="Name" value="PlatformIsrConfig_17"/>
|
|
<setting name="IsrName" value="DMATCD13_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="18">
|
|
<setting name="Name" value="PlatformIsrConfig_18"/>
|
|
<setting name="IsrName" value="DMATCD14_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="19">
|
|
<setting name="Name" value="PlatformIsrConfig_19"/>
|
|
<setting name="IsrName" value="DMATCD15_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="20">
|
|
<setting name="Name" value="PlatformIsrConfig_20"/>
|
|
<setting name="IsrName" value="DMATCD16_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="21">
|
|
<setting name="Name" value="PlatformIsrConfig_21"/>
|
|
<setting name="IsrName" value="DMATCD17_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="22">
|
|
<setting name="Name" value="PlatformIsrConfig_22"/>
|
|
<setting name="IsrName" value="DMATCD18_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="23">
|
|
<setting name="Name" value="PlatformIsrConfig_23"/>
|
|
<setting name="IsrName" value="DMATCD19_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="24">
|
|
<setting name="Name" value="PlatformIsrConfig_24"/>
|
|
<setting name="IsrName" value="DMATCD20_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="25">
|
|
<setting name="Name" value="PlatformIsrConfig_25"/>
|
|
<setting name="IsrName" value="DMATCD21_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="26">
|
|
<setting name="Name" value="PlatformIsrConfig_26"/>
|
|
<setting name="IsrName" value="DMATCD22_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="27">
|
|
<setting name="Name" value="PlatformIsrConfig_27"/>
|
|
<setting name="IsrName" value="DMATCD23_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="28">
|
|
<setting name="Name" value="PlatformIsrConfig_28"/>
|
|
<setting name="IsrName" value="DMATCD24_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="29">
|
|
<setting name="Name" value="PlatformIsrConfig_29"/>
|
|
<setting name="IsrName" value="DMATCD25_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="30">
|
|
<setting name="Name" value="PlatformIsrConfig_30"/>
|
|
<setting name="IsrName" value="DMATCD26_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="31">
|
|
<setting name="Name" value="PlatformIsrConfig_31"/>
|
|
<setting name="IsrName" value="DMATCD27_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="32">
|
|
<setting name="Name" value="PlatformIsrConfig_32"/>
|
|
<setting name="IsrName" value="DMATCD28_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="33">
|
|
<setting name="Name" value="PlatformIsrConfig_33"/>
|
|
<setting name="IsrName" value="DMATCD29_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="34">
|
|
<setting name="Name" value="PlatformIsrConfig_34"/>
|
|
<setting name="IsrName" value="DMATCD30_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="35">
|
|
<setting name="Name" value="PlatformIsrConfig_35"/>
|
|
<setting name="IsrName" value="DMATCD31_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="36">
|
|
<setting name="Name" value="PlatformIsrConfig_36"/>
|
|
<setting name="IsrName" value="ERM_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="37">
|
|
<setting name="Name" value="PlatformIsrConfig_37"/>
|
|
<setting name="IsrName" value="ERM_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="38">
|
|
<setting name="Name" value="PlatformIsrConfig_38"/>
|
|
<setting name="IsrName" value="MCM_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="39">
|
|
<setting name="Name" value="PlatformIsrConfig_39"/>
|
|
<setting name="IsrName" value="STM0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="40">
|
|
<setting name="Name" value="PlatformIsrConfig_40"/>
|
|
<setting name="IsrName" value="STM1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="41">
|
|
<setting name="Name" value="PlatformIsrConfig_41"/>
|
|
<setting name="IsrName" value="SWT0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="42">
|
|
<setting name="Name" value="PlatformIsrConfig_42"/>
|
|
<setting name="IsrName" value="SWT1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="43">
|
|
<setting name="Name" value="PlatformIsrConfig_43"/>
|
|
<setting name="IsrName" value="CTI0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="44">
|
|
<setting name="Name" value="PlatformIsrConfig_44"/>
|
|
<setting name="IsrName" value="CTI1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="45">
|
|
<setting name="Name" value="PlatformIsrConfig_45"/>
|
|
<setting name="IsrName" value="FLASH_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="46">
|
|
<setting name="Name" value="PlatformIsrConfig_46"/>
|
|
<setting name="IsrName" value="FLASH_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="47">
|
|
<setting name="Name" value="PlatformIsrConfig_47"/>
|
|
<setting name="IsrName" value="FLASH_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="48">
|
|
<setting name="Name" value="PlatformIsrConfig_48"/>
|
|
<setting name="IsrName" value="RGM_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="49">
|
|
<setting name="Name" value="PlatformIsrConfig_49"/>
|
|
<setting name="IsrName" value="PMC_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="50">
|
|
<setting name="Name" value="PlatformIsrConfig_50"/>
|
|
<setting name="IsrName" value="SIUL_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="51">
|
|
<setting name="Name" value="PlatformIsrConfig_51"/>
|
|
<setting name="IsrName" value="SIUL_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="52">
|
|
<setting name="Name" value="PlatformIsrConfig_52"/>
|
|
<setting name="IsrName" value="SIUL_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="53">
|
|
<setting name="Name" value="PlatformIsrConfig_53"/>
|
|
<setting name="IsrName" value="SIUL_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="54">
|
|
<setting name="Name" value="PlatformIsrConfig_54"/>
|
|
<setting name="IsrName" value="EMIOS0_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="55">
|
|
<setting name="Name" value="PlatformIsrConfig_55"/>
|
|
<setting name="IsrName" value="EMIOS0_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="56">
|
|
<setting name="Name" value="PlatformIsrConfig_56"/>
|
|
<setting name="IsrName" value="EMIOS0_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="57">
|
|
<setting name="Name" value="PlatformIsrConfig_57"/>
|
|
<setting name="IsrName" value="EMIOS0_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="58">
|
|
<setting name="Name" value="PlatformIsrConfig_58"/>
|
|
<setting name="IsrName" value="EMIOS0_4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="59">
|
|
<setting name="Name" value="PlatformIsrConfig_59"/>
|
|
<setting name="IsrName" value="EMIOS0_5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="60">
|
|
<setting name="Name" value="PlatformIsrConfig_60"/>
|
|
<setting name="IsrName" value="EMIOS1_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="61">
|
|
<setting name="Name" value="PlatformIsrConfig_61"/>
|
|
<setting name="IsrName" value="EMIOS1_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="62">
|
|
<setting name="Name" value="PlatformIsrConfig_62"/>
|
|
<setting name="IsrName" value="EMIOS1_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="63">
|
|
<setting name="Name" value="PlatformIsrConfig_63"/>
|
|
<setting name="IsrName" value="EMIOS1_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="64">
|
|
<setting name="Name" value="PlatformIsrConfig_64"/>
|
|
<setting name="IsrName" value="EMIOS1_4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="65">
|
|
<setting name="Name" value="PlatformIsrConfig_65"/>
|
|
<setting name="IsrName" value="EMIOS1_5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="66">
|
|
<setting name="Name" value="PlatformIsrConfig_66"/>
|
|
<setting name="IsrName" value="EMIOS2_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="67">
|
|
<setting name="Name" value="PlatformIsrConfig_67"/>
|
|
<setting name="IsrName" value="EMIOS2_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="68">
|
|
<setting name="Name" value="PlatformIsrConfig_68"/>
|
|
<setting name="IsrName" value="EMIOS2_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="69">
|
|
<setting name="Name" value="PlatformIsrConfig_69"/>
|
|
<setting name="IsrName" value="EMIOS2_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="70">
|
|
<setting name="Name" value="PlatformIsrConfig_70"/>
|
|
<setting name="IsrName" value="EMIOS2_4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="71">
|
|
<setting name="Name" value="PlatformIsrConfig_71"/>
|
|
<setting name="IsrName" value="EMIOS2_5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="72">
|
|
<setting name="Name" value="PlatformIsrConfig_72"/>
|
|
<setting name="IsrName" value="WKPU_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="73">
|
|
<setting name="Name" value="PlatformIsrConfig_73"/>
|
|
<setting name="IsrName" value="CMU0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="74">
|
|
<setting name="Name" value="PlatformIsrConfig_74"/>
|
|
<setting name="IsrName" value="CMU1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="75">
|
|
<setting name="Name" value="PlatformIsrConfig_75"/>
|
|
<setting name="IsrName" value="CMU2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="76">
|
|
<setting name="Name" value="PlatformIsrConfig_76"/>
|
|
<setting name="IsrName" value="BCTU_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="77">
|
|
<setting name="Name" value="PlatformIsrConfig_77"/>
|
|
<setting name="IsrName" value="LCU0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="78">
|
|
<setting name="Name" value="PlatformIsrConfig_78"/>
|
|
<setting name="IsrName" value="LCU1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="79">
|
|
<setting name="Name" value="PlatformIsrConfig_79"/>
|
|
<setting name="IsrName" value="PIT0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="PIT_0_ISR"/>
|
|
</struct>
|
|
<struct name="80">
|
|
<setting name="Name" value="PlatformIsrConfig_80"/>
|
|
<setting name="IsrName" value="PIT1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="81">
|
|
<setting name="Name" value="PlatformIsrConfig_81"/>
|
|
<setting name="IsrName" value="PIT2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="82">
|
|
<setting name="Name" value="PlatformIsrConfig_82"/>
|
|
<setting name="IsrName" value="RTC_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="83">
|
|
<setting name="Name" value="PlatformIsrConfig_83"/>
|
|
<setting name="IsrName" value="EMAC_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="84">
|
|
<setting name="Name" value="PlatformIsrConfig_84"/>
|
|
<setting name="IsrName" value="EMAC_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="85">
|
|
<setting name="Name" value="PlatformIsrConfig_85"/>
|
|
<setting name="IsrName" value="EMAC_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="86">
|
|
<setting name="Name" value="PlatformIsrConfig_86"/>
|
|
<setting name="IsrName" value="EMAC_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="87">
|
|
<setting name="Name" value="PlatformIsrConfig_87"/>
|
|
<setting name="IsrName" value="FlexCAN0_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="88">
|
|
<setting name="Name" value="PlatformIsrConfig_88"/>
|
|
<setting name="IsrName" value="FlexCAN0_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="89">
|
|
<setting name="Name" value="PlatformIsrConfig_89"/>
|
|
<setting name="IsrName" value="FlexCAN0_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="90">
|
|
<setting name="Name" value="PlatformIsrConfig_90"/>
|
|
<setting name="IsrName" value="FlexCAN0_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="91">
|
|
<setting name="Name" value="PlatformIsrConfig_91"/>
|
|
<setting name="IsrName" value="FlexCAN1_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="92">
|
|
<setting name="Name" value="PlatformIsrConfig_92"/>
|
|
<setting name="IsrName" value="FlexCAN1_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="93">
|
|
<setting name="Name" value="PlatformIsrConfig_93"/>
|
|
<setting name="IsrName" value="FlexCAN1_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="94">
|
|
<setting name="Name" value="PlatformIsrConfig_94"/>
|
|
<setting name="IsrName" value="FlexCAN2_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="95">
|
|
<setting name="Name" value="PlatformIsrConfig_95"/>
|
|
<setting name="IsrName" value="FlexCAN2_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="96">
|
|
<setting name="Name" value="PlatformIsrConfig_96"/>
|
|
<setting name="IsrName" value="FlexCAN2_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="97">
|
|
<setting name="Name" value="PlatformIsrConfig_97"/>
|
|
<setting name="IsrName" value="FlexCAN3_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="98">
|
|
<setting name="Name" value="PlatformIsrConfig_98"/>
|
|
<setting name="IsrName" value="FlexCAN3_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="99">
|
|
<setting name="Name" value="PlatformIsrConfig_99"/>
|
|
<setting name="IsrName" value="FlexCAN4_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="100">
|
|
<setting name="Name" value="PlatformIsrConfig_100"/>
|
|
<setting name="IsrName" value="FlexCAN4_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="101">
|
|
<setting name="Name" value="PlatformIsrConfig_101"/>
|
|
<setting name="IsrName" value="FlexCAN5_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="102">
|
|
<setting name="Name" value="PlatformIsrConfig_102"/>
|
|
<setting name="IsrName" value="FlexCAN5_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="103">
|
|
<setting name="Name" value="PlatformIsrConfig_103"/>
|
|
<setting name="IsrName" value="FLEXIO_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="104">
|
|
<setting name="Name" value="PlatformIsrConfig_104"/>
|
|
<setting name="IsrName" value="LPUART0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="105">
|
|
<setting name="Name" value="PlatformIsrConfig_105"/>
|
|
<setting name="IsrName" value="LPUART1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="106">
|
|
<setting name="Name" value="PlatformIsrConfig_106"/>
|
|
<setting name="IsrName" value="LPUART2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="107">
|
|
<setting name="Name" value="PlatformIsrConfig_107"/>
|
|
<setting name="IsrName" value="LPUART3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="108">
|
|
<setting name="Name" value="PlatformIsrConfig_108"/>
|
|
<setting name="IsrName" value="LPUART4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="109">
|
|
<setting name="Name" value="PlatformIsrConfig_109"/>
|
|
<setting name="IsrName" value="LPUART5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="110">
|
|
<setting name="Name" value="PlatformIsrConfig_110"/>
|
|
<setting name="IsrName" value="LPUART6_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="111">
|
|
<setting name="Name" value="PlatformIsrConfig_111"/>
|
|
<setting name="IsrName" value="LPUART7_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="112">
|
|
<setting name="Name" value="PlatformIsrConfig_112"/>
|
|
<setting name="IsrName" value="LPUART8_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="113">
|
|
<setting name="Name" value="PlatformIsrConfig_113"/>
|
|
<setting name="IsrName" value="LPUART9_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="114">
|
|
<setting name="Name" value="PlatformIsrConfig_114"/>
|
|
<setting name="IsrName" value="LPUART10_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="115">
|
|
<setting name="Name" value="PlatformIsrConfig_115"/>
|
|
<setting name="IsrName" value="LPUART11_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="116">
|
|
<setting name="Name" value="PlatformIsrConfig_116"/>
|
|
<setting name="IsrName" value="LPUART12_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="117">
|
|
<setting name="Name" value="PlatformIsrConfig_117"/>
|
|
<setting name="IsrName" value="LPUART13_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="118">
|
|
<setting name="Name" value="PlatformIsrConfig_118"/>
|
|
<setting name="IsrName" value="LPUART14_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="119">
|
|
<setting name="Name" value="PlatformIsrConfig_119"/>
|
|
<setting name="IsrName" value="LPUART15_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="120">
|
|
<setting name="Name" value="PlatformIsrConfig_120"/>
|
|
<setting name="IsrName" value="LPI2C0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="121">
|
|
<setting name="Name" value="PlatformIsrConfig_121"/>
|
|
<setting name="IsrName" value="LPI2C1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="122">
|
|
<setting name="Name" value="PlatformIsrConfig_122"/>
|
|
<setting name="IsrName" value="LPSPI0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="123">
|
|
<setting name="Name" value="PlatformIsrConfig_123"/>
|
|
<setting name="IsrName" value="LPSPI1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="124">
|
|
<setting name="Name" value="PlatformIsrConfig_124"/>
|
|
<setting name="IsrName" value="LPSPI2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="125">
|
|
<setting name="Name" value="PlatformIsrConfig_125"/>
|
|
<setting name="IsrName" value="LPSPI3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="126">
|
|
<setting name="Name" value="PlatformIsrConfig_126"/>
|
|
<setting name="IsrName" value="LPSPI4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="127">
|
|
<setting name="Name" value="PlatformIsrConfig_127"/>
|
|
<setting name="IsrName" value="LPSPI5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="128">
|
|
<setting name="Name" value="PlatformIsrConfig_128"/>
|
|
<setting name="IsrName" value="QSPI_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="129">
|
|
<setting name="Name" value="PlatformIsrConfig_129"/>
|
|
<setting name="IsrName" value="SAI0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="130">
|
|
<setting name="Name" value="PlatformIsrConfig_130"/>
|
|
<setting name="IsrName" value="SAI1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="131">
|
|
<setting name="Name" value="PlatformIsrConfig_131"/>
|
|
<setting name="IsrName" value="JDC_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="132">
|
|
<setting name="Name" value="PlatformIsrConfig_132"/>
|
|
<setting name="IsrName" value="ADC0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="133">
|
|
<setting name="Name" value="PlatformIsrConfig_133"/>
|
|
<setting name="IsrName" value="ADC1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="134">
|
|
<setting name="Name" value="PlatformIsrConfig_134"/>
|
|
<setting name="IsrName" value="ADC2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="135">
|
|
<setting name="Name" value="PlatformIsrConfig_135"/>
|
|
<setting name="IsrName" value="LPCMP0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="136">
|
|
<setting name="Name" value="PlatformIsrConfig_136"/>
|
|
<setting name="IsrName" value="LPCMP1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="137">
|
|
<setting name="Name" value="PlatformIsrConfig_137"/>
|
|
<setting name="IsrName" value="LPCMP2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="138">
|
|
<setting name="Name" value="PlatformIsrConfig_138"/>
|
|
<setting name="IsrName" value="FCCU_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="139">
|
|
<setting name="Name" value="PlatformIsrConfig_139"/>
|
|
<setting name="IsrName" value="FCCU_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="140">
|
|
<setting name="Name" value="PlatformIsrConfig_140"/>
|
|
<setting name="IsrName" value="STCU_LBIST_MBIST_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="141">
|
|
<setting name="Name" value="PlatformIsrConfig_141"/>
|
|
<setting name="IsrName" value="HSE_B_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="142">
|
|
<setting name="Name" value="PlatformIsrConfig_142"/>
|
|
<setting name="IsrName" value="HSE_B_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="143">
|
|
<setting name="Name" value="PlatformIsrConfig_143"/>
|
|
<setting name="IsrName" value="HSE_B_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="144">
|
|
<setting name="Name" value="PlatformIsrConfig_144"/>
|
|
<setting name="IsrName" value="HSE_B_3_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="145">
|
|
<setting name="Name" value="PlatformIsrConfig_145"/>
|
|
<setting name="IsrName" value="HSE_B_4_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="146">
|
|
<setting name="Name" value="PlatformIsrConfig_146"/>
|
|
<setting name="IsrName" value="HSE_B_5_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="147">
|
|
<setting name="Name" value="PlatformIsrConfig_147"/>
|
|
<setting name="IsrName" value="MU_A_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="148">
|
|
<setting name="Name" value="PlatformIsrConfig_148"/>
|
|
<setting name="IsrName" value="MU_A_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="149">
|
|
<setting name="Name" value="PlatformIsrConfig_149"/>
|
|
<setting name="IsrName" value="MU_A_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="150">
|
|
<setting name="Name" value="PlatformIsrConfig_150"/>
|
|
<setting name="IsrName" value="MU_B_0_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="151">
|
|
<setting name="Name" value="PlatformIsrConfig_151"/>
|
|
<setting name="IsrName" value="MU_B_1_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
<struct name="152">
|
|
<setting name="Name" value="PlatformIsrConfig_152"/>
|
|
<setting name="IsrName" value="MU_B_2_IRQn"/>
|
|
<setting name="IsrTargetCore0" value="true"/>
|
|
<setting name="IsrTargetCore1" value="true"/>
|
|
<setting name="IsrHandler" value="undefined_handler"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Pit_1" uuid="afa6d481-dbe2-4efd-9ff6-e82bab3b3780" type="Pit" type_id="Pit" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Pit">
|
|
<struct name="GptChannelConfigSet">
|
|
<array name="GptPit">
|
|
<struct name="0">
|
|
<setting name="Name" value="Pit_0"/>
|
|
<setting name="GptPitModule" value="PIT_0"/>
|
|
<setting name="PitFreezeEnable" value="false"/>
|
|
<array name="GptPitChannels">
|
|
<struct name="0">
|
|
<setting name="Name" value="PitChannel_0"/>
|
|
<setting name="GptPitChannel" value="CH_0"/>
|
|
<setting name="ChainMode" value="false"/>
|
|
<setting name="PitNotification" value="Pit_Callback"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<array name="GptHwConfiguration">
|
|
<struct name="0">
|
|
<setting name="Name" value="GptHwConfiguration_0"/>
|
|
<setting name="GptIsrHwId" value="PIT_0_CH_RTI"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="GptHwConfiguration_1"/>
|
|
<setting name="GptIsrHwId" value="PIT_0_CH_0"/>
|
|
<setting name="GptIsrEnable" value="true"/>
|
|
<setting name="GptChannelIsUsed" value="true"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="GptHwConfiguration_2"/>
|
|
<setting name="GptIsrHwId" value="PIT_0_CH_1"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="GptHwConfiguration_3"/>
|
|
<setting name="GptIsrHwId" value="PIT_0_CH_2"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="Name" value="GptHwConfiguration_4"/>
|
|
<setting name="GptIsrHwId" value="PIT_0_CH_3"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="Name" value="GptHwConfiguration_5"/>
|
|
<setting name="GptIsrHwId" value="PIT_1_CH_0"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="6">
|
|
<setting name="Name" value="GptHwConfiguration_6"/>
|
|
<setting name="GptIsrHwId" value="PIT_1_CH_1"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="7">
|
|
<setting name="Name" value="GptHwConfiguration_7"/>
|
|
<setting name="GptIsrHwId" value="PIT_1_CH_2"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="8">
|
|
<setting name="Name" value="GptHwConfiguration_8"/>
|
|
<setting name="GptIsrHwId" value="PIT_1_CH_3"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="9">
|
|
<setting name="Name" value="GptHwConfiguration_9"/>
|
|
<setting name="GptIsrHwId" value="PIT_2_CH_0"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="10">
|
|
<setting name="Name" value="GptHwConfiguration_10"/>
|
|
<setting name="GptIsrHwId" value="PIT_2_CH_1"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="11">
|
|
<setting name="Name" value="GptHwConfiguration_11"/>
|
|
<setting name="GptIsrHwId" value="PIT_2_CH_2"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
<struct name="12">
|
|
<setting name="Name" value="GptHwConfiguration_12"/>
|
|
<setting name="GptIsrHwId" value="PIT_2_CH_3"/>
|
|
<setting name="GptIsrEnable" value="false"/>
|
|
<setting name="GptChannelIsUsed" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<struct name="GptAutosarExt">
|
|
<setting name="Name" value="GptAutosarExt"/>
|
|
<setting name="GptEnableDualClockMode" value="false"/>
|
|
<setting name="GptChangeNextTimeoutValueApi" value="false"/>
|
|
<setting name="GptEnableUserModeSupport" value="false"/>
|
|
<setting name="ChainModeApi" value="false"/>
|
|
<setting name="GptStandbyWakeupSupport" value="false"/>
|
|
</struct>
|
|
<struct name="GptDriverConfiguration">
|
|
<setting name="Name" value="GptDriverConfiguration"/>
|
|
<setting name="GptDevErrorDetect" value="false"/>
|
|
<setting name="GptTimeoutMethod" value="OSIF_COUNTER_SYSTEM"/>
|
|
<setting name="GptTimeoutDuration" value="100"/>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Flexio_Mcl_Ip_1" uuid="e258a888-accf-4d15-b7a4-810c1b620d18" type="Flexio_Mcl_Ip" type_id="Flexio_Mcl_Ip" mode="flexio_mcl" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="flexio_mcl_ip">
|
|
<setting name="Name" value="FlexioMcl"/>
|
|
<struct name="MclGeneral">
|
|
<setting name="Name" value="MclGeneral"/>
|
|
<setting name="MclEnableUserModeSupport" value="false"/>
|
|
<struct name="MclFlexioCommon">
|
|
<setting name="Name" value="MclFlexioCommon"/>
|
|
<setting name="MclEnableFlexioCommon" value="true"/>
|
|
<setting name="MclEnableFlexioDevErrorDetect" value="true"/>
|
|
</struct>
|
|
</struct>
|
|
<struct name="MclConfig">
|
|
<setting name="Name" value="MclConfig"/>
|
|
<array name="FlexioCommon">
|
|
<struct name="0">
|
|
<setting name="Name" value="FlexioCommon_0"/>
|
|
<setting name="FlexioMclInstances" value="FLEXIO_0"/>
|
|
<setting name="FlexioDebugEnable" value="true"/>
|
|
<array name="FlexioMclLogicChannels">
|
|
<struct name="0">
|
|
<setting name="Name" value="FlexioMclLogicChannels_0"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_0"/>
|
|
<setting name="FlexioMclPinId" value="PIN_16"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="FlexioMclLogicChannels_1"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_1"/>
|
|
<setting name="FlexioMclPinId" value="PIN_19"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="FlexioMclLogicChannels_2"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_2"/>
|
|
<setting name="FlexioMclPinId" value="PIN_18"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="FlexioMclLogicChannels_3"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_3"/>
|
|
<setting name="FlexioMclPinId" value="PIN_3"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="Name" value="FlexioMclLogicChannels_4"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_4"/>
|
|
<setting name="FlexioMclPinId" value="PIN_25"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="Name" value="FlexioMclLogicChannels_5"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_5"/>
|
|
<setting name="FlexioMclPinId" value="PIN_27"/>
|
|
</struct>
|
|
<struct name="6">
|
|
<setting name="Name" value="FlexioMclLogicChannels_6"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_6"/>
|
|
<setting name="FlexioMclPinId" value="PIN_7"/>
|
|
</struct>
|
|
<struct name="7">
|
|
<setting name="Name" value="FlexioMclLogicChannels_7"/>
|
|
<setting name="FlexioMclChannelId" value="CHANNEL_7"/>
|
|
<setting name="FlexioMclPinId" value="PIN_5"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Siul2_Dio_1" uuid="f5496687-dec6-46f1-aa12-8212c53bf686" type="Siul2_Dio" type_id="Siul2_Dio" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Siul2_Dio">
|
|
<struct name="DioGeneral">
|
|
<setting name="SIUL2DioIPDevErrorDetect" value="false"/>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Adc_Sar_Ip_1" uuid="8cf90485-d643-4984-bca8-099391676390" type="Adc_Sar_Ip" type_id="Adc_Sar_Ip" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Adc_Sar_Ip">
|
|
<setting name="Name" value="Adc Sar Ip"/>
|
|
<setting name="AdcSarDevErrorDetect" value="false"/>
|
|
<setting name="AdcSarTimeoutType" value="OSIF_COUNTER_DUMMY"/>
|
|
<setting name="AdcSarTimeoutVal" value="3000"/>
|
|
<setting name="AdcSarEnableUserModeSupport" value="false"/>
|
|
<setting name="AdcSarEnableWatchdogApi" value="false"/>
|
|
<setting name="AdcSarEnableEoC" value="false"/>
|
|
<setting name="AdcSarEnableTempsenseApi" value="false"/>
|
|
<setting name="AdcSarTempSenseVsupply" value="53"/>
|
|
<array name="AdcHwUnitArray">
|
|
<struct name="0">
|
|
<setting name="Name" value="AdcHwUnit_0"/>
|
|
<setting name="AdcHwUnitId" value="0"/>
|
|
<setting name="AdcTransferType" value="ADC_INTERRUPT"/>
|
|
<setting name="AdcHwUnitConvMode" value="ADC_SAR_IP_CONV_MODE_ONESHOT"/>
|
|
<setting name="AdcHwUnitClkSelect" value="ADC_SAR_IP_CLK_QUARTER_BUS"/>
|
|
<setting name="AdcHwUnitCalibrationClkSelect" value="ADC_SAR_IP_CLK_FULL_BUS"/>
|
|
<setting name="AdcHwUnitPowerDownDelay" value="0"/>
|
|
<setting name="AdcHwUnitDecodeDelay" value="0"/>
|
|
<setting name="AdcHwUnitAutoClkOff" value="false"/>
|
|
<setting name="AdcHwUnitBypassSampling" value="false"/>
|
|
<setting name="AdcHwUnitOverwriteEn" value="true"/>
|
|
<setting name="AdcHwUnitPresampleSource0" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource1" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource2" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitCtuMode" value="ADC_SAR_IP_CTU_MODE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtInjTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtNrmTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitPrimaryExtNrmTrg" value="true"/>
|
|
<setting name="AdcHwUnitAuxiliaryExtNrmTrg" value="false"/>
|
|
<setting name="AdcHwUnitUsrOffset" value="0"/>
|
|
<setting name="AdcHwUnitUsrGain" value="0"/>
|
|
<setting name="AdcHwUnitResolution" value="12"/>
|
|
<setting name="AdcHwUnitDmaClearSource" value="ADC_SAR_IP_DMA_REQ_CLEAR_ON_ACK"/>
|
|
<setting name="AdcHwUnitNotifChainN" value="Adc0EndOfChainNoti"/>
|
|
<setting name="AdcHwUnitNotifChainJ" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifCtu" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifEOC" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifWdg" value="NULL_PTR"/>
|
|
<setting name="AdcSarHwUnitVref" value="53"/>
|
|
<setting name="AdcHwUnitSampleTime0" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime1" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime2" value="255"/>
|
|
<setting name="AdcHwUnitDataAlign" value="ADC_SAR_IP_DATA_ALIGNED_RIGHT"/>
|
|
<array name="AdcHwUnitChnIdxArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_6"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitChnCfgArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_6"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitWdgThrArray"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="AdcHwUnit_1"/>
|
|
<setting name="AdcHwUnitId" value="1"/>
|
|
<setting name="AdcTransferType" value="ADC_INTERRUPT"/>
|
|
<setting name="AdcHwUnitConvMode" value="ADC_SAR_IP_CONV_MODE_ONESHOT"/>
|
|
<setting name="AdcHwUnitClkSelect" value="ADC_SAR_IP_CLK_QUARTER_BUS"/>
|
|
<setting name="AdcHwUnitCalibrationClkSelect" value="ADC_SAR_IP_CLK_FULL_BUS"/>
|
|
<setting name="AdcHwUnitPowerDownDelay" value="0"/>
|
|
<setting name="AdcHwUnitDecodeDelay" value="0"/>
|
|
<setting name="AdcHwUnitAutoClkOff" value="false"/>
|
|
<setting name="AdcHwUnitBypassSampling" value="false"/>
|
|
<setting name="AdcHwUnitOverwriteEn" value="true"/>
|
|
<setting name="AdcHwUnitPresampleSource0" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource1" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource2" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitCtuMode" value="ADC_SAR_IP_CTU_MODE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtInjTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtNrmTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitPrimaryExtNrmTrg" value="true"/>
|
|
<setting name="AdcHwUnitAuxiliaryExtNrmTrg" value="false"/>
|
|
<setting name="AdcHwUnitUsrOffset" value="0"/>
|
|
<setting name="AdcHwUnitUsrGain" value="0"/>
|
|
<setting name="AdcHwUnitResolution" value="12"/>
|
|
<setting name="AdcHwUnitDmaClearSource" value="ADC_SAR_IP_DMA_REQ_CLEAR_ON_ACK"/>
|
|
<setting name="AdcHwUnitNotifChainN" value="Adc1EndOfChainNoti"/>
|
|
<setting name="AdcHwUnitNotifChainJ" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifCtu" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifEOC" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifWdg" value="NULL_PTR"/>
|
|
<setting name="AdcSarHwUnitVref" value="53"/>
|
|
<setting name="AdcHwUnitSampleTime0" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime1" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime2" value="255"/>
|
|
<setting name="AdcHwUnitDataAlign" value="ADC_SAR_IP_DATA_ALIGNED_RIGHT"/>
|
|
<array name="AdcHwUnitChnIdxArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_43"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="ChnIdx" value="AN_2"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitChnCfgArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_43"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="ChnIdx" value="AN_2"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitWdgThrArray"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="AdcHwUnit_2"/>
|
|
<setting name="AdcHwUnitId" value="2"/>
|
|
<setting name="AdcTransferType" value="ADC_INTERRUPT"/>
|
|
<setting name="AdcHwUnitConvMode" value="ADC_SAR_IP_CONV_MODE_ONESHOT"/>
|
|
<setting name="AdcHwUnitClkSelect" value="ADC_SAR_IP_CLK_QUARTER_BUS"/>
|
|
<setting name="AdcHwUnitCalibrationClkSelect" value="ADC_SAR_IP_CLK_FULL_BUS"/>
|
|
<setting name="AdcHwUnitPowerDownDelay" value="0"/>
|
|
<setting name="AdcHwUnitDecodeDelay" value="0"/>
|
|
<setting name="AdcHwUnitAutoClkOff" value="false"/>
|
|
<setting name="AdcHwUnitBypassSampling" value="false"/>
|
|
<setting name="AdcHwUnitOverwriteEn" value="true"/>
|
|
<setting name="AdcHwUnitPresampleSource0" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource1" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitPresampleSource2" value="ADC_SAR_IP_PRESAMPLE_VREFL"/>
|
|
<setting name="AdcHwUnitCtuMode" value="ADC_SAR_IP_CTU_MODE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtInjTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitExtNrmTrg" value="ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED"/>
|
|
<setting name="AdcHwUnitPrimaryExtNrmTrg" value="true"/>
|
|
<setting name="AdcHwUnitAuxiliaryExtNrmTrg" value="false"/>
|
|
<setting name="AdcHwUnitUsrOffset" value="0"/>
|
|
<setting name="AdcHwUnitUsrGain" value="0"/>
|
|
<setting name="AdcHwUnitResolution" value="12"/>
|
|
<setting name="AdcHwUnitDmaClearSource" value="ADC_SAR_IP_DMA_REQ_CLEAR_ON_ACK"/>
|
|
<setting name="AdcHwUnitNotifChainN" value="Adc2EndOfChainNoti"/>
|
|
<setting name="AdcHwUnitNotifChainJ" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifCtu" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifEOC" value="NULL_PTR"/>
|
|
<setting name="AdcHwUnitNotifWdg" value="NULL_PTR"/>
|
|
<setting name="AdcSarHwUnitVref" value="53"/>
|
|
<setting name="AdcHwUnitSampleTime0" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime1" value="255"/>
|
|
<setting name="AdcHwUnitSampleTime2" value="255"/>
|
|
<setting name="AdcHwUnitDataAlign" value="ADC_SAR_IP_DATA_ALIGNED_RIGHT"/>
|
|
<array name="AdcHwUnitChnIdxArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_3"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="ChnIdx" value="AN_4"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="ChnIdx" value="AN_5"/>
|
|
<setting name="NormalChnEn" value="true"/>
|
|
<setting name="InjectedChnEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitChnCfgArray">
|
|
<struct name="0">
|
|
<setting name="ChnIdx" value="AN_3"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="ChnIdx" value="AN_4"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="ChnIdx" value="AN_5"/>
|
|
<setting name="PresampleEn" value="false"/>
|
|
<setting name="ThrEn" value="false"/>
|
|
<setting name="WdgRegIdx" value=""/>
|
|
<setting name="EOCEn" value="true"/>
|
|
<setting name="WdgEn" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<array name="AdcHwUnitWdgThrArray"/>
|
|
</struct>
|
|
</array>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="FlexCAN_43_1" uuid="28f7968e-c56c-4477-81af-64151bdf2a27" type="FlexCAN_43" type_id="FlexCAN" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="FlexCAN">
|
|
<array name="FlexCAN_Configurations">
|
|
<struct name="0">
|
|
<setting name="CanHwChannel" value="FLEXCAN_0"/>
|
|
<setting name="Name" value="FlexCAN_Config0"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_32"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN0_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN0_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="2"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="1"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="true"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="CanHwChannel" value="FLEXCAN_1"/>
|
|
<setting name="Name" value="FlexCAN_Config1"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_32"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN1_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN1_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="0"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="0"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="false"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="CanHwChannel" value="FLEXCAN_2"/>
|
|
<setting name="Name" value="FlexCAN_Config2"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_8"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="1"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN2_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN2_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="0"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="0"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="false"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="CanHwChannel" value="FLEXCAN_3"/>
|
|
<setting name="Name" value="FlexCAN_Config3"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_8"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="1"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN3_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN3_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="0"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="0"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="false"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="CanHwChannel" value="FLEXCAN_4"/>
|
|
<setting name="Name" value="FlexCAN_Config4"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_8"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="1"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN4_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN4_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="0"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="0"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="false"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="CanHwChannel" value="FLEXCAN_5"/>
|
|
<setting name="Name" value="FlexCAN_Config5"/>
|
|
<setting name="max_num_mb" value="24"/>
|
|
<setting name="num_id_filters" value="FLEXCAN_RX_FIFO_ID_FILTERS_8"/>
|
|
<setting name="is_rx_fifo_needed" value="false"/>
|
|
<setting name="fd_enable" value="true"/>
|
|
<setting name="flexcanMode" value="FLEXCAN_NORMAL_MODE"/>
|
|
<setting name="payload" value="FLEXCAN_PAYLOAD_SIZE_8"/>
|
|
<setting name="transfer_type" value="FLEXCAN_RXFIFO_USING_INTERRUPTS"/>
|
|
<setting name="rxFifoDMAChannel" value="0"/>
|
|
<setting name="extCbtEnable" value="true"/>
|
|
<setting name="bitRateSwitch" value="true"/>
|
|
<setting name="CanControllerFdISO" value="true"/>
|
|
<setting name="CanControllerAutoBusOff" value="true"/>
|
|
<setting name="timeStampSurce" value="FLEXCAN_CAN_CLK_TIMESTAMP_SRC"/>
|
|
<setting name="msgBuffTimeStampType" value="FLEXCAN_MSGBUFFTIMESTAMP_TIMER"/>
|
|
<setting name="hrConfigType" value="FLEXCAN_TIMESTAMPCAPTURE_DISABLE"/>
|
|
<setting name="pe_clock_frequency" value="80000000"/>
|
|
<struct name="flexcan_time_segment">
|
|
<setting name="flexcan_cfg_propSeg" value="21"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="42"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="16"/>
|
|
<setting name="flexcan_cfg_preDivider" value="1"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="15"/>
|
|
</struct>
|
|
<struct name="flexcan_time_segment_cbt">
|
|
<setting name="flexcan_cfg_propSeg" value="10"/>
|
|
<setting name="flexcan_cfg_phaseSeg1" value="4"/>
|
|
<setting name="flexcan_cfg_phaseSeg2" value="5"/>
|
|
<setting name="flexcan_cfg_preDivider" value="2"/>
|
|
<setting name="flexcan_cfg_rJumpwidth" value="5"/>
|
|
</struct>
|
|
<setting name="FlexCanCallback" value="CAN5_Callback"/>
|
|
<setting name="FlexCanErrorCallback" value="CAN5_ErrCallback"/>
|
|
<setting name="num_enhanced_std_id_filters" value="0"/>
|
|
<setting name="num_enhanced_ext_id_filters" value="0"/>
|
|
<setting name="num_enhanced_watermark" value="0"/>
|
|
<setting name="is_enhanced_rx_fifo_needed" value="false"/>
|
|
</struct>
|
|
</array>
|
|
<struct name="FlexCAN_General">
|
|
<setting name="FlexCANEnableUserModeSupport" value="false"/>
|
|
<setting name="FlexCANEnableTimeStampSupport" value="false"/>
|
|
<setting name="FlexCANIpDevErrorDetect" value="true"/>
|
|
<setting name="hrSrc" value="FLEXCAN_HRTIMERSRC_MAC"/>
|
|
</struct>
|
|
<struct name="timeout">
|
|
<setting name="timeout_type" value="OSIF_COUNTER_DUMMY"/>
|
|
<setting name="timeout_value" value="100"/>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Emios_Mcl_Ip_1" uuid="f09f8bb5-351a-43e0-b215-056336433efc" type="Emios_Mcl_Ip" type_id="Emios_Mcl_Ip" mode="emios_mcl" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="emios_mcl_ip">
|
|
<setting name="Name" value="EmiosMcl"/>
|
|
<struct name="MclGeneral">
|
|
<setting name="MclEnableDevErrorDetect" value="true"/>
|
|
<struct name="MclEmiosCommon">
|
|
<setting name="Name" value="MclEmiosCommon"/>
|
|
<setting name="MclEnableEmiosCommon" value="true"/>
|
|
</struct>
|
|
</struct>
|
|
<array name="EmiosCommon">
|
|
<struct name="0">
|
|
<setting name="Name" value="EmiosCommon_0"/>
|
|
<setting name="EmiosMclInstances" value="EMIOS_0"/>
|
|
<setting name="EmiosMclEnableFreezState" value="true"/>
|
|
<setting name="EmiosMclEnableGlobalTimeBase" value="true"/>
|
|
<setting name="EmiosMclClkDivVal" value="1"/>
|
|
<array name="EmiosMclMasterBus">
|
|
<struct name="0">
|
|
<setting name="Name" value="EMIOS_0_MasteBus0"/>
|
|
<setting name="EmiosMclMasterBusNumber" value="23"/>
|
|
<setting name="EmiosMclMasterBusModeType" value="MCB_UP_COUNTER"/>
|
|
<setting name="EmiosMclDefaultPeriod" value="16000"/>
|
|
<setting name="EmiosMclFirstOffsetValue" value="0"/>
|
|
<setting name="EmiosMclMasterBusPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclMasterBusAltPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclChannelAllowDebugMode" value="true"/>
|
|
<setting name="EmiosMclInterruptEnable" value="true"/>
|
|
<setting name="EmiosMclPwmExclusiveAccess" value="false"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="EmiosCommon_1"/>
|
|
<setting name="EmiosMclInstances" value="EMIOS_1"/>
|
|
<setting name="EmiosMclEnableFreezState" value="true"/>
|
|
<setting name="EmiosMclEnableGlobalTimeBase" value="true"/>
|
|
<setting name="EmiosMclClkDivVal" value="1"/>
|
|
<array name="EmiosMclMasterBus">
|
|
<struct name="0">
|
|
<setting name="Name" value="EMIOS_1_MasteBus0"/>
|
|
<setting name="EmiosMclMasterBusNumber" value="23"/>
|
|
<setting name="EmiosMclMasterBusModeType" value="MCB_UP_COUNTER"/>
|
|
<setting name="EmiosMclDefaultPeriod" value="16000"/>
|
|
<setting name="EmiosMclFirstOffsetValue" value="0"/>
|
|
<setting name="EmiosMclMasterBusPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclMasterBusAltPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclChannelAllowDebugMode" value="true"/>
|
|
<setting name="EmiosMclInterruptEnable" value="true"/>
|
|
<setting name="EmiosMclPwmExclusiveAccess" value="false"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="EmiosCommon_2"/>
|
|
<setting name="EmiosMclInstances" value="EMIOS_2"/>
|
|
<setting name="EmiosMclEnableFreezState" value="true"/>
|
|
<setting name="EmiosMclEnableGlobalTimeBase" value="true"/>
|
|
<setting name="EmiosMclClkDivVal" value="1"/>
|
|
<array name="EmiosMclMasterBus">
|
|
<struct name="0">
|
|
<setting name="Name" value="EMIOS_2_MasteBus0"/>
|
|
<setting name="EmiosMclMasterBusNumber" value="23"/>
|
|
<setting name="EmiosMclMasterBusModeType" value="MCB_UP_COUNTER"/>
|
|
<setting name="EmiosMclDefaultPeriod" value="16000"/>
|
|
<setting name="EmiosMclFirstOffsetValue" value="0"/>
|
|
<setting name="EmiosMclMasterBusPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclMasterBusAltPrescaler" value="DIV_1"/>
|
|
<setting name="EmiosMclChannelAllowDebugMode" value="true"/>
|
|
<setting name="EmiosMclInterruptEnable" value="true"/>
|
|
<setting name="EmiosMclPwmExclusiveAccess" value="false"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</array>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Emios_pwm_1" uuid="4d53db2f-ce0b-425f-aaa9-fdfe32228d6b" type="Emios_pwm" type_id="Emios_pwm" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Emios_pwm">
|
|
<struct name="PwmGeneral">
|
|
<setting name="Name" value=""/>
|
|
<setting name="PwmDevErrorDetect" value="false"/>
|
|
</struct>
|
|
<array name="PwmEmios">
|
|
<struct name="0">
|
|
<setting name="Name" value="PwmEmios_0"/>
|
|
<setting name="PwmHwInstance" value="Emios_0"/>
|
|
<array name="PwmEmiosChannels">
|
|
<struct name="0">
|
|
<setting name="Name" value="PwmEmiosChannels_0"/>
|
|
<setting name="EmiosChId" value="CH_0"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="PwmEmiosChannels_1"/>
|
|
<setting name="EmiosChId" value="CH_1"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="PwmEmiosChannels_2"/>
|
|
<setting name="EmiosChId" value="CH_2"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="PwmEmiosChannels_3"/>
|
|
<setting name="EmiosChId" value="CH_3"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="PwmEmios_1"/>
|
|
<setting name="PwmHwInstance" value="Emios_1"/>
|
|
<array name="PwmEmiosChannels">
|
|
<struct name="0">
|
|
<setting name="Name" value="PwmEmiosChannels_0"/>
|
|
<setting name="EmiosChId" value="CH_1"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="PwmEmiosChannels_1"/>
|
|
<setting name="EmiosChId" value="CH_2"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="PwmEmiosChannels_2"/>
|
|
<setting name="EmiosChId" value="CH_3"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="3">
|
|
<setting name="Name" value="PwmEmiosChannels_3"/>
|
|
<setting name="EmiosChId" value="CH_16"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="4">
|
|
<setting name="Name" value="PwmEmiosChannels_4"/>
|
|
<setting name="EmiosChId" value="CH_19"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
<struct name="5">
|
|
<setting name="Name" value="PwmEmiosChannels_5"/>
|
|
<setting name="EmiosChId" value="CH_22"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<struct name="2">
|
|
<setting name="Name" value="PwmEmios_2"/>
|
|
<setting name="PwmHwInstance" value="Emios_2"/>
|
|
<array name="PwmEmiosChannels">
|
|
<struct name="0">
|
|
<setting name="Name" value="PwmEmiosChannels_0"/>
|
|
<setting name="EmiosChId" value="CH_2"/>
|
|
<setting name="EmiosChMode" value="EMIOS_PWM_MODE_OPWMB"/>
|
|
<setting name="EmiosChFlagGeneration" value="Trailing_Edge"/>
|
|
<setting name="EmiosChCounterBus" value="EMIOS_PWM_BUS_A"/>
|
|
<setting name="EmiosChFreeze" value="false"/>
|
|
<setting name="EmiosChOutputDisable" value="EMIOS_PWM_OUTPUT_DISABLE_NONE"/>
|
|
<setting name="EmiosChPrescaler" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerAlternate" value="EMIOS_PWM_CLOCK_DIV_1"/>
|
|
<setting name="EmiosChPrescalerSource" value="EMIOS_PWM_PS_SRC_MODULE_CLOCK"/>
|
|
<setting name="EmiosChPolarity" value="EMIOS_PWM_ACTIVE_HIGH"/>
|
|
<setting name="EmiosChInterrupt" value="EMIOS_PWM_NOTIFICATION_DISABLED"/>
|
|
<struct name="EmiosChIrqCallback">
|
|
<setting name="Name" value="EmiosChIrqCallback"/>
|
|
<setting name="EmiosChIrqFunctionCallback" value="NULL_PTR"/>
|
|
<setting name="EmiosChIrqParameterCallback" value="NULL_PTR"/>
|
|
</struct>
|
|
<setting name="EmiosChDutyCycle" value="0"/>
|
|
<setting name="EmiosChPeriod" value="65534"/>
|
|
<setting name="EmiosChPhaseShift" value="0"/>
|
|
<setting name="EmiosChTrigger" value="0"/>
|
|
<setting name="EmiosChDeadtime" value="0"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</array>
|
|
<setting name="Name" value="Emios_Pwm"/>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Lpi2c_1" uuid="5dc0a5bc-9061-4772-8cec-378c7339561b" type="Lpi2c" type_id="Lpi2c" mode="lpi2c" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="lpi2c">
|
|
<struct name="GeneralConfiguration">
|
|
<setting name="I2cEnableUserModeSupport" value="false"/>
|
|
<setting name="I2cDevErrorDetect" value="false"/>
|
|
<setting name="I2cDmaUsed" value="false"/>
|
|
<setting name="I2c_ErrorCallback" value="false"/>
|
|
<setting name="I2cTimeoutMethod" value="OSIF_COUNTER_SYSTEM"/>
|
|
</struct>
|
|
<struct name="I2cGlobalConfig">
|
|
<setting name="Name" value="I2cGlobalConfig"/>
|
|
<array name="I2cChannel">
|
|
<struct name="0">
|
|
<setting name="I2cChannelId" value="0"/>
|
|
<setting name="I2cHwChannel" value="LPI2C_1"/>
|
|
<setting name="I2cOperatingMode" value="LPI2C_STANDARD_MODE"/>
|
|
<setting name="I2cMasterSlaveConfiguration" value="MASTER_MODE"/>
|
|
<struct name="I2cMasterConfiguration">
|
|
<setting name="Name" value="I2c_Lpi2cMasterChannel0"/>
|
|
<setting name="I2cSlaveAddress" value="0x32"/>
|
|
<setting name="I2cSlaveIs10BitAddress" value="false"/>
|
|
<setting name="I2cPrescaler" value="LPI2C_MASTER_PRESC_DIV_32"/>
|
|
<setting name="I2cDataValidDelay" value="0"/>
|
|
<setting name="I2cSetupHoldDelay" value="0"/>
|
|
<setting name="I2cClockHighPeriod" value="5"/>
|
|
<setting name="I2cClockLowPeriod" value="5"/>
|
|
<setting name="I2cPinLowTimeout" value="0"/>
|
|
<setting name="I2cBusIdleTimeout" value="0"/>
|
|
<setting name="I2cMasterFilterEnable" value="false"/>
|
|
<setting name="I2cGlitchFilterSDA" value="0"/>
|
|
<setting name="I2cGlitchFilterSCL" value="0"/>
|
|
<setting name="I2cAsyncMethod" value="LPI2C_USING_INTERRUPTS"/>
|
|
<array name="I2cDmaTxChannelRef"/>
|
|
<array name="I2cDmaRxChannelRef"/>
|
|
<setting name="I2cClockRef" value="40000000"/>
|
|
<setting name="I2cBaudRate" value="104167"/>
|
|
<setting name="lpi2c_master_cfg_masterCallback" value="NULL_PTR"/>
|
|
<setting name="lpi2c_master_cfg_callbackParam" value="0"/>
|
|
<struct name="I2cHighSpeedModeConfiguration">
|
|
<setting name="I2cMasterCode" value="0"/>
|
|
<setting name="I2cDataValidDelay" value="1"/>
|
|
<setting name="I2cSetupHoldDelay" value="2"/>
|
|
<setting name="I2cClockHighPeriod" value="1"/>
|
|
<setting name="I2cClockLowPeriod" value="3"/>
|
|
<setting name="I2cHighSpeedBaudRate" value="208333"/>
|
|
</struct>
|
|
</struct>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="I2cChannelId" value="1"/>
|
|
<setting name="I2cHwChannel" value="LPI2C_0"/>
|
|
<setting name="I2cOperatingMode" value="LPI2C_STANDARD_MODE"/>
|
|
<setting name="I2cMasterSlaveConfiguration" value="SLAVE_MODE"/>
|
|
<struct name="I2cSlaveConfiguration">
|
|
<setting name="Name" value="I2c_Lpi2cMasterChannel1"/>
|
|
<setting name="I2cSlaveAddress" value="0x32"/>
|
|
<setting name="I2cSlaveIs10BitAddress" value="false"/>
|
|
<setting name="Lpi2cSlaveListening" value="true"/>
|
|
<setting name="I2cSlaveFilterEnable" value="false"/>
|
|
<setting name="I2cGlitchFilterSDA" value="0"/>
|
|
<setting name="I2cGlitchFilterSCL" value="0"/>
|
|
<setting name="I2cAsyncMethod" value="LPI2C_USING_INTERRUPTS"/>
|
|
<array name="I2cSlaveDmaTxChannelRef"/>
|
|
<array name="I2cSlaveDmaRxChannelRef"/>
|
|
<setting name="lpi2c_slave_cfg_slaveCallback" value=""/>
|
|
<setting name="lpi2c_slave_cfg_callbackParam" value=""/>
|
|
</struct>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Os_1" uuid="63b35957-dd30-4bfa-9725-43a4500c2749" type="Os" type_id="Os" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Os" quick_selection="Default">
|
|
<setting name="Name" value="Os"/>
|
|
<struct name="ConfigTimeSupport">
|
|
<setting name="POST_BUILD_VARIANT_USED" value="false"/>
|
|
<setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
|
|
</struct>
|
|
<array name="OsApplication"/>
|
|
<array name="OsCounter">
|
|
<struct name="0">
|
|
<setting name="Name" value="OsCounter_0"/>
|
|
<setting name="OsCounterMaxAllowedValue" value="1"/>
|
|
<setting name="OsCounterMinCycle" value="1"/>
|
|
<setting name="OsCounterTicksPerBase" value="1"/>
|
|
<setting name="OsCounterType" value="HARDWARE"/>
|
|
<array name="OsSecondsPerTick"/>
|
|
</struct>
|
|
</array>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Swt_Ip_1" uuid="45b74ac4-6cac-4128-86be-017c4728a46f" type="Swt_Ip" type_id="Swt_Ip" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Swt_Ip">
|
|
<struct name="SwtUserCfg">
|
|
<setting name="SwtDevErrorDetect" value="false"/>
|
|
<setting name="SwtDisableAllowed" value="true"/>
|
|
<setting name="SwtEnableClearResetRequest" value="false"/>
|
|
<setting name="SwtOsifTimeoutMethod" value="DummyTimer"/>
|
|
<setting name="SwtOsifTimeoutVal" value="3000"/>
|
|
<setting name="WdgRunArea" value="RAM"/>
|
|
<array name="swtSettingsConfigRef">
|
|
<struct name="0">
|
|
<setting name="Name" value="Swt_Ip_1_Cfg0"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster0" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster1" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster2" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster3" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster4" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster5" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster6" value="true"/>
|
|
<setting name="WdgMasterAccessProtectionforMaster7" value="true"/>
|
|
<setting name="WdgResetOnInvalidAccess" value="BusError"/>
|
|
<setting name="WdgRunsInStopMode" value="false"/>
|
|
<setting name="WdgRunsInDebugMode" value="false"/>
|
|
<setting name="WdgOperationMode" value="ResetOnTimeOut"/>
|
|
<setting name="WdgKeyedService" value="false"/>
|
|
<setting name="WdgServiceKeyValue" value="0"/>
|
|
<setting name="WdgTimeoutPeriod" value="0.3"/>
|
|
<setting name="WdgWindowMode" value="false"/>
|
|
<setting name="WdgWindowPeriod" value="0"/>
|
|
<setting name="WdgSoftLockConfiguration" value="false"/>
|
|
<setting name="WdgHardLockConfiguration" value="false"/>
|
|
<setting name="SwtCallbackNotification" value="NULL"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Lpspi_1" uuid="31f0a583-d1c4-4e44-99cc-08bb7ddcebbf" type="Lpspi" type_id="Lpspi" mode="lpspi" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Lpspi">
|
|
<setting name="Name" value="Lpspi"/>
|
|
<struct name="SpiDriver">
|
|
<setting name="Name" value="SpiDriver"/>
|
|
<array name="SpiExternalDevice">
|
|
<struct name="0">
|
|
<setting name="Name" value="SpiExternalDevice_0"/>
|
|
<setting name="SpiBaudrate" value="100000"/>
|
|
<setting name="SpiCsIdentifier" value="PCS0"/>
|
|
<setting name="SpiCsPolarity" value="LOW"/>
|
|
<setting name="SpiDataShiftEdge" value="LEADING"/>
|
|
<setting name="SpiHwUnit" value="CSIB0"/>
|
|
<setting name="SpiShiftClockIdleLevel" value="HIGH"/>
|
|
<setting name="SpiDataWidth" value="8"/>
|
|
<setting name="SpiDefaultData" value="0"/>
|
|
<setting name="SpiTransferStart" value="LSB"/>
|
|
<setting name="SpiTimeClk2Cs" value="0.000001"/>
|
|
<setting name="SpiTimeCs2Clk" value="0.000001"/>
|
|
<setting name="SpiTimeCs2Cs" value="0.0000064"/>
|
|
<setting name="SpiCsContinous" value="TRUE"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
<struct name="SpiGeneral">
|
|
<setting name="Name" value="SpiGeneral"/>
|
|
<setting name="SpiEnableUserModeSupport" value="false"/>
|
|
<setting name="SpiEnableDmaFastTransferSupport" value="false"/>
|
|
<setting name="LpspiIpDevErrorDetect" value="true"/>
|
|
<setting name="SpiGlobalDmaEnable" value="false"/>
|
|
<setting name="SpiTimeoutMethod" value="DummyTimer"/>
|
|
<array name="SpiPhyUnit">
|
|
<struct name="0">
|
|
<setting name="Name" value="SpiPhyUnit_0"/>
|
|
<setting name="SpiPhyUnitMapping" value="LPSPI_1"/>
|
|
<setting name="SpiPinConfiguration" value="0"/>
|
|
<setting name="SpiSamplePoint" value="0"/>
|
|
<setting name="SpiPhyUnitClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<setting name="SpiPhyUnitMode" value="SPI_MASTER"/>
|
|
<setting name="SpiPhyUnitAsyncUseDma" value="false"/>
|
|
<array name="SpiPhyTxDmaChannel"/>
|
|
<array name="SpiPhyRxDmaChannel"/>
|
|
<array name="SpiMaxDmaFastTransfer"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="SpiPhyUnit_1"/>
|
|
<setting name="SpiPhyUnitMapping" value="LPSPI_2"/>
|
|
<setting name="SpiPinConfiguration" value="0"/>
|
|
<setting name="SpiSamplePoint" value="0"/>
|
|
<setting name="SpiPhyUnitClockFunctionalGroupRef" value="BOARD_BootClockRUN"/>
|
|
<setting name="SpiPhyUnitMode" value="SPI_SLAVE"/>
|
|
<setting name="SpiPhyUnitAsyncUseDma" value="false"/>
|
|
<array name="SpiPhyTxDmaChannel"/>
|
|
<array name="SpiPhyRxDmaChannel"/>
|
|
<array name="SpiMaxDmaFastTransfer"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
<instance name="Lpuart_Lin_1" uuid="c20b0354-76aa-4b91-97b5-2e26eea08919" type="Lpuart_Lin" type_id="Lpuart_Lin" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
|
<config_set name="Lpuart_Lin">
|
|
<setting name="Name" value="Lpuart_Lin"/>
|
|
<struct name="LinGeneral" quick_selection="Default">
|
|
<setting name="Name" value="LinGeneral"/>
|
|
<setting name="LinDevErrorDetect" value="false"/>
|
|
<setting name="LinIndex" value="0"/>
|
|
<setting name="LinTimeoutDuration" value="65535"/>
|
|
<setting name="LinTimeoutType" value="OSIF_COUNTER_DUMMY"/>
|
|
<setting name="LinFrameTimeoutDisable" value="false"/>
|
|
<array name="LinStartTimeoutNotification"/>
|
|
<array name="LinEndTimeoutNotification"/>
|
|
</struct>
|
|
<struct name="LinGlobalConfig">
|
|
<setting name="Name" value="LinGlobalConfig_0"/>
|
|
<array name="LinChannel">
|
|
<struct name="0">
|
|
<setting name="Name" value="LinChannel_0"/>
|
|
<setting name="LinChannelId" value="0"/>
|
|
<setting name="LinNodeType" value="MASTER"/>
|
|
<setting name="LinChannelBaudRate" value="9600"/>
|
|
<setting name="BreakLength" value="1"/>
|
|
<setting name="DetectedBreakLength" value="1"/>
|
|
<setting name="LinResponseTimeout" value="14"/>
|
|
<setting name="LinHeaderTimeout" value="44"/>
|
|
<setting name="LinHwChannel" value="LPUART_IP_1"/>
|
|
<setting name="LintimerGetTimeIntervalCallback" value="NULL"/>
|
|
<setting name="LinUserCallback" value="Lin1callback"/>
|
|
<setting name="LinAutobaudEnable" value="false"/>
|
|
<setting name="LinClassicTypePID" value="Classic"/>
|
|
<array name="LinNumOfClassicPID"/>
|
|
<setting name="Moduleclk" value="80000000"/>
|
|
</struct>
|
|
<struct name="1">
|
|
<setting name="Name" value="LinChannel_1"/>
|
|
<setting name="LinChannelId" value="1"/>
|
|
<setting name="LinNodeType" value="MASTER"/>
|
|
<setting name="LinChannelBaudRate" value="9600"/>
|
|
<setting name="BreakLength" value="1"/>
|
|
<setting name="DetectedBreakLength" value="1"/>
|
|
<setting name="LinResponseTimeout" value="14"/>
|
|
<setting name="LinHeaderTimeout" value="44"/>
|
|
<setting name="LinHwChannel" value="LPUART_IP_9"/>
|
|
<setting name="LintimerGetTimeIntervalCallback" value="NULL"/>
|
|
<setting name="LinUserCallback" value="Lin2callback"/>
|
|
<setting name="LinAutobaudEnable" value="false"/>
|
|
<setting name="LinClassicTypePID" value="Classic"/>
|
|
<array name="LinNumOfClassicPID"/>
|
|
<setting name="Moduleclk" value="80000000"/>
|
|
</struct>
|
|
</array>
|
|
</struct>
|
|
</config_set>
|
|
</instance>
|
|
</instances>
|
|
</functional_group>
|
|
</functional_groups>
|
|
<components>
|
|
<component name="system" uuid="a31f3c0f-2e20-439e-88c8-c0ed000de73a" type_id="system">
|
|
<config_set_global name="SystemModel">
|
|
<setting name="EcvdGenerationMethod" value="INDIVIDUAL"/>
|
|
<setting name="EcvdOutputPath" value=""/>
|
|
<setting name="EcvdGenerationTrigger" value="Generate Configuration"/>
|
|
</config_set_global>
|
|
</component>
|
|
</components>
|
|
</periphs>
|
|
</tools>
|
|
</configuration> |