smbae/ADM
1
0
Fork 0
mirror of https://github.com/Dev-KATECH/ADM.git synced 2026-05-17 01:43:59 +09:00
Code Issues Actions Packages Projects Releases Wiki Activity
cbe93f1365
ADM/GW/RTD/include/Emios_Pwm_Ip_HwAccess.h
S2-CHICKEN 77297108b6 VCU C code first commit
2024-08-08 10:00:15 +09:00

781 lines
31 KiB
C
Raw Blame History

/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral : Emios Flexio
* Dependencies : none
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
#ifndef EMIOS_PWM_IP_HWACCESS_H
#define EMIOS_PWM_IP_HWACCESS_H
/**
* @file Emios_Pwm_Ip_HwAccess.h
*
* @internal
* @addtogroup emios_pwm_ip Emios Pwm IPL
* @{
*/
#ifdef __cplusplus
extern "C"{
#endif
/*==================================================================================================
* INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "StandardTypes.h"
#include "Emios_Pwm_Ip_Cfg.h"
/*==================================================================================================
* SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define EMIOS_PWM_IP_HWACCESS_VENDOR_ID 43
#define EMIOS_PWM_IP_HWACCESS_MODULE_ID 121
#define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION 4
#define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION 4
#define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION 0
#define EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION 0
#define EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION 9
#define EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION 0
/*==================================================================================================
* FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if header file and StandardTypes.h are of the same AUTOSAR version */
#if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
(EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
#error "AUTOSAR Version Numbers of Emios_Pwm_Ip_HwAccess.h and StandardTypes.h are different"
#endif
#endif
/* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same vendor */
#if (EMIOS_PWM_IP_HWACCESS_VENDOR_ID != EMIOS_PWM_IP_CFG_VENDOR_ID)
#error "Vendor IDs of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
#endif
/* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same AUTOSAR version */
#if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \
(EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MINOR_VERSION) || \
(EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_REVISION_VERSION))
#error "AUTOSAR version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
#endif
/* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same software version */
#if ((EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION != EMIOS_PWM_IP_CFG_SW_MAJOR_VERSION) || \
(EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION != EMIOS_PWM_IP_CFG_SW_MINOR_VERSION) || \
(EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION != EMIOS_PWM_IP_CFG_SW_PATCH_VERSION))
#error "Software version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
#endif
/*==================================================================================================
* CONSTANTS
==================================================================================================*/
/*==================================================================================================
* DEFINES AND MACROS
==================================================================================================*/
/*==================================================================================================
* ENUMS
==================================================================================================*/
/*!
* @brief Emios PWM channel modes
*/
typedef enum
{
/** @brief Output Pulse Width and Frequency Modulation Buffered.*/
EMIOS_PWM_HW_MODE_OPWFMB = 0x00U,
/** @brief Center Aligned Output Pulse Width Modulation Buffered */
EMIOS_PWM_HW_MODE_OPWMCB = 0x01U,
/** @brief Output Pulse-Width Modulation with Trigger */
EMIOS_PWM_HW_MODE_OPWMB = 0x02U,
/** @brief Output Pulse Width Modulation Buffered. */
EMIOS_PWM_HW_MODE_OPWMT = 0x03U
} Emios_Pwm_Ip_PwmType;
/*!
* @brief Emios PWM master bus modes
*/
typedef enum
{
EMIOS_PWM_IP_MC_UP_COUNTER_START = 16u,
EMIOS_PWM_IP_MC_UP_COUNTER_END = 18u,
EMIOS_PWM_IP_MC_UP_DOWN_COUNTER = 20u,
EMIOS_PWM_IP_MCB_UP_COUNTER = 80u,
EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER = 84u,
EMIOS_PWM_IP_NODEFINE_COUNTER = 0u
} Emios_Pwm_Ip_MasterBusModeType;
/*==================================================================================================
* STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/
/*==================================================================================================
* GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/
/*==================================================================================================
* FUNCTION PROTOTYPES
==================================================================================================*/
#define PWM_START_SEC_CODE
#include "Pwm_MemMap.h"
/*-----------------------MCR Register----------------------------*/
/*!
* brief Get MCR Freeze enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
*/
static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const base)
{
return (((base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE;
}
/*-----------------------OUDIS Register----------------------------*/
/*!
* brief Set OUDIS Channel n enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
base->OUDIS = base->OUDIS | (eMIOS_OUDIS_OU0((value == TRUE) ? 0x00U : 0x01U) << channel);
}
/*!
* brief Get OUDIS Channel n enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
*/
static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)channel)) >> channel) == 0U) ? TRUE : FALSE;
}
/*!
* brief Get OUDIS register
* param[in] base The Emios base address pointer
*/
static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const base)
{
return (base->OUDIS);
}
/*-----------------------UCDIS Register----------------------------*/
/*!
* brief Set UCDIS Channel n enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetChannelEnable(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
base->UCDIS = base->UCDIS | (eMIOS_UCDIS_UCDIS0((value == TRUE) ? 0x00U : 0x01U) << channel);
}
/*!
* brief Get UCDIS Channel n enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline boolean Emios_Pwm_Ip_GetChannelEnable(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->UCDIS & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)channel)) >> channel) == 0U) ? TRUE : FALSE;
}
/*-----------------------UC register A-----------------------------*/
/*!
* brief Set A register's value, maximum value is 0xFFFF
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
uint16 value)
{
base->CH.UC[channel].A = eMIOS_A_A(value);
}
/*!
* brief Get A register's value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Unified Channels A register
*/
static inline uint16 Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (uint16)((base->CH.UC[channel].A & eMIOS_A_A_MASK) >> eMIOS_A_A_SHIFT);
}
/*-----------------------UC register B-----------------------------*/
/*!
* brief Set B register's value, maximum value is 0xFFFFFF
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
uint16 value)
{
base->CH.UC[channel].B = eMIOS_B_B(value);
}
/*!
* brief Get B register's value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Unified Channels B register
*/
static inline uint16 Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (uint16)((base->CH.UC[channel].B & eMIOS_B_B_MASK) >> eMIOS_B_B_SHIFT);
}
/*-----------------------UC register CNT-----------------------------*/
/*!
* brief Get CNT register's value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Unified Channels CNT register
*/
static inline uint16 Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (uint16)((base->CH.UC[channel].CNT & eMIOS_CNT_C_MASK) >> eMIOS_CNT_C_SHIFT);
}
/*----------------------------UC register C bit fields--------------------------*/
/*!
* brief Set Freeze Enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Normal operation
* - 1 Freeze UC registers values
*/
static inline void Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_FREN_MASK)) | eMIOS_C_FREN(value_convert);
}
/*!
* brief Set Output Disable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetOutDisable(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_ODIS_MASK)) | eMIOS_C_ODIS(value_convert);
}
/*!
* brief Set Output Disable select value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetOutDisableSource(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_OutDisableSourceType value)
{
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_ODISSL_MASK)) | eMIOS_C_ODISSL(value);
}
/*!
* brief Set Prescaler Enable bit.
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Prescaler disabled (no clock)
* - 1 Prescaler enabled
*/
static inline void Emios_Pwm_Ip_SetPrescalerEnable(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_UCPREN_MASK)) | eMIOS_C_UCPREN(value_convert);
}
/* Bitfiled UCPRE is not used. Instead the value is controled using UCEXTPRE from C2 */
/*!
* brief Set Direct Memory Access bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Flag/overrun assigned to Interrupt request.
* - 1 Flag/overrun assigned to DMA request.
*/
static inline void Emios_Pwm_Ip_SetDMARequest(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_DMA_MASK)) | eMIOS_C_DMA(value_convert);
}
/*!
* brief Get Direct Memory Access bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Direct Memory Access state in Unified Channels Control register
* - 0 Flag/overrun assigned to Interrupt request.
* - 1 Flag/overrun assigned to DMA request.
*/
static inline boolean Emios_Pwm_Ip_GetDMARequest(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE;
}
/*!
* brief Set FLAG Enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Disable (FLAG does not generate an interrupt request)
* - 1 Enable (FLAG generates an interrupt request)
*/
static inline void Emios_Pwm_Ip_SetInterruptRequest(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_FEN_MASK)) | eMIOS_C_FEN(value_convert);
}
/*!
* brief Get FLAG Enable bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of FLAG Enable bit
* - 0 Disable (FLAG does not generate an interrupt request)
* - 1 Enable (FLAG generates an interrupt request)
*/
static inline boolean Emios_Pwm_Ip_GetInterruptRequest(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE;
}
/*!
* brief Force Match A bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Has no effect.
* - 1 Force a match at comparator A
*/
static inline void Emios_Pwm_Ip_SetForceMatchA(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_FORCMA_MASK)) | eMIOS_C_FORCMA(value_convert);
}
/*!
* brief Force Match B bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Has no effect.
* - 1 Force a match at comparator B
*/
static inline void Emios_Pwm_Ip_SetForceMatchB(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
boolean value)
{
uint8 value_convert = (value == FALSE)? 0U : 1U;
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_FORCMB_MASK)) | eMIOS_C_FORCMB(value_convert);
}
/*!
* brief Set Bus Select bits.
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetCounterBus(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_CounterBusSourceType value)
{
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_BSL_MASK)) | eMIOS_C_BSL(value);
}
/*!
* brief Get Bus Select value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Bus Select in Unified Channels Control register
*/
static inline Emios_Pwm_Ip_CounterBusSourceType Emios_Pwm_Ip_GetCounterBus(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
Emios_Pwm_Ip_CounterBusSourceType counterBus;
switch((base->CH.UC[channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT)
{
case 0x00U:
counterBus = EMIOS_PWM_BUS_A;
break;
case 0x01U:
counterBus = EMIOS_PWM_BUS_BCDE;
break;
case 0x02U:
counterBus = EMIOS_PWM_BUS_F;
break;
default:
counterBus = EMIOS_PWM_BUS_INTERNAL;
break;
}
return counterBus;
}
/*!
* brief Set Edge Polarity bit.
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetEdgePolarity(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_PolarityType value)
{
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_EDPOL(value);
}
/*!
* brief Get Edge Polarity bit.
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Edge Polarity bit in Unified Channels Control register
*/
static inline Emios_Pwm_Ip_PolarityType Emios_Pwm_Ip_GetEdgePolarity(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].C & eMIOS_C_EDPOL_MASK) >> eMIOS_C_EDPOL_SHIFT) == 0U)? (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_ACTIVE_LOW : (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_ACTIVE_HIGH;
}
/*!
* brief Set mode of operation of the Unified Channel
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] mode The mode to set
*/
static inline void Emios_Pwm_Ip_SetPwmMode(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_PwmModeType mode)
{
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_MODE_MASK)) | eMIOS_C_MODE(mode);
}
/*!
* brief Get mode of operation of the Unified Channel
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Mode selection in Unified Channels Control register
*/
static inline Emios_Pwm_Ip_PwmModeType Emios_Pwm_Ip_GetPwmMode(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
Emios_Pwm_Ip_PwmModeType mode;
switch ((base->CH.UC[channel].C & eMIOS_C_MODE_MASK) >> eMIOS_C_MODE_SHIFT)
{
case 0x01U:
mode = EMIOS_PWM_MODE_GPO;
break;
case 0x06U:
mode = EMIOS_PWM_MODE_DAOC_FLAG;
break;
case 0x07U:
mode = EMIOS_PWM_MODE_DAOC_FLAG_BOTH;
break;
case 0x26U:
mode = EMIOS_PWM_MODE_OPWMT;
break;
case 0x58U:
mode = EMIOS_PWM_MODE_OPWFMB_FLAG;
break;
case 0x5AU:
mode = EMIOS_PWM_MODE_OPWFMB_FLAG_BOTH;
break;
case 0x5CU:
mode = EMIOS_PWM_MODE_OPWMCB_TRAIL_EDGE_FLAG;
break;
case 0x5EU:
mode = EMIOS_PWM_MODE_OPWMCB_TRAIL_EDGE_FLAG_BOTH;
break;
case 0x5DU:
mode = EMIOS_PWM_MODE_OPWMCB_LEAD_EDGE_FLAG;
break;
case 0x5FU:
mode = EMIOS_PWM_MODE_OPWMCB_LEAD_EDGE_FLAG_BOTH;
break;
case 0x60U:
mode = EMIOS_PWM_MODE_OPWMB_FLAG;
break;
case 0x62U:
mode = EMIOS_PWM_MODE_OPWMB_FLAG_BOTH;
break;
default:
mode = EMIOS_PWM_MODE_NODEFINE;
break;
}
return mode;
}
/*!
* brief Set mode and Edge Polarity bit of operation of the Unified Channel at the same time to avoid spike pulse
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] mode The mode to set
* param[in] pol The Edge polarity to set
* return void
*/
static inline void Emios_Pwm_Ip_SetPwmModePol(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_PwmModeType mode,
Emios_Pwm_Ip_PolarityType pol)
{
base->CH.UC[channel].C = (base->CH.UC[channel].C & ~(eMIOS_C_MODE_MASK) & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_MODE(mode) | eMIOS_C_EDPOL(pol);
}
/*!
* brief Get mode of operation of the Unified Channel
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Mode selection in Unified Channels Control register
*/
static inline Emios_Pwm_Ip_MasterBusModeType Emios_Pwm_Ip_GetChannelPwmMode( const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
Emios_Pwm_Ip_MasterBusModeType masterBusMode;
switch ((base->CH.UC[channel].C & eMIOS_C_MODE_MASK) >> eMIOS_C_MODE_SHIFT)
{
case 16U:
masterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_START;
break;
case 18U:
masterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_END;
break;
case 20U:
masterBusMode = EMIOS_PWM_IP_MC_UP_DOWN_COUNTER;
break;
case 80U:
masterBusMode = EMIOS_PWM_IP_MCB_UP_COUNTER;
break;
case 84U:
masterBusMode = EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER;
break;
default:
masterBusMode = EMIOS_PWM_IP_NODEFINE_COUNTER;
break;
}
return masterBusMode;
}
/*----------------------UC register S bit field-----------------------------*/
/*!
* brief Write 1 to clear overrun bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
*/
static inline void Emios_Pwm_Ip_ClearOverRunFlag(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
/* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
base->CH.UC[channel].S = (base->CH.UC[channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVR(1UL);
}
/*!
* brief Get overrun bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Overrun bit in Unified Channels Control register
* The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set .
* The OVR bit can be cleared either by clearing the FLAG bit or by writing a 1 to the OVR bit.
* - 0 Overrun has not occurred
* - 1 Overrun has occurred
*/
static inline boolean Emios_Pwm_Ip_GetOverRunFlag(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].S & eMIOS_S_OVR_MASK) >> eMIOS_S_OVR_SHIFT) == 0U)? FALSE : TRUE;
}
/*!
* brief Write 1 to clear the overflow bit.
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
*/
static inline void Emios_Pwm_Ip_ClearOverFlowFlag(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
/* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
base->CH.UC[channel].S = (base->CH.UC[channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVFL(1UL);
}
/*!
* brief Get Overflow bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Overflow bit in Unified Channels Control register
* The OVFL bit indicates that an overflow has occurred in the internal counter.
* The OVFL bit must be cleared by software writing a 1 to it.
* - 0 No overflow
* - 1 An overflow had occurred
*/
static inline boolean Emios_Pwm_Ip_GetOverFlowFlag(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].S & eMIOS_S_OVFL_MASK) >> eMIOS_S_OVFL_SHIFT) == 0U)? FALSE : TRUE;
}
/*!
* brief Get Unified Channel Output pin bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of Unified Channel Output pin bit in Unified Channels Control register
*/
static inline boolean Emios_Pwm_Ip_GetOutputPinState(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].S & eMIOS_S_UCOUT_MASK) >> eMIOS_S_UCOUT_SHIFT) == 0U)? (boolean)FALSE : (boolean)TRUE;
}
/*!
* brief Write 1 to clear the FLAG bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
*/
static inline void Emios_Pwm_Ip_ClearFlagEvent(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
/* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
base->CH.UC[channel].S = (base->CH.UC[channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_FLAG(1UL);
}
/*!
* brief Get FLAG bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of FLAG bit in Unified Channels Control register
* The FLAG bit indicates that a match event has occurred in the channel.
* The FLAG bit must be cleared by software writing a 1 to it.
* - 0 No flag event
* - 1 A flag eventhad occurred
*/
static inline boolean Emios_Pwm_Ip_GetOverFlagEvent(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (((base->CH.UC[channel].S & eMIOS_S_FLAG_MASK) >> eMIOS_S_FLAG_SHIFT) == 0U)? FALSE : TRUE;
}
/*-----------------------UC register ALTA-----------------------------*/
/*!
* brief Set A2 channel registers value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetTrigger(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
uint16 value)
{
base->CH.UC[channel].ALTA = (base->CH.UC[channel].ALTA & ~(eMIOS_ALTA_ALTA_MASK)) | eMIOS_ALTA_ALTA(value);
}
/*!
* brief Get A2 channel registers value
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* return Value of A2 channel registers in Unified Channels Control register
*/
static inline uint16 Emios_Pwm_Ip_GetTrigger(const Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel)
{
return (uint16)((base->CH.UC[channel].ALTA & eMIOS_ALTA_ALTA_MASK) >> eMIOS_ALTA_ALTA_SHIFT);
}
/*------------------UC register C2 --------------------------*/
/*!
* brief Set Extended Prescaler bits
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
*/
static inline void Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_InternalClkPsType value)
{
base->CH.UC[channel].C2 = (base->CH.UC[channel].C2 & ~(eMIOS_C2_UCEXTPRE_MASK)) | eMIOS_C2_UCEXTPRE(value);
}
/*!
* brief Set Prescaler Clock select bit
* param[in] base The Emios base address pointer
* param[in] channel The channel id for the given instance
* param[in] value The value to set
* - 0 Prescaled Clock
* - 1 eMIOS module clock
*/
static inline void Emios_Pwm_Ip_SetPrescalerSource(Emios_Pwm_Ip_HwAddrType *const base,
uint8 channel,
Emios_Pwm_Ip_InternalPsSrcType value)
{
base->CH.UC[channel].C2 = (base->CH.UC[channel].C2 & ~(eMIOS_C2_UCPRECLK_MASK)) | eMIOS_C2_UCPRECLK(value);
}
#define PWM_STOP_SEC_CODE
#include "Pwm_MemMap.h"
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* EMIOS_PWM_IP_HWACCESS_H */
Reference in New Issue View Git Blame Copy Permalink