ADM/GW/Debug_RAM/RTD/src/Clock_Ip_ProgFreqSwitch.c.060i.targetclone
2024-08-08 10:00:15 +09:00

73 lines
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CgmXPcfsSdurDivcDiveDivs (const struct Clock_Ip_PcfsConfigType * config)
{
uint32 swIndex;
uint32 hwIndex;
uint32 instance;
<unnamed type> _1;
int _2;
unsigned char _3;
unsigned char _4;
unsigned char _5;
long unsigned int _6;
volatile struct cgmPcfs_Type * _7;
long unsigned int _8;
long unsigned int _9;
long unsigned int _10;
long unsigned int _11;
long unsigned int _12;
long unsigned int _13;
long unsigned int _14;
long unsigned int _15;
long unsigned int _16;
long unsigned int _17;
<bb 2> [local count: 1073741824]:
# DEBUG BEGIN_STMT
_1 = config_19(D)->name;
_2 = (int) _1;
_3 = clockFeatures[_2][2];
instance_20 = (uint32) _3;
# DEBUG instance => instance_20
# DEBUG BEGIN_STMT
_4 = clockFeatures[_2][4];
hwIndex_21 = (uint32) _4;
# DEBUG hwIndex => hwIndex_21
# DEBUG BEGIN_STMT
_5 = clockFeatures[_2][5];
swIndex_22 = (uint32) _5;
# DEBUG swIndex => swIndex_22
# DEBUG BEGIN_STMT
_6 = pcfsEntries[swIndex_22].sdur;
_7 = cgmPcfs[instance_20];
_8 = _6 & 65535;
_7->PCFS_SDUR ={v} _8;
# DEBUG BEGIN_STMT
_9 = pcfsEntries[swIndex_22].divc_rate;
_10 = _9 & 255;
_11 = pcfsEntries[swIndex_22].divc_init;
_12 = _11 << 16;
_13 = _10 | _12;
_7->PCFS[hwIndex_21].DIVC ={v} _13;
# DEBUG BEGIN_STMT
_14 = pcfsEntries[swIndex_22].div_endValue;
_15 = _14 & 1048575;
_7->PCFS[hwIndex_21].DIVE ={v} _15;
# DEBUG BEGIN_STMT
_16 = pcfsEntries[swIndex_22].div_startValue;
_17 = _16 & 1048575;
_7->PCFS[hwIndex_21].DIVS ={v} _17;
return;
}
ProgressiveFrequencyClockSwitchEmpty (const struct Clock_Ip_PcfsConfigType * config)
{
<bb 2> [local count: 1073741824]:
# DEBUG BEGIN_STMT
return;
}