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c3ce113903
ADM/GW/Debug_FLASH/RTD/src/SchM_Spi.c.016i.visibility

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Marking local functions:
Marking externally visible functions: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 Spi_schm_read_msr
Marking externally visible variables:
Reclaiming functions:
Reclaiming variables:
Clearing address taken flags:
Symbol table:
Sys_GetCoreID/77 (Sys_GetCoreID) @05e7bee0
Type: function
Visibility: external public
References:
Referring:
Availability: not_available
Function flags: optimize_size
Called by: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39
Calls:
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18) @05e7b9a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18) @05e7b700
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)msr_SPI_EXCLUSIVE_AREA_18/36 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17) @05e7b460
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17) @05e7b1c0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)msr_SPI_EXCLUSIVE_AREA_17/34 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16) @05e72d20
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16) @05e727e0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)msr_SPI_EXCLUSIVE_AREA_16/32 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15) @05e722a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15) @05e72ee0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)msr_SPI_EXCLUSIVE_AREA_15/30 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14) @05e72c40
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14) @05e729a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)msr_SPI_EXCLUSIVE_AREA_14/28 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13) @05e72700
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13) @05e72460
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)msr_SPI_EXCLUSIVE_AREA_13/26 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12) @05e721c0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12) @05e6cd20
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)msr_SPI_EXCLUSIVE_AREA_12/24 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11) @05e6c7e0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11) @05e6c2a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)msr_SPI_EXCLUSIVE_AREA_11/22 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10) @05e6cee0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10) @05e6cc40
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)msr_SPI_EXCLUSIVE_AREA_10/20 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09) @05e6c9a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09) @05e6c700
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)msr_SPI_EXCLUSIVE_AREA_09/18 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08) @05e6c460
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08) @05e6c1c0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)msr_SPI_EXCLUSIVE_AREA_08/16 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07) @05e65d20
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07) @05e657e0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)msr_SPI_EXCLUSIVE_AREA_07/14 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06) @05e652a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06) @05e65ee0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)msr_SPI_EXCLUSIVE_AREA_06/12 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05) @05e65c40
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05) @05e659a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)msr_SPI_EXCLUSIVE_AREA_05/10 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04) @05e65700
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04) @05e65460
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)msr_SPI_EXCLUSIVE_AREA_04/8 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03) @05e651c0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03) @05d71ee0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)msr_SPI_EXCLUSIVE_AREA_03/6 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02) @05d719a0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02) @05d71460
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)msr_SPI_EXCLUSIVE_AREA_02/4 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01) @05d71e00
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01) @05d71b60
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)msr_SPI_EXCLUSIVE_AREA_01/2 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00) @05d718c0
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Sys_GetCoreID/77
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00) @05d71620
Type: function definition analyzed
Visibility: externally_visible public
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)msr_SPI_EXCLUSIVE_AREA_00/0 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)
Referring:
Availability: available
Function flags: body optimize_size
Called by:
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
Spi_schm_read_msr/38 (Spi_schm_read_msr) @05d71380
Type: function definition analyzed
Visibility: externally_visible public
References:
Referring:
Availability: available
Function flags: body optimize_size
Called by: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39
Calls:
reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (reentry_guard_SPI_EXCLUSIVE_AREA_18) @05d6f1b0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_18/36 (msr_SPI_EXCLUSIVE_AREA_18) @05d6f120
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (reentry_guard_SPI_EXCLUSIVE_AREA_17) @05d6f090
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_17/34 (msr_SPI_EXCLUSIVE_AREA_17) @05d6f000
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (reentry_guard_SPI_EXCLUSIVE_AREA_16) @05d6af30
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_16/32 (msr_SPI_EXCLUSIVE_AREA_16) @05d6aea0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (reentry_guard_SPI_EXCLUSIVE_AREA_15) @05d6ae10
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_15/30 (msr_SPI_EXCLUSIVE_AREA_15) @05d6ad80
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (reentry_guard_SPI_EXCLUSIVE_AREA_14) @05d6acf0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_14/28 (msr_SPI_EXCLUSIVE_AREA_14) @05d6ac60
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (reentry_guard_SPI_EXCLUSIVE_AREA_13) @05d6abd0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_13/26 (msr_SPI_EXCLUSIVE_AREA_13) @05d6ab40
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (reentry_guard_SPI_EXCLUSIVE_AREA_12) @05d6aab0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_12/24 (msr_SPI_EXCLUSIVE_AREA_12) @05d6aa20
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (reentry_guard_SPI_EXCLUSIVE_AREA_11) @05d6a990
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_11/22 (msr_SPI_EXCLUSIVE_AREA_11) @05d6a900
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (reentry_guard_SPI_EXCLUSIVE_AREA_10) @05d6a870
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_10/20 (msr_SPI_EXCLUSIVE_AREA_10) @05d6a7e0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (reentry_guard_SPI_EXCLUSIVE_AREA_09) @05d6a750
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_09/18 (msr_SPI_EXCLUSIVE_AREA_09) @05d6a6c0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (reentry_guard_SPI_EXCLUSIVE_AREA_08) @05d6a630
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_08/16 (msr_SPI_EXCLUSIVE_AREA_08) @05d6a5a0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (reentry_guard_SPI_EXCLUSIVE_AREA_07) @05d6a510
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_07/14 (msr_SPI_EXCLUSIVE_AREA_07) @05d6a480
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (reentry_guard_SPI_EXCLUSIVE_AREA_06) @05d6a3f0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_06/12 (msr_SPI_EXCLUSIVE_AREA_06) @05d6a360
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (reentry_guard_SPI_EXCLUSIVE_AREA_05) @05d6a2d0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_05/10 (msr_SPI_EXCLUSIVE_AREA_05) @05d6a240
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (reentry_guard_SPI_EXCLUSIVE_AREA_04) @05d6a1b0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_04/8 (msr_SPI_EXCLUSIVE_AREA_04) @05d6a120
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (reentry_guard_SPI_EXCLUSIVE_AREA_03) @05d6a090
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_03/6 (msr_SPI_EXCLUSIVE_AREA_03) @05d6a000
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (reentry_guard_SPI_EXCLUSIVE_AREA_02) @05d62f30
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_02/4 (msr_SPI_EXCLUSIVE_AREA_02) @05d62ea0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (reentry_guard_SPI_EXCLUSIVE_AREA_01) @05d62e10
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_01/2 (msr_SPI_EXCLUSIVE_AREA_01) @05d62d80
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
Availability: available
Varpool flags:
reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (reentry_guard_SPI_EXCLUSIVE_AREA_00) @05d62cf0
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
Availability: available
Varpool flags:
msr_SPI_EXCLUSIVE_AREA_00/0 (msr_SPI_EXCLUSIVE_AREA_00) @05d62c60
Type: variable definition analyzed
Visibility: force_output prevailing_def_ironly
References:
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
Availability: available
Varpool flags:
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_18[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_18[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_17[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_17[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_16[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_16[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_15[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_15[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_14[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_14[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_13[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_13[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_12[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_12[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_11[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_11[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_10[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_10[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_09[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_09[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_08[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_08[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_07[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_07[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_06[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_06[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_05[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_05[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_04[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_04[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_03[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_03[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_02[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_02[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_01[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_01[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _7;
return;
}
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
_3 = _2 + 4294967295;
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_00[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
if (_6 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsie i");
<bb 5> :
return;
}
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 ()
{
uint32 u32CoreId;
<bb 2> :
# DEBUG BEGIN_STMT
_1 = Sys_GetCoreID ();
u32CoreId = (uint32) _1;
# DEBUG BEGIN_STMT
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
if (_2 == 0)
goto <bb 3>; [INV]
else
goto <bb 5>; [INV]
<bb 3> :
# DEBUG BEGIN_STMT
_3 = Spi_schm_read_msr ();
msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _3;
# DEBUG BEGIN_STMT
_4 = msr_SPI_EXCLUSIVE_AREA_00[u32CoreId];
_5 = _4 & 1;
if (_5 == 0)
goto <bb 4>; [INV]
else
goto <bb 5>; [INV]
<bb 4> :
# DEBUG BEGIN_STMT
__asm__ __volatile__(" cpsid i");
<bb 5> :
# DEBUG BEGIN_STMT
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
_7 = _6 + 1;
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _7;
return;
}
Spi_schm_read_msr ()
{
register uint32 reg_tmp;
uint32 D.4353;
<bb 2> :
# DEBUG BEGIN_STMT
# DEBUG BEGIN_STMT
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp);
# DEBUG BEGIN_STMT
D.4353 = reg_tmp;
return D.4353;
}
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