mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 01:43:59 +09:00
329 lines
6.3 KiB
Plaintext
329 lines
6.3 KiB
Plaintext
|
|
Marking local functions: sys_m7_cache_init
|
|
|
|
|
|
Marking externally visible functions: SystemInit Sys_GetCoreID default_interrupt_routine startup_go_to_user_mode
|
|
|
|
|
|
Marking externally visible variables: RESET_CATCH_CORE
|
|
|
|
|
|
Reclaiming functions:
|
|
Reclaiming variables:
|
|
Clearing address taken flags:
|
|
Symbol table:
|
|
|
|
sys_m7_cache_init/7 (sys_m7_cache_init) @06b9e700
|
|
Type: function definition analyzed
|
|
Visibility: prevailing_def_ironly
|
|
References:
|
|
Referring:
|
|
Availability: local
|
|
Function flags: body local optimize_size
|
|
Called by: SystemInit/6
|
|
Calls:
|
|
SystemInit/6 (SystemInit) @06b9ee00
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: rbar/0 (read)rasr/1 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: sys_m7_cache_init/7 Sys_GetCoreID/5
|
|
Sys_GetCoreID/5 (Sys_GetCoreID) @06b9eb60
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: SystemInit/6
|
|
Calls:
|
|
default_interrupt_routine/4 (default_interrupt_routine) @06b9e8c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls:
|
|
startup_go_to_user_mode/3 (startup_go_to_user_mode) @06b9e620
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls:
|
|
RESET_CATCH_CORE/2 (RESET_CATCH_CORE) @06b9a900
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
rasr/1 (rasr) @06b1d3a8
|
|
Type: variable definition analyzed
|
|
Visibility: prevailing_def_ironly
|
|
References:
|
|
Referring: SystemInit/6 (read)
|
|
Availability: available
|
|
Varpool flags: initialized read-only const-value-known
|
|
rbar/0 (rbar) @06b1d2d0
|
|
Type: variable definition analyzed
|
|
Visibility: prevailing_def_ironly
|
|
References:
|
|
Referring: SystemInit/6 (read)
|
|
Availability: available
|
|
Varpool flags: initialized read-only const-value-known
|
|
sys_m7_cache_init ()
|
|
{
|
|
uint32 ways;
|
|
uint32 sets;
|
|
uint32 ccsidr;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
ccsidr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sets = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ways = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 3758153728B;
|
|
_1->CSSELR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
_2 = 3758153728B;
|
|
ccsidr = _2->CCSIDR;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = ccsidr >> 13;
|
|
sets = _3 & 32767;
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_4 = ccsidr >> 3;
|
|
ways = _4 & 1023;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_5 = sets << 5;
|
|
_6 = _5 & 16352;
|
|
_7 = ways << 30;
|
|
_8 = 3758153728B;
|
|
_9 = _6 | _7;
|
|
_8->DCISW = _9;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
ways.1_10 = ways;
|
|
ways = ways.1_10 + 4294967295;
|
|
if (ways.1_10 != 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
sets.2_11 = sets;
|
|
sets = sets.2_11 + 4294967295;
|
|
if (sets.2_11 != 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
_12 = 3758153728B;
|
|
_13 = _12->CCR;
|
|
_14 = 3758153728B;
|
|
_15 = _13 | 65536;
|
|
_14->CCR = _15;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
# DEBUG BEGIN_STMT
|
|
_16 = 3758153728B;
|
|
_16->ICIALLU = 0;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
# DEBUG BEGIN_STMT
|
|
_17 = 3758153728B;
|
|
_18 = _17->CCR;
|
|
_19 = 3758153728B;
|
|
_20 = _18 | 131072;
|
|
_19->CCR = _20;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SystemInit ()
|
|
{
|
|
uint8 coreId;
|
|
uint8 regionNum;
|
|
uint32 coreMask;
|
|
uint32 i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
regionNum = 0;
|
|
# DEBUG BEGIN_STMT
|
|
coreId = Sys_GetCoreID ();
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) coreId;
|
|
switch (_1) <default: <L2> [INV], case 0: <L0> [INV], case 1: <L1> [INV]>
|
|
|
|
<bb 3> :
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
coreMask = 1;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 4> :
|
|
<L1>:
|
|
# DEBUG BEGIN_STMT
|
|
coreMask = 2;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
<L2>:
|
|
# DEBUG BEGIN_STMT
|
|
coreMask = 0;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_2 = 1076232192B;
|
|
_3 = _2->IRSPRC[i];
|
|
_4 = (short unsigned int) coreMask;
|
|
_5 = 1076232192B;
|
|
_6 = _3 | _4;
|
|
_5->IRSPRC[i] = _6;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 239)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
# DEBUG BEGIN_STMT
|
|
regionNum = 0;
|
|
goto <bb 11>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
_7 = 3758153728B;
|
|
_8 = (long unsigned int) regionNum;
|
|
_7->RNR = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) regionNum;
|
|
_10 = 3758153728B;
|
|
_11 = rbar[_9];
|
|
_10->RBAR = _11;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = (int) regionNum;
|
|
_13 = 3758153728B;
|
|
_14 = rasr[_12];
|
|
_13->RASR = _14;
|
|
# DEBUG BEGIN_STMT
|
|
regionNum.0_15 = regionNum;
|
|
regionNum = regionNum.0_15 + 1;
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
if (regionNum <= 13)
|
|
goto <bb 10>; [INV]
|
|
else
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
_16 = 3758153728B;
|
|
_17 = _16->CTRL;
|
|
_18 = 3758153728B;
|
|
_19 = _17 | 1;
|
|
_18->CTRL = _19;
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("dsb");
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__("isb");
|
|
# DEBUG BEGIN_STMT
|
|
sys_m7_cache_init ();
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Sys_GetCoreID ()
|
|
{
|
|
uint8 D.4418;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 1076232192B;
|
|
_2 = _1->CPXNUM;
|
|
_3 = (unsigned char) _2;
|
|
D.4418 = _3 & 3;
|
|
return D.4418;
|
|
|
|
}
|
|
|
|
|
|
default_interrupt_routine ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 2>; [INV]
|
|
|
|
}
|
|
|
|
|
|
startup_go_to_user_mode ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|