mirror of
https://github.com/Dev-KATECH/ADM.git
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1370 lines
42 KiB
Plaintext
1370 lines
42 KiB
Plaintext
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Marking local functions:
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Marking externally visible functions: SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00 Wdg_schm_read_msr
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Marking externally visible variables:
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Reclaiming functions:
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Reclaiming variables:
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Clearing address taken flags:
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Symbol table:
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Sys_GetCoreID/49 (Sys_GetCoreID) @05d8fa80
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25
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Calls:
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11) @05d8f540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (write)msr_WDG_EXCLUSIVE_AREA_11/22 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11) @05d8f2a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)msr_WDG_EXCLUSIVE_AREA_11/22 (write)msr_WDG_EXCLUSIVE_AREA_11/22 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10) @05d8f000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (write)msr_WDG_EXCLUSIVE_AREA_10/20 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10) @05d89b60
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)msr_WDG_EXCLUSIVE_AREA_10/20 (write)msr_WDG_EXCLUSIVE_AREA_10/20 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09) @05d89620
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (write)msr_WDG_EXCLUSIVE_AREA_09/18 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09) @05d890e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)msr_WDG_EXCLUSIVE_AREA_09/18 (write)msr_WDG_EXCLUSIVE_AREA_09/18 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08) @05d89d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (write)msr_WDG_EXCLUSIVE_AREA_08/16 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08) @05d89a80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)msr_WDG_EXCLUSIVE_AREA_08/16 (write)msr_WDG_EXCLUSIVE_AREA_08/16 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07) @05d897e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (write)msr_WDG_EXCLUSIVE_AREA_07/14 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07) @05d89540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)msr_WDG_EXCLUSIVE_AREA_07/14 (write)msr_WDG_EXCLUSIVE_AREA_07/14 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06) @05d892a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (write)msr_WDG_EXCLUSIVE_AREA_06/12 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06) @05d89000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)msr_WDG_EXCLUSIVE_AREA_06/12 (write)msr_WDG_EXCLUSIVE_AREA_06/12 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05) @05c97b60
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (write)msr_WDG_EXCLUSIVE_AREA_05/10 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05) @05c97620
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)msr_WDG_EXCLUSIVE_AREA_05/10 (write)msr_WDG_EXCLUSIVE_AREA_05/10 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04) @05c970e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (write)msr_WDG_EXCLUSIVE_AREA_04/8 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04) @05c97d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)msr_WDG_EXCLUSIVE_AREA_04/8 (write)msr_WDG_EXCLUSIVE_AREA_04/8 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03) @05c97a80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (write)msr_WDG_EXCLUSIVE_AREA_03/6 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03) @05c977e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)msr_WDG_EXCLUSIVE_AREA_03/6 (write)msr_WDG_EXCLUSIVE_AREA_03/6 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02) @05c97540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (write)msr_WDG_EXCLUSIVE_AREA_02/4 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02) @05c972a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)msr_WDG_EXCLUSIVE_AREA_02/4 (write)msr_WDG_EXCLUSIVE_AREA_02/4 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01) @05c97000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (write)msr_WDG_EXCLUSIVE_AREA_01/2 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01) @05c92a80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)msr_WDG_EXCLUSIVE_AREA_01/2 (write)msr_WDG_EXCLUSIVE_AREA_01/2 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00) @05c92ee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (write)msr_WDG_EXCLUSIVE_AREA_00/0 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00) @05c92c40
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)msr_WDG_EXCLUSIVE_AREA_00/0 (write)msr_WDG_EXCLUSIVE_AREA_00/0 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Wdg_schm_read_msr/24 Sys_GetCoreID/49
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Wdg_schm_read_msr/24 (Wdg_schm_read_msr) @05c929a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References:
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25
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Calls:
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reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (reentry_guard_WDG_EXCLUSIVE_AREA_11) @05c91558
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Type: variable definition analyzed
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Visibility: force_output prevailing_def_ironly
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References:
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Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)
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Availability: available
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Varpool flags:
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msr_WDG_EXCLUSIVE_AREA_11/22 (msr_WDG_EXCLUSIVE_AREA_11) @05c914c8
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Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (reentry_guard_WDG_EXCLUSIVE_AREA_10) @05c91438
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_10/20 (msr_WDG_EXCLUSIVE_AREA_10) @05c913a8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (reentry_guard_WDG_EXCLUSIVE_AREA_09) @05c91318
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_09/18 (msr_WDG_EXCLUSIVE_AREA_09) @05c91288
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (reentry_guard_WDG_EXCLUSIVE_AREA_08) @05c911f8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_08/16 (msr_WDG_EXCLUSIVE_AREA_08) @05c91168
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (reentry_guard_WDG_EXCLUSIVE_AREA_07) @05c910d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_07/14 (msr_WDG_EXCLUSIVE_AREA_07) @05c91048
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (reentry_guard_WDG_EXCLUSIVE_AREA_06) @05c8af78
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_06/12 (msr_WDG_EXCLUSIVE_AREA_06) @05c8aee8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (reentry_guard_WDG_EXCLUSIVE_AREA_05) @05c8ae58
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_05/10 (msr_WDG_EXCLUSIVE_AREA_05) @05c8adc8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (reentry_guard_WDG_EXCLUSIVE_AREA_04) @05c8ad38
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_04/8 (msr_WDG_EXCLUSIVE_AREA_04) @05c8aca8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (reentry_guard_WDG_EXCLUSIVE_AREA_03) @05c8ac18
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_03/6 (msr_WDG_EXCLUSIVE_AREA_03) @05c8ab88
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (reentry_guard_WDG_EXCLUSIVE_AREA_02) @05c8aaf8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_02/4 (msr_WDG_EXCLUSIVE_AREA_02) @05c8aa68
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (reentry_guard_WDG_EXCLUSIVE_AREA_01) @05c8a9d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_01/2 (msr_WDG_EXCLUSIVE_AREA_01) @05c8a948
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (reentry_guard_WDG_EXCLUSIVE_AREA_00) @05c8a8b8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_00/0 (msr_WDG_EXCLUSIVE_AREA_00) @05c8a828
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (write)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_11[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_10[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_09[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_08[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_07[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_06[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_05[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_04[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_03[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_02[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_01[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Wdg_schm_read_msr ();
|
|
msr_WDG_EXCLUSIVE_AREA_00[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Wdg_schm_read_msr ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 D.4253;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp);
|
|
# DEBUG BEGIN_STMT
|
|
D.4253 = reg_tmp;
|
|
return D.4253;
|
|
|
|
}
|
|
|
|
|