mirror of
https://github.com/Dev-KATECH/ADM.git
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1612 lines
54 KiB
Plaintext
1612 lines
54 KiB
Plaintext
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Reclaiming functions:
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Reclaiming variables:
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Clearing address taken flags:
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Symbol table:
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Sys_GetCoreID/49 (Sys_GetCoreID) @05e29a80
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (1073741824 (estimated locally),1.00 per call)
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Calls:
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11) @05e29540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (write)msr_WDG_EXCLUSIVE_AREA_11/22 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11) @05e292a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)msr_WDG_EXCLUSIVE_AREA_11/22 (write)msr_WDG_EXCLUSIVE_AREA_11/22 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (read)reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10) @05e29000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (write)msr_WDG_EXCLUSIVE_AREA_10/20 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10) @05e23b60
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)msr_WDG_EXCLUSIVE_AREA_10/20 (write)msr_WDG_EXCLUSIVE_AREA_10/20 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (read)reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09) @05e23620
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (write)msr_WDG_EXCLUSIVE_AREA_09/18 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09) @05e230e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)msr_WDG_EXCLUSIVE_AREA_09/18 (write)msr_WDG_EXCLUSIVE_AREA_09/18 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (read)reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08) @05e23d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (write)msr_WDG_EXCLUSIVE_AREA_08/16 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08) @05e23a80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)msr_WDG_EXCLUSIVE_AREA_08/16 (write)msr_WDG_EXCLUSIVE_AREA_08/16 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (read)reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07) @05e237e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (write)msr_WDG_EXCLUSIVE_AREA_07/14 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07) @05e23540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)msr_WDG_EXCLUSIVE_AREA_07/14 (write)msr_WDG_EXCLUSIVE_AREA_07/14 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (read)reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06) @05e232a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (write)msr_WDG_EXCLUSIVE_AREA_06/12 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06) @05e23000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)msr_WDG_EXCLUSIVE_AREA_06/12 (write)msr_WDG_EXCLUSIVE_AREA_06/12 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (read)reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05) @05d2fb60
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (write)msr_WDG_EXCLUSIVE_AREA_05/10 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05) @05d2f620
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)msr_WDG_EXCLUSIVE_AREA_05/10 (write)msr_WDG_EXCLUSIVE_AREA_05/10 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (read)reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04) @05d2f0e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (write)msr_WDG_EXCLUSIVE_AREA_04/8 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04) @05d2fd20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)msr_WDG_EXCLUSIVE_AREA_04/8 (write)msr_WDG_EXCLUSIVE_AREA_04/8 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (read)reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03) @05d2fa80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (write)msr_WDG_EXCLUSIVE_AREA_03/6 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03) @05d2f7e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)msr_WDG_EXCLUSIVE_AREA_03/6 (write)msr_WDG_EXCLUSIVE_AREA_03/6 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (read)reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02) @05d2f540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (write)msr_WDG_EXCLUSIVE_AREA_02/4 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02) @05d2f2a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)msr_WDG_EXCLUSIVE_AREA_02/4 (write)msr_WDG_EXCLUSIVE_AREA_02/4 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (read)reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01) @05d2f000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (write)msr_WDG_EXCLUSIVE_AREA_01/2 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01) @05d2aa80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)msr_WDG_EXCLUSIVE_AREA_01/2 (write)msr_WDG_EXCLUSIVE_AREA_01/2 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (read)reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00) @05d2aee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (write)msr_WDG_EXCLUSIVE_AREA_00/0 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00) @05d2ac40
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)msr_WDG_EXCLUSIVE_AREA_00/0 (write)msr_WDG_EXCLUSIVE_AREA_00/0 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (read)reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/49 (1073741824 (estimated locally),1.00 per call)
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Wdg_schm_read_msr/24 (Wdg_schm_read_msr) @05d2a9a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References:
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls:
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reentry_guard_WDG_EXCLUSIVE_AREA_11/23 (reentry_guard_WDG_EXCLUSIVE_AREA_11) @05d29558
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Type: variable definition analyzed
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Visibility: force_output prevailing_def_ironly
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References:
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Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_11/22 (msr_WDG_EXCLUSIVE_AREA_11) @05d294c8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11/47 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10/21 (reentry_guard_WDG_EXCLUSIVE_AREA_10) @05d29438
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_10/20 (msr_WDG_EXCLUSIVE_AREA_10) @05d293a8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10/45 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09/19 (reentry_guard_WDG_EXCLUSIVE_AREA_09) @05d29318
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_09/18 (msr_WDG_EXCLUSIVE_AREA_09) @05d29288
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09/43 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08/17 (reentry_guard_WDG_EXCLUSIVE_AREA_08) @05d291f8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_08/16 (msr_WDG_EXCLUSIVE_AREA_08) @05d29168
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08/41 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07/15 (reentry_guard_WDG_EXCLUSIVE_AREA_07) @05d290d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_07/14 (msr_WDG_EXCLUSIVE_AREA_07) @05d29048
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07/39 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06/13 (reentry_guard_WDG_EXCLUSIVE_AREA_06) @05d22f78
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_06/12 (msr_WDG_EXCLUSIVE_AREA_06) @05d22ee8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06/37 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06/38 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05/11 (reentry_guard_WDG_EXCLUSIVE_AREA_05) @05d22e58
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_05/10 (msr_WDG_EXCLUSIVE_AREA_05) @05d22dc8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05/35 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05/36 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04/9 (reentry_guard_WDG_EXCLUSIVE_AREA_04) @05d22d38
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_04/8 (msr_WDG_EXCLUSIVE_AREA_04) @05d22ca8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04/33 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04/34 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03/7 (reentry_guard_WDG_EXCLUSIVE_AREA_03) @05d22c18
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_03/6 (msr_WDG_EXCLUSIVE_AREA_03) @05d22b88
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03/31 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03/32 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02/5 (reentry_guard_WDG_EXCLUSIVE_AREA_02) @05d22af8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_02/4 (msr_WDG_EXCLUSIVE_AREA_02) @05d22a68
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02/29 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02/30 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01/3 (reentry_guard_WDG_EXCLUSIVE_AREA_01) @05d229d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_01/2 (msr_WDG_EXCLUSIVE_AREA_01) @05d22948
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01/27 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01/28 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00/1 (reentry_guard_WDG_EXCLUSIVE_AREA_00) @05d228b8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_WDG_EXCLUSIVE_AREA_00/0 (msr_WDG_EXCLUSIVE_AREA_00) @05d22828
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (read)SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00/25 (write)SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00/26 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Wdg_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_WDG_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Wdg_schm_read_msr ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_1);
|
|
# DEBUG reg_tmp => reg_tmp_1
|
|
# DEBUG BEGIN_STMT
|
|
return reg_tmp_1;
|
|
|
|
}
|
|
|
|
|