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ADM/GW/RTD/src/Clock_Ip_Specific.c
S2-CHICKEN 77297108b6 VCU C code first commit
2024-08-08 10:00:15 +09:00

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/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral :
* Dependencies : none
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
/**
* @file Clock_Ip_Specific.c
* @version 0.9.0
*
* @brief CLOCK driver implementations.
* @details CLOCK driver implementations.
*
* @addtogroup CLOCK_DRIVER Clock Ip Driver
* @{
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section Clock_Ip_Specific_c_REF_1
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor
* directives or comments. AUTOSAR imposes the specification of the sections in which certain parts
* of the driver must be placed.
*
* @section Clock_Ip_Specific_c_REF_2
* Violates MISRA 2012 Advisory Rule 4.8, This file includes the definition
* of types but does not use it. Header is common for all files
*
* @section Clock_Ip_Specific_c_REF_3
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object
* and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Clock_Ip_Specific_c_REF_4
* Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
* Function like macro are used to reduce code complexity
*
* @section Clock_Ip_Specific_c_REF_5
* Violates MISRA 2012 Advisory Rule 12.3, The comma operator should not be used.
* The comma is used to abstract the trusted call function and to determine when the return into user mode is needed.
*
* @section Clock_Ip_Specific_c_REF_6
* Violates MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with external linkage if
* they are referenced in only one translation unit.
* This error shouldn't be reported for static objects.
*
* @section Clock_Ip_Specific_c_REF_7
* Violates MISRA 2012 Required Rule 13.1, Initializer lists shall not contain persisten side effects.
* The initializer lists is used to access memory mapped registers.
*
* @section Clock_Ip_Specific_c_REF_8
* Violates MISRA 2012 Required Rule 18.4, The +, +- and operators should not be applied to an expression of pointer type.
* This is required to change the source address.
*
*/
#include <stdbool.h>
#include <stddef.h>
#if defined(S32K3XX)
#include "Clock_Ip_Private.h"
#if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
#define USER_MODE_REG_PROT_ENABLED (STD_ON)
#include "RegLockMacros.h"
#endif
#endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
/*==================================================================================================
SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define CLOCK_IP_SPECIFIC_VENDOR_ID_C 43
#define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C 4
#define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C 4
#define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C 0
#define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C 0
#define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C 9
#define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C 0
/*==================================================================================================
* FILE VERSION CHECKS
==================================================================================================*/
/* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same vendor */
#if (CLOCK_IP_SPECIFIC_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
#error "Clock_Ip_Specific.c and Clock_Ip_Private.h have different vendor ids"
#endif
/* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Autosar version */
#if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
(CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
(CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
)
#error "AutoSar Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
#endif
/* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Software version */
#if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
(CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
(CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
)
#error "Software Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
#endif
#if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if Clock_Ip_Specific.c file and RegLockMacros.h file are of the same Autosar version */
#if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
(CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
#error "AutoSar Version Numbers of Clock_Ip_Specific.c and RegLockMacros.h are different"
#endif
#endif
#endif
#endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
#define CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL 0U
#define BUFFER_NO_CLK 0U
#define BUFFER_FIRC 1U
#define BUFFER_SIRC 2U
#define BUFFER_FXOSC 3U
#define BUFFER_SXOSC 4U
#define BUFFER_PLL 5U
#define BUFFER_emacmiirx 6U
#define BUFFER_emacmiirmiitx 7U
#define BUFFER_CORE_FIRC 8U
#define BUFFER_AIPSPLAT_FIRC 9U
#define BUFFER_AIPSSLOW_FIRC 10U
#define BUFFER_HSE_FIRC 11U
#define BUFFER_DCM_FIRC 12U
#define BUFFER_LBIST_FIRC 13U
#define BUFFER_QSPIMEM_FIRC 14U
#define BUFFER_CLKOUTRUN_FIRC 15U
#define BUFFER_CLKOUTRUN_SIRC 16U
#define BUFFER_CLKOUTRUN_FXOSC 17U
#define BUFFER_CLKOUTRUN_SXOSC 18U
#define BUFFER_CLKOUTRUN_CORE_FIRC 19U
#define BUFFER_CLKOUTRUN_HSE_FIRC 20U
#define BUFFER_CLKOUTRUN_AIPSPLAT_FIRC 21U
#define BUFFER_CLKOUTRUN_AIPSSLOW_FIRC 22U
#define BUFFER_CLKOUTRUN_emacmiirx 23U
#define BUFFER_CLKOUTRUN_emacmiirmiitx 24U
#define BUFFER_PLLPOSTDIV_PLL 25U
#define BUFFER_PLLPHI0_PLLPOSTDIV_PLL 26U
#define BUFFER_PLLPHI1_PLLPOSTDIV_PLL 27U
#define BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL 28U
#define BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL 29U
#define BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL 30U
#define BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL 31U
#define BUFFER_DCM_PLLPHI0_PLLPOSTDIV_PLL 32U
#define BUFFER_LBIST_PLLPHI0_PLLPOSTDIV_PLL 33U
#define BUFFER_QSPIMEM_PLLPHI0_PLLPOSTDIV_PLL 34U
#define BUFFER_CLKOUTRUN_PLLPHI0_PLLPOSTDIV_PLL 35U
#define BUFFER_CLKOUTRUN_PLLPHI1_PLLPOSTDIV_PLL 36U
#define BUFFER_CLKOUTRUN_CORE_PLLPHI0_PLLPOSTDIV_PLL 37U
#define BUFFER_CLKOUTRUN_HSE_PLLPHI0_PLLPOSTDIV_PLL 38U
#define BUFFER_CLKOUTRUN_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL 39U
#define BUFFER_CLKOUTRUN_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL 40U
#define BUFFER_FREQS_NO 41U
/* Pcfs settings that are dependent on device */
#define A_MAX_SIZE 6U
typedef struct {
uint32 input1, input2, input3, input4, input5;
uint32 aux1, aux2, aux3, aux4, aux5;
uint32 output;
} tCalcFreqDataType;
#ifdef FEATURE_CLOCK_IP_HAS_FLASH_WAIT_STATES
/* Clock start ram section code */
#define MCU_START_SEC_RAMCODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static void CodeInRam_SetFlashWaitStates(void);
/* Clock start ram section code */
#define MCU_STOP_SEC_RAMCODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#endif /* FEATURE_CLOCK_IP_HAS_FLASH_WAIT_STATES */
/* microA per MHz */
#define DYNAMIC_IDD_CHANGE 2360U
#define NO_CALLBACK 0U
#define DIV_TRIGGER_CMU 1U
#define HWMUX_PCFS 1U
#define FIRCOSC 1U
#define SLOW_XOSC 1U
#define PLL_MOD 1U
#define GATE 1U
#define PLL_POSTDIV 2U
#define SIRCOSC 2U
#define FAST_XOSC_CMU 2U
#define PCFS_PLL_OUT 3U
#define PLL_OUT 4U
#define DIV_TRIGGER 5U
#define DIV_PHASE_TRIGGER 6U
#define SWMUX_DIV 7U
#define HWMUX_DIV 8U
/* Clock start constant section data */
#define MCU_START_SEC_CONST_8
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
const uint8 dividerCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* DIV_TRIGGER_CMU */
PLL_PLLDV_ODIV2_OUTPUT, /* PLL_POSTDIV */
PLL_PLL0DIV_DE_DIV_OUTPUT, /* PCFS_PLL_OUT */
PLL_PLL0DIV_DE_DIV_OUTPUT, /* PLL_OUT */
CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* DIV_TRIGGER */
CGM_X_DE_DIV_STAT_WITH_PHASE, /* DIV_PHASE_TRIGGER */
CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* SWMUX_DIV */
CGM_X_DE_DIV_STAT_WITHOUT_PHASE, /* HWMUX_DIV */
};
const uint8 dividertriggerCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* DIV_TRIGGER_CMU */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* DIV_TRIGGER */
CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT, /* DIV_PHASE_TRIGGER */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 xoscCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
SXOSC_OSCON_EOCV, /* SLOW_XOSC */
FXOSC_OSCON_BYP_EOCV_GM_SEL, /* FAST_XOSC_CMU */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 ircoscCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
FIRC_STDBY_ENABLE, /* FIRCOSC */
SIRC_STDBY_ENABLE, /* SIRCOSC */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 gateCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
MC_ME_PARTITION_COFB_ENABLE_REQUEST, /* GATE */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 fractional_dividerCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 pllCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE,/* PLL_MOD */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 selectorCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
CGM_X_CSC_CSS_CLK_SW_RAMPDOWN_RAMPUP_SWIP, /* HWMUX_PCFS */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
CGM_X_CSC_CSS_CS_GRIP, /* SWMUX_DIV */
CGM_X_CSC_CSS_CLK_SW_SWIP, /* HWMUX_DIV */
};
const uint8 pcfsCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS, /* PCFS_PLL_OUT */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
const uint8 cmuCallbackIndex[ALL_CALLBACKS_COUNT] = {
NO_CALLBACK, /* No callback */
CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* DIV_TRIGGER_CMU */
CMU_FC_FCE_REF_CNT_LFREF_HFREF, /* FAST_XOSC_CMU */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
NO_CALLBACK, /* No callback */
};
/* Clock features mapping */
const uint8 clockFeatures[CLOCK_NAMES_NO][CLOCK_FEATURES_NO] =
/* \
***************************************************************************************************************************************************************************** \
********************************* ******** ************* ********* DIVIDER **** C P ****** ************************************ * ****** \
********************************* ******** C ************* ********* INDEX **** O C ****** ************************************ C * C ****** \
********************************* I ******** A ************* ********* **** L F ****** ************************************ M * M ****** \
********************************* N ******** L ************* INTERFACE ********* or **** L S ****** CLK ************************************ U * U ****** \
********************************* S ******** L ************* CLOCK ********* **** E ****** ENABLE ************************************ * ****** \
********************************* T ******** B ************* ********* PCTL **** C H ****** REQ ************************************ I * S ****** \
********************************* A ******** A ************* or ********* INDEX **** T W ****** ************************************ N * W ****** \
********************************* N ******** C ************* ********* **** I ****** PCFS ************************************ S * ****** \
********************************* C ******** K ************* SELECTOR ********* or **** O I ****** SW ************************************ T * I ****** \
********************************* E ******** ************* INDEX ********* **** N N ****** INDEX ************************************ A * N ****** \
********************************* ******** ************* ********* PCC **** D ****** ************************************ N * D ****** \
********************************* ******** ************* ********* INDEX **** I E ****** ************************************ C * E ****** \
********************************* ******** ************* ********* **** D X ****** ************************************ E * X ****** \
********************************* ******** ************* ********* PARTITION **** ****** ************************************ * ****** \
********************************* ******** ************* ********* INDEX **** ****** ************************************ * ****** \
******************************************************************************************************************************************************************************/
{
/* FIRC_CLK clock */ {0U, NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U}, /* FIRC_CLK clock */
/* FIRC_STANDBY_CLK clock */ {0U, FIRCOSC, 0U, 0U, 0U, 0U, 0U, 0U}, /* FIRC_STANDBY_CLK clock */
/* SIRC_CLK clock */ {0U, NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_CLK clock */
/* SIRC_STANDBY_CLK clock */ {0U, SIRCOSC, 0U, 0U, 0U, 0U, 0U, 0U}, /* SIRC_STANDBY_CLK clock */
/* FXOSC_CLK clock */ {0U, FAST_XOSC_CMU, 0U, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ53_SHIFT, 0U, 0U}, /* FXOSC_CLK clock */
/* SXOSC_CLK clock */ {1U, SLOW_XOSC, 0U, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ51_SHIFT, 0U, 0U}, /* SXOSC_CLK clock */
/* PLL_CLK clock */ {0U, PLL_MOD, 0U, 0U, 0U, 0U, 0U, 0U}, /* PLL_CLK clock */
/* PLL_POSTDIV_CLK clock */ {0U, PLL_POSTDIV, 0U, 0U, 0U, 0U, 0U, 0U}, /* PLL_POSTDIV_CLK clock */
/* PLL_PHI0 clock */ {0U, PCFS_PLL_OUT, 0U, 0U, 7U, PCFS_PLLPHI0, 0U, 0U}, /* PLL_PHI0 clock */
/* PLL_PHI1 clock */ {0U, PLL_OUT, 0U, 1U, 0U, 0U, 0U, 0U}, /* PLL_PHI1 clock */
/* emac_mii_rx clock */ {0U, NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U}, /* emac_mii_rx clock */
/* emac_mii_rmii_tx clock */ {0U, NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U}, /* emac_mii_rmii_tx clock */
/* SCS_CLK clock */ {0U, HWMUX_PCFS, 0U, 0U, 0U, NO_TRIGGER, 0U, 0U}, /* SCS_CLK clock */
/* CORE_CLK clock */ {0U, DIV_TRIGGER_CMU, 0U, 0U, 0U, TRIGGER, 1U, 1U}, /* CORE_CLK clock */
/* AIPS_PLAT_CLK clock */ {0U, DIV_TRIGGER_CMU, 0U, 1U, 0U, TRIGGER, 2U, 2U}, /* AIPS_PLAT_CLK clock */
/* AIPS_SLOW_CLK clock */ {0U, DIV_TRIGGER, 0U, 2U, 0U, TRIGGER, 0U, 0U}, /* AIPS_SLOW_CLK clock */
/* HSE_CLK clock */ {0U, DIV_TRIGGER_CMU, 0U, 3U, 0U, TRIGGER, 3U, 3U}, /* HSE_CLK clock */
/* DCM_CLK clock */ {0U, DIV_TRIGGER, 0U, 4U, 0U, TRIGGER, 0U, 0U}, /* DCM_CLK clock */
/* LBIST_CLK clock */ {0U, DIV_PHASE_TRIGGER, 0U, 5U, 0U, TRIGGER, 0U, 0U}, /* LBIST_CLK clock */
/* QSPI_MEM_CLK clock */ {0U, DIV_TRIGGER, 0U, 6U, 0U, TRIGGER, 0U, 0U}, /* QSPI_MEM_CLK clock */
/* CLKOUT_RUN_CLK clock */ {0U, SWMUX_DIV, 6U, 0U, 0U, NO_TRIGGER, 0U, 0U}, /* CLKOUT_RUN_CLK clock */
/* THE_LAST_PRODUCER_CLK */ {0U, NO_CALLBACK, 0U, 0U, 0U, 0U, 0U, 0U}, /* THE_LAST_PRODUCER_CLK */
/* ADC0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ40_SHIFT, 0U, 0U}, /* ADC0_CLK clock */
/* ADC1_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ41_SHIFT, 0U, 0U}, /* ADC1_CLK clock */
/* ADC2_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ42_SHIFT, 0U, 0U}, /* ADC2_CLK clock */
/* BCTU0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ33_SHIFT, 0U, 0U}, /* BCTU0_CLK clock */
/* CLKOUT_STANDBY_CLK clock */ {0U, SWMUX_DIV, 5U, 0U, 0U, NO_TRIGGER, 0U, 0U}, /* CLKOUT_STANDBY_CLK clock */
/* CMP0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ92_SHIFT, 0U, 0U}, /* CMP0_CLK clock */
/* CMP1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ93_SHIFT, 0U, 0U}, /* CMP1_CLK clock */
/* CMP2_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ58_SHIFT, 0U, 0U}, /* CMP2_CLK clock */
/* CRC0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 3U, MC_ME_PRTN1_COFB3_CLKEN_REQ96_SHIFT, 0U, 0U}, /* CRC0_CLK clock */
/* DCM0_CLK clock */ {0U, NO_CALLBACK, (uint8)DCM_CLK, 0U, 0U, 0U, 0U, 0U}, /* DCM0_CLK clock */
/* DMAMUX0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ32_SHIFT, 0U, 0U}, /* DMAMUX0_CLK clock */
/* DMAMUX1_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ33_SHIFT, 0U, 0U}, /* DMAMUX1_CLK clock */
/* EDMA0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ3_SHIFT, 0U, 0U}, /* EDMA0_CLK clock */
/* EDMA0_TCD0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ4_SHIFT, 0U, 0U}, /* EDMA0_TCD0_CLK clock */
/* EDMA0_TCD10_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ14_SHIFT, 0U, 0U}, /* EDMA0_TCD10_CLK clock */
/* EDMA0_TCD11_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ15_SHIFT, 0U, 0U}, /* EDMA0_TCD11_CLK clock */
/* EDMA0_TCD12_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ4_SHIFT, 0U, 0U}, /* EDMA0_TCD12_CLK clock */
/* EDMA0_TCD13_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ5_SHIFT, 0U, 0U}, /* EDMA0_TCD13_CLK clock */
/* EDMA0_TCD14_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ6_SHIFT, 0U, 0U}, /* EDMA0_TCD14_CLK clock */
/* EDMA0_TCD15_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ7_SHIFT, 0U, 0U}, /* EDMA0_TCD15_CLK clock */
/* EDMA0_TCD16_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ8_SHIFT, 0U, 0U}, /* EDMA0_TCD16_CLK clock */
/* EDMA0_TCD17_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ9_SHIFT, 0U, 0U}, /* EDMA0_TCD17_CLK clock */
/* EDMA0_TCD18_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ10_SHIFT, 0U, 0U}, /* EDMA0_TCD18_CLK clock */
/* EDMA0_TCD19_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ11_SHIFT, 0U, 0U}, /* EDMA0_TCD19_CLK clock */
/* EDMA0_TCD1_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ5_SHIFT, 0U, 0U}, /* EDMA0_TCD1_CLK clock */
/* EDMA0_TCD20_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ12_SHIFT, 0U, 0U}, /* EDMA0_TCD20_CLK clock */
/* EDMA0_TCD21_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ13_SHIFT, 0U, 0U}, /* EDMA0_TCD21_CLK clock */
/* EDMA0_TCD22_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ14_SHIFT, 0U, 0U}, /* EDMA0_TCD22_CLK clock */
/* EDMA0_TCD23_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ15_SHIFT, 0U, 0U}, /* EDMA0_TCD23_CLK clock */
/* EDMA0_TCD24_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ16_SHIFT, 0U, 0U}, /* EDMA0_TCD24_CLK clock */
/* EDMA0_TCD25_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ17_SHIFT, 0U, 0U}, /* EDMA0_TCD25_CLK clock */
/* EDMA0_TCD26_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ18_SHIFT, 0U, 0U}, /* EDMA0_TCD26_CLK clock */
/* EDMA0_TCD27_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ19_SHIFT, 0U, 0U}, /* EDMA0_TCD27_CLK clock */
/* EDMA0_TCD28_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ20_SHIFT, 0U, 0U}, /* EDMA0_TCD28_CLK clock */
/* EDMA0_TCD29_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ21_SHIFT, 0U, 0U}, /* EDMA0_TCD29_CLK clock */
/* EDMA0_TCD2_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ6_SHIFT, 0U, 0U}, /* EDMA0_TCD2_CLK clock */
/* EDMA0_TCD30_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ22_SHIFT, 0U, 0U}, /* EDMA0_TCD30_CLK clock */
/* EDMA0_TCD31_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ23_SHIFT, 0U, 0U}, /* EDMA0_TCD31_CLK clock */
/* EDMA0_TCD3_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ7_SHIFT, 0U, 0U}, /* EDMA0_TCD3_CLK clock */
/* EDMA0_TCD4_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ8_SHIFT, 0U, 0U}, /* EDMA0_TCD4_CLK clock */
/* EDMA0_TCD5_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ9_SHIFT, 0U, 0U}, /* EDMA0_TCD5_CLK clock */
/* EDMA0_TCD6_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ10_SHIFT, 0U, 0U}, /* EDMA0_TCD6_CLK clock */
/* EDMA0_TCD7_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ11_SHIFT, 0U, 0U}, /* EDMA0_TCD7_CLK clock */
/* EDMA0_TCD8_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ12_SHIFT, 0U, 0U}, /* EDMA0_TCD8_CLK clock */
/* EDMA0_TCD9_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ13_SHIFT, 0U, 0U}, /* EDMA0_TCD9_CLK clock */
/* EIM0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ22_SHIFT, 0U, 0U}, /* EIM0_CLK clock */
/* EMAC_RX_CLK clock */ {0U, HWMUX_DIV, 7U, 0U, 0U, 0U, 0U, 0U}, /* EMAC_RX_CLK clock */
/* EMAC0_RX_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT, 0U, 0U}, /* EMAC0_RX_CLK clock */
/* EMAC_TS_CLK clock */ {0U, HWMUX_DIV, 9U, 0U, 0U, 0U, 0U, 0U}, /* EMAC_TS_CLK clock */
/* EMAC0_TS_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT, 0U, 0U}, /* EMAC0_TS_CLK clock */
/* EMAC_TX_CLK clock */ {0U, HWMUX_DIV, 8U, 0U, 0U, 0U, 0U, 0U}, /* EMAC_TX_CLK clock */
/* EMAC0_TX_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ32_SHIFT, 0U, 0U}, /* EMAC0_TX_CLK clock */
/* EMIOS0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ34_SHIFT, 0U, 0U}, /* EMIOS0_CLK clock */
/* EMIOS1_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ35_SHIFT, 0U, 0U}, /* EMIOS1_CLK clock */
/* EMIOS2_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ36_SHIFT, 0U, 0U}, /* EMIOS2_CLK clock */
/* ERM0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ23_SHIFT, 0U, 0U}, /* ERM0_CLK clock */
/* FLASH0_CLK clock */ {0U, NO_CALLBACK, (uint8)AIPS_SLOW_CLK, 0U, 0U, 0U, 0U, 0U}, /* FLASH0_CLK clock */
/* FLEXCANA_CLK clock */ {0U, HWMUX_DIV, 3U, 0U, 0U, 0U, 0U, 0U}, /* FLEXCANA_CLK clock */
/* FLEXCAN0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ65_SHIFT, 0U, 0U}, /* FLEXCAN0_CLK clock */
/* FLEXCAN1_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ66_SHIFT, 0U, 0U}, /* FLEXCAN1_CLK clock */
/* FLEXCAN2_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ67_SHIFT, 0U, 0U}, /* FLEXCAN2_CLK clock */
/* FLEXCANB_CLK clock */ {0U, HWMUX_DIV, 4U, 0U, 0U, 0U, 0U, 0U}, /* FLEXCANB_CLK clock */
/* FLEXCAN3_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ68_SHIFT, 0U, 0U}, /* FLEXCAN3_CLK clock */
/* FLEXCAN4_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ69_SHIFT, 0U, 0U}, /* FLEXCAN4_CLK clock */
/* FLEXCAN5_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ70_SHIFT, 0U, 0U}, /* FLEXCAN5_CLK clock */
/* FLEXIO0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ73_SHIFT, 0U, 0U}, /* FLEXIO0_CLK clock */
/* INTM_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ31_SHIFT, 0U, 0U}, /* INTM_CLK clock */
/* LCU0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ38_SHIFT, 0U, 0U}, /* LCU0_CLK clock */
/* LCU1_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ39_SHIFT, 0U, 0U}, /* LCU1_CLK clock */
/* LPI2C0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ84_SHIFT, 0U, 0U}, /* LPI2C0_CLK clock */
/* LPI2C1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ85_SHIFT, 0U, 0U}, /* LPI2C1_CLK clock */
/* LPSPI0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ86_SHIFT, 0U, 0U}, /* LPSPI0_CLK clock */
/* LPSPI1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ87_SHIFT, 0U, 0U}, /* LPSPI1_CLK clock */
/* LPSPI2_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ88_SHIFT, 0U, 0U}, /* LPSPI2_CLK clock */
/* LPSPI3_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ89_SHIFT, 0U, 0U}, /* LPSPI3_CLK clock */
/* LPSPI4_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ47_SHIFT, 0U, 0U}, /* LPSPI4_CLK clock */
/* LPSPI5_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ48_SHIFT, 0U, 0U}, /* LPSPI5_CLK clock */
/* LPUART0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ74_SHIFT, 0U, 0U}, /* LPUART0_CLK clock */
/* LPUART10_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ37_SHIFT, 0U, 0U}, /* LPUART10_CLK clock */
/* LPUART11_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ38_SHIFT, 0U, 0U}, /* LPUART11_CLK clock */
/* LPUART12_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ39_SHIFT, 0U, 0U}, /* LPUART12_CLK clock */
/* LPUART13_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ40_SHIFT, 0U, 0U}, /* LPUART13_CLK clock */
/* LPUART14_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ41_SHIFT, 0U, 0U}, /* LPUART14_CLK clock */
/* LPUART15_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ42_SHIFT, 0U, 0U}, /* LPUART15_CLK clock */
/* LPUART1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ75_SHIFT, 0U, 0U}, /* LPUART1_CLK clock */
/* LPUART2_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ76_SHIFT, 0U, 0U}, /* LPUART2_CLK clock */
/* LPUART3_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ77_SHIFT, 0U, 0U}, /* LPUART3_CLK clock */
/* LPUART4_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ78_SHIFT, 0U, 0U}, /* LPUART4_CLK clock */
/* LPUART5_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ79_SHIFT, 0U, 0U}, /* LPUART5_CLK clock */
/* LPUART6_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ80_SHIFT, 0U, 0U}, /* LPUART6_CLK clock */
/* LPUART7_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ81_SHIFT, 0U, 0U}, /* LPUART7_CLK clock */
/* LPUART8_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ35_SHIFT, 0U, 0U}, /* LPUART8_CLK clock */
/* LPUART9_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ36_SHIFT, 0U, 0U}, /* LPUART9_CLK clock */
/* MSCM_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ24_SHIFT, 0U, 0U}, /* MSCM_CLK clock */
/* MUA_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ46_SHIFT, 0U, 0U}, /* MUA_CLK clock */
/* MUB_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ47_SHIFT, 0U, 0U}, /* MUB_CLK clock */
/* PIT0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ44_SHIFT, 0U, 0U}, /* PIT0_CLK clock */
/* PIT1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ45_SHIFT, 0U, 0U}, /* PIT1_CLK clock */
/* PIT2_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ63_SHIFT, 0U, 0U}, /* PIT2_CLK clock */
/* QSPI0_RAM_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT, 0U, 0U}, /* QSPI0_RAM_CLK clock */
/* QSPI_SFCK_CLK clock */ {0U, HWMUX_DIV, 10U, 0U, 0U, 0U, 0U, 0U}, /* QSPI_SFCK_CLK clock */
/* QSPI0_SFCK_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT, 0U, 0U}, /* QSPI0_SFCK_CLK clock */
/* QSPI0_TX_MEM_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ51_SHIFT, 0U, 0U}, /* QSPI0_TX_MEM_CLK clock */
/* RTC_CLK clock */ {0U, NO_CALLBACK, 12U, 0U, 0U, 0U, 0U, 0U}, /* RTC_CLK clock */
/* RTC0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ34_SHIFT, 0U, 0U}, /* RTC0_CLK clock */
/* SAI0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ91_SHIFT, 0U, 0U}, /* SAI0_CLK clock */
/* SAI1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ55_SHIFT, 0U, 0U}, /* SAI1_CLK clock */
/* SEMA42_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ24_SHIFT, 0U, 0U}, /* SEMA42_CLK clock */
/* SIUL0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ42_SHIFT, 0U, 0U}, /* SIUL0_CLK clock */
/* STCU0_CLK clock */ {0U, NO_CALLBACK, (uint8)AIPS_SLOW_CLK, 0U, 0U, 0U, 0U, 0U}, /* STCU0_CLK clock */
/* STMA_CLK clock */ {0U, HWMUX_DIV, 1U, 0U, 0U, 0U, 0U, 0U}, /* STMA_CLK clock */
/* STM0_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ29_SHIFT, 0U, 0U}, /* STM0_CLK clock */
#if defined(FEATURE_CLOCK_IP_HAS_STMB_CLK)
/* STMB_CLK clock */ {0U, HWMUX_DIV, 2U, 0U, 0U, 0U, 0U, 0U}, /* STMB_CLK clock */
#endif
#if defined(FEATURE_CLOCK_IP_HAS_STM1_CLK)
/* STM1_CLK clock */ {0U, GATE, (uint8)AIPS_PLAT_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ29_SHIFT, 0U, 0U}, /* STM1_CLK clock */
#endif
/* SWT0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 0U, MC_ME_PRTN1_COFB0_CLKEN_REQ28_SHIFT, 0U, 0U}, /* SWT0_CLK clock */
/* SWT1_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 2U, 0U, MC_ME_PRTN2_COFB0_CLKEN_REQ27_SHIFT, 0U, 0U}, /* SWT1_CLK clock */
/* TCM_CM7_0_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ62_SHIFT, 0U, 0U}, /* TCM_CM7_0_CLK clock */
/* TCM_CM7_1_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 2U, 1U, MC_ME_PRTN2_COFB1_CLKEN_REQ63_SHIFT, 0U, 0U}, /* TCM_CM7_1_CLK clock */
/* TEMPSENSE_CLK clock */ {0U, GATE, (uint8)CORE_CLK, 1U, 2U, MC_ME_PRTN1_COFB2_CLKEN_REQ95_SHIFT, 0U, 0U}, /* TEMPSENSE_CLK clock */
/* TRACE_CLK clock */ {0U, SWMUX_DIV, 11U, 0U, 0U, NO_TRIGGER, 0U, 0U}, /* TRACE_CLK clock */
/* TRGMUX0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 0U, 1U, MC_ME_PRTN0_COFB1_CLKEN_REQ32_SHIFT, 0U, 0U}, /* TRGMUX0_CLK clock */
/* TSENSE0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ49_SHIFT, 0U, 0U}, /* TSENSE0_CLK clock */
/* WKPU0_CLK clock */ {0U, GATE, (uint8)AIPS_SLOW_CLK, 1U, 1U, MC_ME_PRTN1_COFB1_CLKEN_REQ45_SHIFT, 0U, 0U}, /* WKPU0_CLK clock */
};
/* Clock stop constant section data */
#define MCU_STOP_SEC_CONST_8
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start constant section data */
#define MCU_START_SEC_CONST_16
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/*!
* @brief Converts a clock name to a selector entry hardware value
*/
const uint16 selectorEntry_hardwareValue[CLOCK_PRODUCERS_NO] = {
0U, /*!< FIRC_CLK_CLK clock source */
0U, /*!< FIRC_STANDBY_CLK clock source */
1U, /*!< SIRC_CLK_CLK clock source */
1U, /*!< SIRC_STANDBY_CLK clock source */
2U, /*!< FXOSC_CLK_CLK clock source */
4U, /*!< SXOSC_CLK_CLK clock source */
0U, /*!< PLL_VCO_CLK clock source */
0U, /*!< PLL_POSTVDIV_CLK clock source */
8U, /*!< PLL_PHI0_CLK clock source */
9U, /*!< PLL_PHI1_CLK clock source */
25U, /*!< emac_mii_rx_CLK external source */
24U, /*!< emac_mii_rmii_tx_CLK external source */
0U, /*!< SCS_CLK common clock */
16U, /*!< CORE_CLK common clock */
22U, /*!< AIPS_PLAT_CLK common clock */
23U, /*!< AIPS_SLOW_CLK common clock */
19U, /*!< HSE_CLK common clock */
0U, /*!< DCM_CLK common clock */
0U, /*!< LBIST_CLK common clock */
0U, /*!< QSPI_MEM_CLK common clock */
0U, /*!< CLKOUT_RUN_CLK common clock */
};
/* Clock stop constant section data */
#define MCU_STOP_SEC_CONST_16
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start constant section data */
#define MCU_START_SEC_CONST_32
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static const uint32 enableDisableMask[2U] = {0U,0xFFFFFFFFU};
/* Clock stop constant section data */
#define MCU_STOP_SEC_CONST_32
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start constant section data */
#define MCU_START_SEC_CONST_UNSPECIFIED
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
volatile cgmMux_Type* const cgm[MC_CGM_instances_count][MC_CGM_muxs_count] =
{
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_0_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_1_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_2_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_3_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_4_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_5_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_6_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_7_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_8_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_9_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_10_CSC) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmMux_Type*)( &(MC_CGM->MUX_11_CSC) ),
},
};
volatile cgmPcfs_Type* const cgmPcfs[MC_CGM_instances_count] =
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile cgmPcfs_Type*)( &(MC_CGM->PCFS_SDUR) ),
};
volatile ExtOSC_Type* const xosc[XOSC_INSTANCES_ARRAY_SIZE] =
{
(volatile ExtOSC_Type*)FXOSC,
(volatile ExtOSC_Type*)SXOSC,
};
volatile PLL_Type* const pll[PLL_INSTANCES_ARRAY_SIZE] =
{
(volatile PLL_Type*)PLL,
};
volatile ClockMonitor_Type* const cmu[CMU_INSTANCES_ARRAY_SIZE] =
{
(volatile ClockMonitor_Type*)CMU_0,
(volatile ClockMonitor_Type*)CMU_3,
(volatile ClockMonitor_Type*)CMU_4,
(volatile ClockMonitor_Type*)CMU_5
};
volatile setMcmePartition_Type* const mcmeSetPartitions[MC_ME_partitions_count] =
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile setMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN0_COFB1_CLKEN)) - 4U),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile setMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN1_COFB0_CLKEN)) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile setMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN2_COFB0_CLKEN)) ),
};
volatile const getMcmePartition_Type* const mcmeGetPartitions[MC_ME_partitions_count] =
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile const getMcmePartition_Type*)( ((volatile const uint8*)&(MC_ME->PRTN0_COFB1_STAT)) - 4U),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile const getMcmePartition_Type*)( ((volatile const uint8*)&(MC_ME->PRTN1_COFB0_STAT)) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile const getMcmePartition_Type*)( ((volatile const uint8*)&(MC_ME->PRTN2_COFB0_STAT)) ),
};
volatile triggerMcmePartition_Type* const mcmeTriggerPartitions[MC_ME_partitions_count] =
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile triggerMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN0_PCONF)) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile triggerMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN1_PCONF)) ),
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 A conversion should not be performed between a pointer to object and an integer type.
*/
/**
* @violates @ref Clock_Ip_Specific_c_REF_7 Initializer lists shall not contain persisten side effects.
*/
(volatile triggerMcmePartition_Type*)( ((volatile uint8*)&(MC_ME->PRTN2_PCONF)) ),
};
const clock_name_source_type_t clockName_sourceType[CLOCK_PRODUCERS_NO] = {
IRCOSC_TYPE, /*!< FIRC_CLK */
IRCOSC_TYPE, /*!< FIRC_STANDBY_CLK clock source */
IRCOSC_TYPE, /*!< SIRC_CLK */
IRCOSC_TYPE, /*!< SIRC_STANDBY_CLK clock source */
XOSC_TYPE, /*!< FXOSC_CLK */
XOSC_TYPE, /*!< SXOSC_CLK */
PLL_TYPE, /*!< PLL_CLK */
PLL_TYPE, /*!< PLL_POSTDIV_CLK */
PLL_TYPE, /*!< PLL_PHI0_CLK */
PLL_TYPE, /*!< PLL_PHI1_CLK */
EXT_CLK_TYPE, /*!< EMAC_MII_RX_CLK */
EXT_CLK_TYPE, /*!< EMAC_MII_RMII_TX_CLK */
UKNOWN_TYPE, /*!< SCS_CLK */
UKNOWN_TYPE, /*!< CORE_CLK */
UKNOWN_TYPE, /*!< AIPS_PLAT_CLK */
UKNOWN_TYPE, /*!< AIPS_SLOW_CLK */
UKNOWN_TYPE, /*!< HSE_CLK */
UKNOWN_TYPE, /*!< DCM_CLK */
UKNOWN_TYPE, /*!< LBIST_CLK */
UKNOWN_TYPE, /*!< QSPI_MEM_CLK */
UKNOWN_TYPE, /*!< CLKOUT_RUN_CLK */
};
/*!
* @brief Converts hardware value of a selector entry to clock name
*/
static const Clock_Ip_NameType hardwareValue_selectorEntry[SELECTOR_HARDWARE_VALUES_NO] = {
FIRC_CLK, /* clock name for 0 hardware value */
SIRC_CLK, /* clock name for 1 hardware value */
FXOSC_CLK, /* clock name for 2 hardware value */
RESERVED_CLK, /* clock name for 3 hardware value */
SXOSC_CLK, /* clock name for 4 hardware value */
RESERVED_CLK, /* clock name for 5 hardware value */
RESERVED_CLK, /* clock name for 6 hardware value */
RESERVED_CLK, /* clock name for 7 hardware value */
PLL_PHI0_CLK, /* clock name for 8 hardware value */
PLL_PHI1_CLK, /* clock name for 9 hardware value */
RESERVED_CLK, /* clock name for 10 hardware value */
RESERVED_CLK, /* clock name for 11 hardware value */
RESERVED_CLK, /* clock name for 12 hardware value */
RESERVED_CLK, /* clock name for 13 hardware value */
RESERVED_CLK, /* clock name for 14 hardware value */
RESERVED_CLK, /* clock name for 15 hardware value */
CORE_CLK, /* clock name for 16 hardware value */
RESERVED_CLK, /* clock name for 17 hardware value */
RESERVED_CLK, /* clock name for 18 hardware value */
HSE_CLK, /* clock name for 19 hardware value */
RESERVED_CLK, /* clock name for 20 hardware value */
RESERVED_CLK, /* clock name for 21 hardware value */
AIPS_PLAT_CLK, /* clock name for 22 hardware value */
AIPS_SLOW_CLK, /* clock name for 23 hardware value */
EMAC_MII_RMII_TX_CLK, /* clock name for 24 hardware value */
EMAC_MII_RX_CLK, /* clock name for 25 hardware value */
RESERVED_CLK, /* clock name for 26 hardware value */
RESERVED_CLK, /* clock name for 27 hardware value */
RESERVED_CLK, /* clock name for 28 hardware value */
RESERVED_CLK, /* clock name for 29 hardware value */
RESERVED_CLK, /* clock name for 30 hardware value */
RESERVED_CLK, /* clock name for 31 hardware value */
};
const clock_element_state_t selectorEntryIndex[SELECTOR_HARDWARE_VALUES_NO] =
{
SELECTOR_ENTRY_1, /* FIRC_CLK - 0 hardware value */
SELECTOR_ENTRY_3, /* SIRC_CLK - 1 hardware value */
SELECTOR_ENTRY_4, /* FXOSC_CLK - 2 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 3 hardware value */
SELECTOR_ENTRY_5, /* SXOSC_CLK - 4 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 5 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 6 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 7 hardware value */
SELECTOR_ENTRY_2, /* PLL_PHI0_CLK - 8 hardware value */
SELECTOR_ENTRY_6, /* PLL_PHI1_CLK - 9 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 10 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 11 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 12 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 13 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 14 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 15 hardware value */
SELECTOR_ENTRY_7, /* CORE_CLK - 16 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 7 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 18 hardware value */
SELECTOR_ENTRY_8, /* HSE_CLK - 19 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 20 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 21 hardware value */
SELECTOR_ENTRY_9, /* AIPS_PLAT_CLK - 22 hardware value */
SELECTOR_ENTRY_10, /* AIPS_SLOW_CLK - 23 hardware value */
SELECTOR_ENTRY_12, /* EMAC_RMII_TX_CLK 24 hardware value */
SELECTOR_ENTRY_11, /* EMAC_RX_CLK - 25 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 26 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 27 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 28 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 29 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 30 hardware value */
DISABLED_CLOCK, /* RESERVED_CLK - 31 hardware value */
};
const Clock_Ip_NameType HwPllName[NUMBER_OF_HARDWARE_PLL] =
{
PLL_CLK /* PLL_CLK clock */
};
/* Clock stop constant section data */
#define MCU_STOP_SEC_CONST_UNSPECIFIED
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start uninitialized shared section data */
#define MCU_START_SEC_VAR_NO_INIT_32_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static uint32 bufferFreqs[BUFFER_FREQS_NO];
/* Clock stop uninitialized shared section data */
#define MCU_STOP_SEC_VAR_NO_INIT_32_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start uninitialized shared section data */
#define MCU_START_SEC_VAR_NO_INIT_8_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static uint8 freqPointers[CLOCK_PRODUCERS_NO + 1U];
/* Clock stop uninitialized shared section data */
#define MCU_STOP_SEC_VAR_NO_INIT_8_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start uninitialized shared section data */
#define MCU_START_SEC_VAR_NO_INIT_UNSPECIFIED_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static clock_element_state_t clkState[CLOCK_PRODUCERS_NO + 1U];
/* Clock stop uninitialized shared section data */
#define MCU_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_NO_CACHEABLE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#define MCU_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Mcu_MemMap.h"
static tCalcFreqDataType tmpData;
#define MCU_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Mcu_MemMap.h"
#define MCU_START_SEC_VAR_INIT_32
#include "Mcu_MemMap.h"
static uint32 configuredCoreClock = 0U; /* Frequency of the configured core clock. */
static uint32 configuredAipsPlatClock = 0U; /* Frequency of the configured aips slow clock. */
static uint32 configuredAipsSlowClock = 0U; /* Frequency of the configured aips plat clock. */
static uint32 configuredHseClock = 0U; /* Frequency of the configured hse clock. */
#ifdef RECORD_CALLBACK_TIMESTAMPS
#define SYSTICK_MAX (0xFFFFFFu)
uint32 timestampCallback[CALC_FREQ_CALLBACKS_NO];
uint32 systickCounter = 0U;
uint32 timestampIndexEntry = 0U;
#endif
#define MCU_STOP_SEC_VAR_INIT_32
#include "Mcu_MemMap.h"
/* Clock start initialized section data */
#define MCU_START_SEC_VAR_INIT_UNSPECIFIED
#include "Mcu_MemMap.h"
static const Clock_Ip_ClockConfigType *config_clock = NULL_PTR;
pcfsEntry pcfsEntries[PCFS_ENTRIES_NO] = {
/* PCFS_PLL_PHI0 */
{
PLL_PHI0_CLK, /* Name of the clock that supports pcfs (rampup-rampdown) */
CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL, /* Pointer to pcfs configuration structure - by default is not under mcu control */
0U, /* SDUR */
0U, /* DIVC_INIT */
0U, /* DIV_RATE */
0U, /* DIV_START_VALUE */
0U, /* DIV_END_VALUE */
},
};
cmuEntry cmuEntries[CMU_ENTRIES_NO] = {
/* CMU_FXOSC_CLK */
{
FXOSC_CLK, /* Name of the clock that supports cmu (clock monitor) */
CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL, /* Pointer to pcfs configuration structure - by default is not under mcu control */
0U, /* enable */
0U, /* refCount */
0x00FFFFFCU, /* hfRef */
3U, /* lfRef */
},
/* CMU_CORE_CLK */
{
CORE_CLK, /* Name of the clock that supports cmu (clock monitor) */
CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL, /* Pointer to pcfs configuration structure - by default is not under mcu control */
0U, /* enable */
0U, /* refCount */
0x00FFFFFCU, /* hfRef */
3U, /* lfRef */
},
/* AIPS_PLAT_CLK */
{
AIPS_PLAT_CLK, /* Name of the clock that supports cmu (clock monitor) */
CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL, /* Pointer to pcfs configuration structure - by default is not under mcu control */
0U, /* enable */
0U, /* refCount */
0x00FFFFFCU, /* hfRef */
3U, /* lfRef */
},
/* HSE_CLK */
{
HSE_CLK, /* Name of the clock that supports cmu (clock monitor) */
CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL, /* Pointer to pcfs configuration structure - by default is not under mcu control */
0U, /* enable */
0U, /* refCount */
0x00FFFFFCU, /* hfRef */
3U, /* lfRef */
},
};
/* Clock stop initialized section data */
#define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#ifdef FEATURE_CLOCK_IP_HAS_RAM_WAIT_STATES
#define MCU_START_SEC_CODE_AC
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static void PRAMC_SetRamIWS(void);
#define MCU_STOP_SEC_CODE_AC
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#endif
#define MCU_START_SEC_CODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#ifdef FEATURE_CLOCK_IP_HAS_RAM_WAIT_STATES
void SetRamWaitStates(void)
{
#ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
/**
* @violates @ref Clock_Ip_S32G3XX_c_REF_4 A function should be used in preference to a function-like macro where they are interchangeable.
*/
/**
* @violates @ref Clock_Ip_S32G3XX_c_REF_5 The comma is used to abstract the trusted call function and to determine when the return into user mode is needed.
*/
OsIf_Trusted_Call(PRAMC_SetRamIWS);
#else
PRAMC_SetRamIWS();
#endif
#else
PRAMC_SetRamIWS();
#endif
}
#endif
#ifdef FEATURE_CLOCK_IP_HAS_FLASH_WAIT_STATES
void FLASH_SetFlashIWS(void);
void SetFlashWaitStates(void)
{
FLASH_SetFlashIWS();
}
#endif
void UpdateClockState(Clock_Ip_NameType name, clock_element_state_t state)
{
if ( ((uint32)name) < ((uint32)THE_LAST_PRODUCER_CLK))
{
clkState[name] = state;
}
}
clock_element_state_t GetClockState(Clock_Ip_NameType name)
{
clock_element_state_t retValue;
if ( ((uint32)name) < ((uint32)THE_LAST_PRODUCER_CLK))
{
retValue = clkState[name];
}
else
{
retValue = clkState[THE_LAST_PRODUCER_CLK];
}
return retValue;
}
void SpecificPeripheralClockInitialization(Clock_IP_SpecificPeriphConfigType const * config)
{
(void)config;
}
void SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * config)
{
config_clock = config;
}
uint32 GetProducerClockFreq(Clock_Ip_NameType clockName)
{
return bufferFreqs[freqPointers[clockName]];
}
void UpdateFrequencies(power_modes_t powerMode)
{
static const Clock_Ip_NameType selectorEntriesSCS_CLK[3U] = {THE_LAST_PRODUCER_CLK,FIRC_CLK,PLL_PHI0_CLK};
static const uint8 bufferFreqEntriesSCS_CLK[3U] = {BUFFER_NO_CLK,BUFFER_FIRC,BUFFER_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesCORE_CLK[3U] = {BUFFER_NO_CLK,BUFFER_CORE_FIRC,BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesAIPS_PLAT_CLK[3U] = {BUFFER_NO_CLK,BUFFER_AIPSPLAT_FIRC,BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesAIPS_SLOW_CLK[3U] = {BUFFER_NO_CLK,BUFFER_AIPSSLOW_FIRC,BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesHSE_CLK[3U] = {BUFFER_NO_CLK,BUFFER_HSE_FIRC,BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesDCM_CLK[3U] = {BUFFER_NO_CLK,BUFFER_DCM_FIRC,BUFFER_DCM_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesLBIST_CLK[3U] = {BUFFER_NO_CLK,BUFFER_LBIST_FIRC,BUFFER_LBIST_PLLPHI0_PLLPOSTDIV_PLL};
static const uint8 bufferFreqEntriesQSPI_MEM_CLK[3U] = {BUFFER_NO_CLK,BUFFER_QSPIMEM_FIRC,BUFFER_QSPIMEM_PLLPHI0_PLLPOSTDIV_PLL};
static const Clock_Ip_NameType selectorEntriesCLKOUT_RUN_CLK[13U] = {THE_LAST_PRODUCER_CLK,FIRC_CLK,PLL_PHI0_CLK,SIRC_CLK,FXOSC_CLK,SXOSC_CLK,PLL_PHI1_CLK,CORE_CLK,HSE_CLK,AIPS_PLAT_CLK,AIPS_SLOW_CLK,EMAC_MII_RX_CLK,EMAC_MII_RMII_TX_CLK};
static const uint8 bufferFreqEntriesCLKOUT_RUN_CLK[3U][13U] =
{
{BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK,BUFFER_NO_CLK},
{BUFFER_NO_CLK,BUFFER_CLKOUTRUN_FIRC,BUFFER_CLKOUTRUN_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_SIRC,BUFFER_CLKOUTRUN_FXOSC,BUFFER_CLKOUTRUN_SXOSC,BUFFER_CLKOUTRUN_PLLPHI1_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_CORE_FIRC,BUFFER_CLKOUTRUN_HSE_FIRC,BUFFER_CLKOUTRUN_AIPSPLAT_FIRC,BUFFER_CLKOUTRUN_AIPSSLOW_FIRC,BUFFER_CLKOUTRUN_emacmiirx,BUFFER_CLKOUTRUN_emacmiirmiitx},
{BUFFER_NO_CLK,BUFFER_CLKOUTRUN_FIRC,BUFFER_CLKOUTRUN_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_SIRC,BUFFER_CLKOUTRUN_FXOSC,BUFFER_CLKOUTRUN_SXOSC,BUFFER_CLKOUTRUN_PLLPHI1_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_CORE_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_HSE_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL,BUFFER_CLKOUTRUN_emacmiirx,BUFFER_CLKOUTRUN_emacmiirmiitx}
};
static const clock_element_state_t convertValueToClockState[256U] =
{DISABLED_CLOCK,SELECTOR_ENTRY_1,SELECTOR_ENTRY_2,SELECTOR_ENTRY_3,SELECTOR_ENTRY_4,SELECTOR_ENTRY_5,SELECTOR_ENTRY_6,SELECTOR_ENTRY_7,SELECTOR_ENTRY_8,SELECTOR_ENTRY_9,SELECTOR_ENTRY_10,SELECTOR_ENTRY_11,SELECTOR_ENTRY_12,SELECTOR_ENTRY_13,SELECTOR_ENTRY_14,SELECTOR_ENTRY_15,SELECTOR_ENTRY_16,SELECTOR_ENTRY_17,SELECTOR_ENTRY_18,SELECTOR_ENTRY_19,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,
DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,DISABLED_CLOCK,ENABLED_CLOCK};
(void)powerMode;
freqPointers[FIRC_STANDBY_CLK] = ((uint8)clkState[FIRC_STANDBY_CLK]) & BUFFER_FIRC;
freqPointers[SIRC_STANDBY_CLK] = ((uint8)clkState[SIRC_STANDBY_CLK]) & BUFFER_SIRC;
uint8 pllEn = ((uint8)clkState[PLL_CLK]);
freqPointers[FXOSC_CLK] = ((uint8)clkState[FXOSC_CLK]) & BUFFER_FXOSC;
freqPointers[SXOSC_CLK] = ((uint8)clkState[SXOSC_CLK]) & BUFFER_SXOSC;
freqPointers[PLL_CLK] = pllEn & BUFFER_PLL;
clkState[PLL_PHI0_CLK] = convertValueToClockState[((uint8)clkState[PLL_PHI0_CLK]) & pllEn];
clkState[PLL_PHI1_CLK] = convertValueToClockState[((uint8)clkState[PLL_PHI1_CLK]) & pllEn];
freqPointers[PLL_PHI0_CLK] = ((uint8)clkState[PLL_PHI0_CLK]) & BUFFER_PLLPHI0_PLLPOSTDIV_PLL;
freqPointers[PLL_PHI1_CLK] = ((uint8)clkState[PLL_PHI1_CLK]) & BUFFER_PLLPHI1_PLLPOSTDIV_PLL;
freqPointers[SCS_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesSCS_CLK[clkState[SCS_CLK]];
freqPointers[CORE_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesCORE_CLK[clkState[SCS_CLK]];
freqPointers[AIPS_PLAT_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesAIPS_PLAT_CLK[clkState[SCS_CLK]];
freqPointers[AIPS_SLOW_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesAIPS_SLOW_CLK[clkState[SCS_CLK]];
freqPointers[HSE_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesHSE_CLK[clkState[SCS_CLK]];
freqPointers[DCM_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesDCM_CLK[clkState[SCS_CLK]];
freqPointers[LBIST_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesLBIST_CLK[clkState[SCS_CLK]];
freqPointers[QSPI_MEM_CLK] = ((uint8)clkState[selectorEntriesSCS_CLK[clkState[SCS_CLK]]]) & bufferFreqEntriesQSPI_MEM_CLK[clkState[SCS_CLK]];
clkState[CLKOUT_RUN_CLK] = selectorEntryIndex[(cgm[0U][6U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT];
freqPointers[CLKOUT_RUN_CLK] = ((uint8)clkState[selectorEntriesCLKOUT_RUN_CLK[clkState[CLKOUT_RUN_CLK]]]) &
bufferFreqEntriesCLKOUT_RUN_CLK[clkState[SCS_CLK]][clkState[CLKOUT_RUN_CLK]];
}
static void CONFIG_ELEMENTS_MAPPINGS_01(void)
{
uint8 i;
#ifdef RECORD_CALLBACK_TIMESTAMPS
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE(0u);
S32_SysTick->RVR = S32_SysTick_RVR_RELOAD(SYSTICK_MAX);
S32_SysTick->CVR = S32_SysTick_CVR_CURRENT(0U);
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE(1u) | S32_SysTick_CSR_TICKINT(0u) | S32_SysTick_CSR_CLKSOURCE(1u);
#endif
for (i = 0U; i <= ((uint8)THE_LAST_PRODUCER_CLK); i++)
{
freqPointers[i] = CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL;
}
for (i = 0U; i < config_clock->ircoscsCount; i++)
{
freqPointers[config_clock->ircoscs[i].name] = i + 1U;
}
for (i = 0U; i < config_clock->xoscsCount; i++)
{
freqPointers[config_clock->xoscs[i].name] = i + 1U;
}
for (i = 0U; i < config_clock->pllsCount; i++)
{
freqPointers[config_clock->plls[i].name] = i + 1U;
}
for (i = 0U; i < config_clock->extClksCount; i++)
{
freqPointers[config_clock->extClks[i].name] = i + 1U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CONFIG_ELEMENTS_MAPPINGS_02(void)
{
uint8 i,j;
for (i = 0U; i < config_clock->selectorsCount; i++)
{
if (((uint8)config_clock->selectors[i].name) < ((uint8)THE_LAST_PRODUCER_CLK))
{
freqPointers[config_clock->selectors[i].name] = i + 1U;
}
}
for (i = 0U; i < config_clock->dividersCount; i++)
{
if (((uint8)config_clock->dividers[i].name) < ((uint8)THE_LAST_PRODUCER_CLK))
{
freqPointers[config_clock->dividers[i].name] = i + 1U;
}
}
for (i = 0U; i < config_clock->fracDivsCount; i++)
{
if (((uint8)config_clock->fracDivs[i].name) < ((uint8)THE_LAST_PRODUCER_CLK))
{
freqPointers[config_clock->fracDivs[i].name] = i + 1U;
}
}
for (i = 0U; i < config_clock->pcfsCount; i++)
{
for (j = 0U; j < PCFS_ENTRIES_NO; j++)
{
if (pcfsEntries[j].name == config_clock->pcfs[i].name)
{
pcfsEntries[j].configIndex = i+1U;
}
}
}
for (i = 0U; i < config_clock->cmusCount; i++)
{
for (j = 0U; j < CMU_ENTRIES_NO; j++)
{
if (cmuEntries[j].name == config_clock->cmus[i].name)
{
cmuEntries[j].configIndex = i+1U;
}
}
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void NOT_UNDER_MCU_CONTROL_A(void)
{
clkState[FIRC_CLK] = ENABLED_CLOCK;
if (freqPointers[FIRC_STANDBY_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[FIRC_STANDBY_CLK] = (((FIRC->STDBY_ENABLE & FIRC_STDBY_ENABLE_STDBY_EN_MASK) >> FIRC_STDBY_ENABLE_STDBY_EN_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
if (freqPointers[FXOSC_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[FXOSC_CLK] = (((xosc[0]->STAT & FXOSC_STAT_OSC_STAT_MASK) >> FXOSC_STAT_OSC_STAT_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
if (freqPointers[SIRC_STANDBY_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[SIRC_STANDBY_CLK] = (((SIRC->MISCELLANEOUS_IN & SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE_MASK) >> SIRC_MISCELLANEOUS_IN_STANDBY_ENABLE_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
clkState[SIRC_CLK] = ENABLED_CLOCK;
if (freqPointers[SXOSC_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[SXOSC_CLK] = (((SXOSC->SXOSC_STAT & SXOSC_SXOSC_STAT_OSC_STAT_MASK) >> SXOSC_SXOSC_STAT_OSC_STAT_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
if (freqPointers[PLL_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
/* Check if the PLL is enabled in MC_ME */
if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) != 0U)
{
/* Check clock status for PLL */
clkState[PLL_CLK] = (((pll[0]->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
else
{
clkState[PLL_CLK] = DISABLED_CLOCK;
}
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void NOT_UNDER_MCU_CONTROL_B(void)
{
if (freqPointers[PLL_PHI0_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
/* Check if the PLL is enabled in MC_ME */
if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) != 0U)
{
/* Check clock status for PLL */
clkState[PLL_PHI0_CLK] = (((pll[0]->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
else
{
clkState[PLL_PHI0_CLK] = DISABLED_CLOCK;
}
}
if (freqPointers[PLL_PHI1_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
/* Check if the PLL is enabled in MC_ME */
if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) != 0U)
{
/* Check clock status for PLL */
clkState[PLL_PHI1_CLK] = (((pll[0]->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODIV_DE_SHIFT) == 0U) ? DISABLED_CLOCK : ENABLED_CLOCK;
}
else
{
clkState[PLL_PHI1_CLK] = DISABLED_CLOCK;
}
}
clkState[EMAC_MII_RX_CLK] = ENABLED_CLOCK;
clkState[EMAC_MII_RMII_TX_CLK] = ENABLED_CLOCK;
if (freqPointers[SCS_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[SCS_CLK] = selectorEntryIndex[(cgm[0U][0U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT];
}
if (freqPointers[CLKOUT_RUN_CLK] == CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
clkState[CLKOUT_RUN_CLK] = selectorEntryIndex[(cgm[0U][6U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT];
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IRCOSCS_XOSCS_SERDES_EXTERNAL_CLOCKS(void)
{
const Clock_Ip_XoscConfigType *xoscConfig;
const Clock_Ip_ExtClkConfigType *extClkConfig;
if (freqPointers[FXOSC_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
xoscConfig = &config_clock->xoscs[freqPointers[FXOSC_CLK] - 1U];
bufferFreqs[BUFFER_FXOSC] = xoscConfig->freq;
}
else
{
bufferFreqs[BUFFER_FXOSC] = 16000000U;
}
if (freqPointers[SXOSC_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
xoscConfig = &config_clock->xoscs[freqPointers[SXOSC_CLK] - 1U];
bufferFreqs[BUFFER_SXOSC] = xoscConfig->freq;
}
else
{
bufferFreqs[BUFFER_SXOSC] = 32768U;
}
bufferFreqs[BUFFER_SIRC] = 32000U;
bufferFreqs[BUFFER_FIRC] = 48000000U;
freqPointers[FIRC_CLK] = BUFFER_FIRC;
freqPointers[SIRC_CLK] = BUFFER_SIRC;
if (freqPointers[EMAC_MII_RX_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
extClkConfig = &config_clock->extClks[freqPointers[EMAC_MII_RX_CLK] - 1U];
bufferFreqs[BUFFER_emacmiirx] = extClkConfig->value;
}
else
{
bufferFreqs[BUFFER_emacmiirx] = 0U;
}
if (freqPointers[EMAC_MII_RMII_TX_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
extClkConfig = &config_clock->extClks[freqPointers[EMAC_MII_RMII_TX_CLK] - 1U];
bufferFreqs[BUFFER_emacmiirmiitx] = extClkConfig->value;
}
else
{
bufferFreqs[BUFFER_emacmiirmiitx] = 0U;
}
freqPointers[EMAC_MII_RX_CLK] = BUFFER_emacmiirx;
freqPointers[EMAC_MII_RMII_TX_CLK] = BUFFER_emacmiirmiitx;
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PLL_A(void)
{
const Clock_Ip_PllConfigType *pllConfig;
tmpData.input1 = bufferFreqs[BUFFER_FXOSC]; /* fin */
if (freqPointers[PLL_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
pllConfig = &config_clock->plls[freqPointers[PLL_CLK] - 1U];
tmpData.input2 = pllConfig->predivider; /* rdiv */
tmpData.input3 = pllConfig->mulFactorDiv; /* mfi */
tmpData.input4 = pllConfig->numeratorFracLoopDiv; /* mfn */
tmpData.input5 = 0U;
}
else
{
tmpData.input2 = ((pll[0]->PLLDV & PLL_PLLDV_RDIV_MASK) >> PLL_PLLDV_RDIV_SHIFT); /* rdiv */
tmpData.input3 = ((pll[0]->PLLDV & PLL_PLLDV_MFI_MASK) >> PLL_PLLDV_MFI_SHIFT); /* mfi */
tmpData.input4 = ((pll[0]->PLLFD & PLL_PLLFD_MFN_MASK) >> PLL_PLLFD_MFN_SHIFT); /* mfn */
tmpData.input5 = ((pll[0]->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT); /* odiv2 */
}
tmpData.aux1 = tmpData.input3 / tmpData.input2; /* mfi divided by rdiv */
tmpData.aux2 = tmpData.input3 - (tmpData.aux1 * tmpData.input2); /* mfi minus aux1 multiplied by rdiv */
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PLL_B(void)
{
tmpData.aux3 = (tmpData.input2 << 14U) + (tmpData.input2 << 11U); /* rdiv multiplied by 18432 */
tmpData.aux4 = tmpData.input1 / tmpData.aux3; /* fin divide by (rdiv multiplied by 18432) */
tmpData.aux5 = tmpData.input1 - (tmpData.aux4 * tmpData.aux3); /* fin minus aux4 multiplied by (rdiv mul 18432) */
tmpData.output = tmpData.aux1 * tmpData.input1; /* aux1 multipied by fin */
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PLL_C(void)
{
tmpData.output += tmpData.input1 / tmpData.input2 * tmpData.aux2; /* fin divided by rdiv and multiplied by aux2 */
tmpData.output += tmpData.aux4 * tmpData.input4; /* mfn multiplied by aux4 */
tmpData.output += tmpData.aux5 * tmpData.input4 / tmpData.aux3; /* aux5 multiplied by mfn and divide by (rdiv mul 18432) */
bufferFreqs[BUFFER_PLL] = tmpData.output;
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_A(void)
{
uint32 dividerValue;
if (freqPointers[CORE_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CORE_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CORE_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CORE_FIRC] = 0U;
}
if (freqPointers[AIPS_PLAT_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[AIPS_PLAT_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[1U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_AIPSPLAT_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_AIPSPLAT_FIRC] = 0U;
}
if (freqPointers[AIPS_SLOW_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[AIPS_SLOW_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[2U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_AIPSSLOW_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_AIPSSLOW_FIRC] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_B(void)
{
uint32 dividerValue;
if (freqPointers[HSE_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[HSE_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[3U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_HSE_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_HSE_FIRC] = 0U;
}
if (freqPointers[DCM_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[DCM_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[4U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_DCM_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_DCM_FIRC] = 0U;
}
if (freqPointers[LBIST_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[LBIST_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[5U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_LBIST_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_LBIST_FIRC] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_C(void)
{
uint32 dividerValue;
if (freqPointers[QSPI_MEM_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[QSPI_MEM_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[6U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_QSPIMEM_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_QSPIMEM_FIRC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_FIRC] = bufferFreqs[BUFFER_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_FIRC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_SIRC] = bufferFreqs[BUFFER_SIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_SIRC] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_D(void)
{
uint32 dividerValue;
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_FXOSC] = bufferFreqs[BUFFER_FXOSC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_FXOSC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_SXOSC] = bufferFreqs[BUFFER_SXOSC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_SXOSC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_CORE_FIRC] = bufferFreqs[BUFFER_CORE_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_CORE_FIRC] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_E(void)
{
uint32 dividerValue;
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_HSE_FIRC] = bufferFreqs[BUFFER_HSE_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_HSE_FIRC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSPLAT_FIRC] = bufferFreqs[BUFFER_AIPSPLAT_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSPLAT_FIRC] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSSLOW_FIRC] = bufferFreqs[BUFFER_AIPSSLOW_FIRC] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSSLOW_FIRC] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_F(void)
{
uint32 dividerValue;
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_emacmiirx] = bufferFreqs[BUFFER_emacmiirx] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_emacmiirx] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_emacmiirmiitx] = bufferFreqs[BUFFER_emacmiirmiitx] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_emacmiirmiitx] = 0U;
}
if (freqPointers[PLL_POSTDIV_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[PLL_POSTDIV_CLK] - 1U].value;
}
else
{
dividerValue = ((pll[0]->PLLDV & PLL_PLLDV_ODIV2_MASK) >> PLL_PLLDV_ODIV2_SHIFT);
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLL];
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_G(void)
{
uint32 dividerValue;
if (freqPointers[PLL_PHI0_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[PLL_PHI0_CLK] - 1U].value;
}
else
{
dividerValue = (((pll[0]->PLLODIV[0] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U);
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[PLL_PHI1_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[PLL_PHI1_CLK] - 1U].value;
}
else
{
dividerValue = (((pll[0]->PLLODIV[1] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U);
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_PLLPHI1_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_PLLPHI1_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[CORE_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CORE_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_H(void)
{
uint32 dividerValue;
if (freqPointers[AIPS_PLAT_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[AIPS_PLAT_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[1U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[AIPS_SLOW_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[AIPS_SLOW_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[2U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[HSE_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[HSE_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[3U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_I(void)
{
uint32 dividerValue;
if (freqPointers[DCM_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[DCM_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[4U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_DCM_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_DCM_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[LBIST_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[LBIST_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[5U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_LBIST_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_LBIST_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[QSPI_MEM_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[QSPI_MEM_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][0U]->divider[6U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_QSPIMEM_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_QSPIMEM_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_J(void)
{
uint32 dividerValue;
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_PLLPHI1_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_PLLPHI1_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_PLLPHI1_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_CORE_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_CORE_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void IntegerDividers_K(void)
{
uint32 dividerValue;
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_HSE_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_HSE_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
if (freqPointers[CLKOUT_RUN_CLK] != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
dividerValue = config_clock->dividers[freqPointers[CLKOUT_RUN_CLK] - 1U].value;
}
else
{
dividerValue = ((cgm[0U][6U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + 1U;
}
if (dividerValue != 0U)
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL] = bufferFreqs[BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL] / dividerValue;
}
else
{
bufferFreqs[BUFFER_CLKOUTRUN_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL] = 0U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS(void)
{
uint32 i;
/* Find configured clock */
const Clock_Ip_SelectorConfigType *selectorSCS_CLK = NULL_PTR;
for (i = 0U; i < config_clock->selectorsCount; i++)
{
if (SCS_CLK == config_clock->selectors[i].name)
{
selectorSCS_CLK = &config_clock->selectors[i];
break;
}
}
if (selectorSCS_CLK != NULL_PTR)
{
switch(selectorSCS_CLK->value)
{
case FIRC_CLK:
{
configuredCoreClock = bufferFreqs[BUFFER_CORE_FIRC];
configuredAipsPlatClock = bufferFreqs[BUFFER_AIPSPLAT_FIRC];
configuredAipsSlowClock = bufferFreqs[BUFFER_AIPSSLOW_FIRC];
configuredHseClock = bufferFreqs[BUFFER_HSE_FIRC];
}
break;
case PLL_PHI0_CLK:
{
configuredCoreClock = bufferFreqs[BUFFER_CORE_PLLPHI0_PLLPOSTDIV_PLL];
configuredAipsPlatClock = bufferFreqs[BUFFER_AIPSPLAT_PLLPHI0_PLLPOSTDIV_PLL];
configuredAipsSlowClock = bufferFreqs[BUFFER_AIPSSLOW_PLLPHI0_PLLPOSTDIV_PLL];
configuredHseClock = bufferFreqs[BUFFER_HSE_PLLPHI0_PLLPOSTDIV_PLL];
}
break;
default:
{
configuredCoreClock = 0U;
configuredAipsPlatClock = 0U;
configuredAipsSlowClock = 0U;
configuredHseClock = 0U;
}
break;
}
}
else
{
configuredCoreClock = 0U;
configuredAipsPlatClock = 0U;
configuredAipsSlowClock = 0U;
configuredHseClock = 0U;
}
/* Fix warning compiler: unused variable */
(void)configuredCoreClock;
(void)configuredAipsPlatClock;
(void)configuredAipsSlowClock;
(void)configuredHseClock;
}
#define DEFAULT_MAX_ALLOWABLE_IDD_CHANGE 50U
static void PCFS_PLL_PHI0_A(void)
{
const Clock_Ip_PcfsConfigType *pcfsConfig;
uint32 maxAllowableIDDchange;
uint32 stepDuration;
uint32 finput, fsafe;
uint32 amaxBrut;
if (pcfsEntries[0U].configIndex != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
pcfsConfig = &config_clock->pcfs[pcfsEntries[0U].configIndex - 1U];
maxAllowableIDDchange = pcfsConfig->maxAllowableIDDchange;
stepDuration = pcfsConfig->stepDuration;
}
else
{
maxAllowableIDDchange = DEFAULT_MAX_ALLOWABLE_IDD_CHANGE;
stepDuration = ((cgmPcfs[0U]->PCFS_SDUR & MC_CGM_PCFS_SDUR_SDUR_MASK) >> MC_CGM_PCFS_SDUR_SDUR_SHIFT);
}
finput = bufferFreqs[BUFFER_PLLPHI0_PLLPOSTDIV_PLL] / 1000000U;
fsafe = bufferFreqs[BUFFER_FIRC] / 1000000U;
tmpData.input1 = stepDuration; /* step duration */
tmpData.input2 = finput; /* frequency of the input clock for which progressive switch is processed */
tmpData.input3 = fsafe; /* frequency of safe clock */
/* Calculate amax=fchg/Finput */
amaxBrut = (maxAllowableIDDchange * stepDuration * 100000U / (finput * DYNAMIC_IDD_CHANGE));
tmpData.aux1 = amaxBrut;
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PCFS_PLL_PHI0_B(void)
{
const uint32 aMax[A_MAX_SIZE] = {0U,5U,10U,15U,20U,100U};
const uint32 pcfsRate[A_MAX_SIZE] = {0U,12U,48U,112U,184U,1000U};
uint32 amaxBrut = tmpData.aux1;
uint32 RATE = 0U;
uint8 i;
/* Round pcfs rate by rounding amax */
if (amaxBrut < aMax[0U])
{
RATE = pcfsRate[0U];
}
else if (amaxBrut > aMax[A_MAX_SIZE - 1U])
{
RATE = pcfsRate[A_MAX_SIZE - 1U];
}
else
{
for (i = 1U; i < (uint8)A_MAX_SIZE; i++)
{
if (aMax[i-1U] < amaxBrut)
{
RATE = pcfsRate[i - 1U];
}
}
}
tmpData.aux1 = RATE; /* RATE */
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PCFS_PLL_PHI0_C(void)
{
uint32 finput = tmpData.input2;
uint32 fsafe = tmpData.input3;
uint32 RATE = tmpData.aux1;
/* Calculate K by using formula k = ceil(0.5 + sqrt(0.25 - (2000 * (1 -(Finput/fsafe)) / RATE))) */
tmpData.aux2 = 256U + (((1024U * 2000U) * finput) / (fsafe * RATE)) - ((1024U * 2000U) / RATE);
tmpData.aux3 = 1UL << 30U; /* The second-to-top bit is set: use 1u << 14 for uint16 type; use 1uL<<30 for uint32 type */
/* Implement sqrt from K formula by using a square-root computing in embedded C */
/* "one" starts at the highest power of four <= than the argument */
while (tmpData.aux3 > tmpData.aux2)
{
tmpData.aux3 = tmpData.aux3 >> 2;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PCFS_PLL_PHI0_D(void)
{
/* Implement sqrt from K formula by using a square-root computing in embedded C */
while (tmpData.aux3 != 0U)
{
if (tmpData.aux2 >= (tmpData.aux4 + tmpData.aux3))
{
tmpData.aux2 = tmpData.aux2 - (tmpData.aux4 + tmpData.aux3);
tmpData.aux4 = tmpData.aux4 + (tmpData.aux3 << 1U);
}
tmpData.aux4 = tmpData.aux4 >> 1U;
tmpData.aux3 = tmpData.aux3 >> 2U;
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void PCFS_PLL_PHI0_E(void)
{
uint32 stepDuration = tmpData.input1;
uint32 finput = tmpData.input2;
uint32 fsafe = tmpData.input3;
uint32 RATE = tmpData.aux1;
uint32 K = (64U + 127U + (tmpData.aux4 << 2U)) >> 7U; /* Calculated K from k = ceil(0.5 + sqrt(0.25 - (2000 * (1 -(Fi/fsafe)) / RATE))) */
pcfsEntries[0U].sdur = (uint32)(stepDuration * fsafe);
pcfsEntries[0U].divc_init = (uint32)(RATE * K);
pcfsEntries[0U].divc_rate = RATE;
pcfsEntries[PCFS_PLLPHI0].div_startValue = 999U + (((uint32)(RATE * K * (K+1U))) >> 1U);
pcfsEntries[0U].div_endValue = (finput * 1000U / fsafe) - 1U;
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
#define CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER 10U
#define CMU_FC_VAR 3U
#define CMU_REFERENCE_CLOCK_VARIATION 33U
#define CMU_MONITORED_CLOCK_VARIATION 11U
static void CMU_FXOSC_CLK_A(void)
{
uint32 fReferenceClk, fMonitoredClk, fBusClk;
uint32 cmp1, cmp2;
uint8 enable;
const Clock_Ip_CmuConfigType *cmuConfig;
if (cmuEntries[0U].configIndex != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
cmuConfig = &config_clock->cmus[cmuEntries[0U].configIndex - 1U];
enable = cmuConfig->enable;
}
else
{
enable = 0U;
}
fReferenceClk = bufferFreqs[BUFFER_FIRC] / 1000U;
fMonitoredClk = bufferFreqs[BUFFER_FXOSC] / 1000U;
fBusClk = configuredAipsSlowClock / 1000U;
tmpData.input1 = enable; /* Enable cmu */
tmpData.input2 = fReferenceClk; /* Reference clock */
tmpData.input3 = fMonitoredClk; /* fMonitoredClk */
tmpData.input4 = fBusClk; /* frequency of safe clock */
/* cmp1 = ceiling of (3 * fRef/ fBus) */
cmp1 = 1U + (uint32)((float32)((3.0F * (float32)fReferenceClk) / (float32)fBusClk));
/* cmp2 = ceiling of (8 + (5 * fRef / fMonitor)) */
if (fMonitoredClk > 0U)
{
cmp2 = 9U + (uint32)((float32)((5.0F * (float32)fReferenceClk) / (float32)fMonitoredClk));
}
else
{
cmp2 = 0U;
}
cmuEntries[0U].enable = enable;
/* REF count = Max(cmp1,cmp2) */
cmuEntries[0U].refCount = (((cmp1 > cmp2) ? cmp1 : cmp2) * CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER);
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_FXOSC_CLK_B(void)
{
uint32 fReferenceClk, fMonitoredClk;
fReferenceClk = tmpData.input2; /* Reference clock */
fMonitoredClk = tmpData.input3; /* fMonitoredClk */
if (fReferenceClk > 0U)
{
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(max)/reference_clock(min)) * RCCR[REF_CNT]) + 3) */
cmuEntries[0U].hfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F + (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F - (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[0U].refCount)) + (float32)CMU_FC_VAR);
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(min)/reference_clock(max)) * RCCR[REF_CNT]) + 3) */
cmuEntries[0U].lfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F - (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F + (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[0U].refCount)) - (float32)CMU_FC_VAR);
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_CORE_CLK_A(void)
{
uint32 fReferenceClk, fMonitoredClk, fBusClk;
uint32 cmp1, cmp2;
uint8 enable;
const Clock_Ip_CmuConfigType *cmuConfig;
if (cmuEntries[1U].configIndex != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
cmuConfig = &config_clock->cmus[cmuEntries[1U].configIndex - 1U];
enable = cmuConfig->enable;
}
else
{
enable = 0U;
}
fReferenceClk = bufferFreqs[BUFFER_FXOSC] / 1000U;
fMonitoredClk = configuredCoreClock / 1000U;
fBusClk = configuredAipsSlowClock / 1000U;
tmpData.input1 = enable; /* Enable/disable cmu */
tmpData.input2 = fReferenceClk; /* Reference clock */
tmpData.input3 = fMonitoredClk; /* fMonitoredClk */
tmpData.input4 = fBusClk; /* frequency of safe clock */
/* cmp1 = ceiling of (3 * fRef/ fBus) */
cmp1 = 1U + (uint32)((float32)((3.0F * (float32)fReferenceClk) / (float32)fBusClk));
/* cmp2 = ceiling of (8 + (5 * fRef / fMonitor)) */
if (fMonitoredClk > 0U)
{
cmp2 = 9U + (uint32)((float32)((5.0F * (float32)fReferenceClk) / (float32)fMonitoredClk));
}
else
{
cmp2 = 0U;
}
cmuEntries[1U].enable = enable;
/* REF count = Max(cmp1,cmp2) */
cmuEntries[1U].refCount = (((cmp1 > cmp2) ? cmp1 : cmp2) * CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER);
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_CORE_CLK_B(void)
{
uint32 fReferenceClk, fMonitoredClk;
fReferenceClk = tmpData.input2; /* Reference clock */
fMonitoredClk = tmpData.input3; /* fMonitoredClk */
if (fReferenceClk > 0U)
{
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(max)/reference_clock(min)) * RCCR[REF_CNT]) + 3) */
cmuEntries[1U].hfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F + (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F - (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[1U].refCount)) + (float32)CMU_FC_VAR);
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(min)/reference_clock(max)) * RCCR[REF_CNT]) + 3) */
cmuEntries[1U].lfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F - (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F + (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[1U].refCount)) - (float32)CMU_FC_VAR);
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_AIPS_PLAT_CLK_A(void)
{
uint32 fReferenceClk, fMonitoredClk, fBusClk;
uint32 cmp1, cmp2;
uint8 enable;
const Clock_Ip_CmuConfigType *cmuConfig;
if (cmuEntries[2U].configIndex != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
cmuConfig = &config_clock->cmus[cmuEntries[2U].configIndex - 1U];
enable = cmuConfig->enable;
}
else
{
enable = 0U;
}
fReferenceClk = bufferFreqs[BUFFER_FIRC] / 1000U;
fMonitoredClk = configuredAipsPlatClock / 1000U;
fBusClk = configuredAipsSlowClock / 1000U;
tmpData.input1 = enable; /* Enable/disable cmu */
tmpData.input2 = fReferenceClk; /* Reference clock */
tmpData.input3 = fMonitoredClk; /* fMonitoredClk */
tmpData.input4 = fBusClk; /* frequency of safe clock */
/* cmp1 = ceiling of (3 * fRef/ fBus) */
cmp1 = 1U + (uint32)((float32)((3.0F * (float32)fReferenceClk) / (float32)fBusClk));
/* cmp2 = ceiling of (8 + (5 * fRef / fMonitor)) */
if (fMonitoredClk > 0U)
{
cmp2 = 9U + (uint32)((float32)((5.0F * (float32)fReferenceClk) / (float32)fMonitoredClk));
}
else
{
cmp2 = 0U;
}
cmuEntries[2U].enable = enable;
/* REF count = Max(cmp1,cmp2) */
cmuEntries[2U].refCount = (((cmp1 > cmp2) ? cmp1 : cmp2) * CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER);
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_AIPS_PLAT_CLK_B(void)
{
uint32 fReferenceClk, fMonitoredClk;
fReferenceClk = tmpData.input2; /* Reference clock */
fMonitoredClk = tmpData.input3; /* fMonitoredClk */
if (fReferenceClk > 0U)
{
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(max)/reference_clock(min)) * RCCR[REF_CNT]) + 3) */
cmuEntries[2U].hfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F + (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F - (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[2U].refCount)) + (float32)CMU_FC_VAR);
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(min)/reference_clock(max)) * RCCR[REF_CNT]) + 3) */
cmuEntries[2U].lfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F - (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F + (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[2U].refCount)) - (float32)CMU_FC_VAR);
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_HSE_CLK_A(void)
{
uint32 fReferenceClk, fMonitoredClk, fBusClk;
uint32 cmp1, cmp2;
uint8 enable;
const Clock_Ip_CmuConfigType *cmuConfig;
if (cmuEntries[3U].configIndex != CLOCK_ELEMENT_IS_NOT_UNDER_MCU_CONTROL)
{
cmuConfig = &config_clock->cmus[cmuEntries[3U].configIndex - 1U];
enable = cmuConfig->enable;
}
else
{
enable = 0U;
}
fReferenceClk = bufferFreqs[BUFFER_FIRC] / 1000U;
fMonitoredClk = configuredHseClock / 1000U;
fBusClk = configuredAipsSlowClock / 1000U;
tmpData.input1 = enable; /* Enable cmu */
tmpData.input2 = fReferenceClk; /* Reference clock */
tmpData.input3 = fMonitoredClk; /* fMonitoredClk */
tmpData.input4 = fBusClk; /* frequency of safe clock */
/* cmp1 = ceiling of (3 * fRef/ fBus) */
cmp1 = 1U + (uint32)((float32)((3.0F * (float32)fReferenceClk) / (float32)fBusClk));
/* cmp2 = ceiling of (8 + (5 * fRef / fMonitor)) */
if (fMonitoredClk > 0U)
{
cmp2 = 9U + (uint32)((float32)((5.0F * (float32)fReferenceClk) / (float32)fMonitoredClk));
}
else
{
cmp2 = 0U;
}
cmuEntries[3U].enable = enable;
/* REF count = Max(cmp1,cmp2) */
cmuEntries[3U].refCount = (((cmp1 > cmp2) ? cmp1 : cmp2) * CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER);
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
static void CMU_HSE_CLK_B(void)
{
uint32 fReferenceClk, fMonitoredClk;
fReferenceClk = tmpData.input2; /* Reference clock */
fMonitoredClk = tmpData.input3; /* fMonitoredClk */
if (fReferenceClk > 0U)
{
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(max)/reference_clock(min)) * RCCR[REF_CNT]) + 3) */
cmuEntries[3U].hfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F + (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F - (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[3U].refCount)) + (float32)CMU_FC_VAR);
/* The formula calculation: HTCR[HFREF] = (((monitored_clock(min)/reference_clock(max)) * RCCR[REF_CNT]) + 3) */
cmuEntries[3U].lfRef = (uint32)(((((float32)fMonitoredClk * (1000.0F - (float32)CMU_MONITORED_CLOCK_VARIATION)) / ((float32)fReferenceClk * (1000.0F + (float32)CMU_REFERENCE_CLOCK_VARIATION))) * ((float32)cmuEntries[3U].refCount)) - (float32)CMU_FC_VAR);
}
#ifdef RECORD_CALLBACK_TIMESTAMPS
uint32 oldSystickCounter = systickCounter;
systickCounter = S32_SysTick->CVR;
timestampCallback[timestampIndexEntry++] = oldSystickCounter - systickCounter;
#endif
}
void McMeEnterKey(void)
{
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 The cast is used to access memory mapped registers.
*/
MC_ME->CTL_KEY = 0x5AF0U; /* Enter key */
/**
* @violates @ref Clock_Ip_Specific_c_REF_3 The cast is used to access memory mapped registers.
*/
MC_ME->CTL_KEY = 0xA50FU;
}
#if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
static boolean McMeGetPllStatus(void);
static boolean McMeGetCmuStatus(void);
static void McMeEnablePll(void);
static void McMeEnableCmu(void);
static void CallbackDelay(void);
static boolean McMeGetPllStatus(void)
{
return ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U) ? FALSE : TRUE;
}
static boolean McMeGetCmuStatus(void)
{
return ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK) == 0U) ? FALSE : TRUE;
}
static void McMeEnablePll(void)
{
uint32 StartTime;
uint32 ElapsedTime;
uint32 TimeoutTicks;
boolean TimeoutOccurred = FALSE;
/* Enable clock for PLL device */
MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ56(1U); /* REQ56: Frequency Modulated Phase-Locked Loop */
MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
McMeEnterKey();
/* Wait until PLL clock is running */
ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
do
{
TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
}
while(((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U) && (FALSE == TimeoutOccurred));
/* timeout notification */
if (TRUE == TimeoutOccurred)
{
/* Report timeout error */
ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PLL_CLK);
}
}
static void McMeEnableCmu(void)
{
uint32 StartTime;
uint32 ElapsedTime;
uint32 TimeoutTicks;
boolean TimeoutOccurred = FALSE;
/* Enable clock for CMU device */
MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ47(1U); /* REQ47: Clock monitor unit */
MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
McMeEnterKey();
/* Wait until CMU clock is running */
ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
do
{
TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
}
while(((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK) == 0U) && (FALSE == TimeoutOccurred));
/* timeout notification */
if (TRUE == TimeoutOccurred)
{
/* Report timeout error */
ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, RESERVED_CLK);
}
}
#endif
#endif
static void CallEmptyCallbacks(void)
{
cmuCallbacks[NO_CALLBACK].Set(NULL_PTR);
cmuCallbacks[NO_CALLBACK].Disable(RESERVED_CLK);
cmuCallbacks[NO_CALLBACK].Clear(RESERVED_CLK);
(void)cmuCallbacks[NO_CALLBACK].GetStatus(RESERVED_CLK);
dividerCallbacks[NO_CALLBACK].Set(NULL_PTR);
dividerTriggerCallbacks[NO_CALLBACK].Configure(NULL_PTR);
extOscCallbacks[NO_CALLBACK].Reset(NULL_PTR);
fracDivCallbacks[NO_CALLBACK].Set(NULL_PTR);
(void)fracDivCallbacks[NO_CALLBACK].Complete(RESERVED_CLK);
gateCallbacks[NO_CALLBACK].Set(NULL_PTR);
gateCallbacks[NO_CALLBACK].Update(RESERVED_CLK,false);
intOscCallbacks[NO_CALLBACK].Set(NULL_PTR);
pllCallbacks[NO_CALLBACK].Set(NULL_PTR);
(void)pllCallbacks[NO_CALLBACK].Complete(RESERVED_CLK);
selectorCallbacks[NO_CALLBACK].Set(NULL_PTR);
pcfsCallbacks[NO_CALLBACK].Set(NULL_PTR);
}
static void CallbackDelay(void)
{
boolean TimeoutOccurred = FALSE;
uint32 StartTime;
uint32 ElapsedTime;
uint32 TimeoutTicks;
ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, 10U);
do
{
TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
}
while (FALSE == TimeoutOccurred);
}
const CalcFreqCallback calcFreqCallbacks[CALC_FREQ_CALLBACKS_NO] = { \
CONFIG_ELEMENTS_MAPPINGS_01, CONFIG_ELEMENTS_MAPPINGS_02, \
NOT_UNDER_MCU_CONTROL_A, NOT_UNDER_MCU_CONTROL_B, \
IRCOSCS_XOSCS_SERDES_EXTERNAL_CLOCKS, \
PLL_A,PLL_B,PLL_C, \
IntegerDividers_A, IntegerDividers_B, IntegerDividers_C, IntegerDividers_D, IntegerDividers_E, IntegerDividers_F, IntegerDividers_G, IntegerDividers_H, IntegerDividers_I, IntegerDividers_J, IntegerDividers_K,\
CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS, \
PCFS_PLL_PHI0_A, PCFS_PLL_PHI0_B, PCFS_PLL_PHI0_C, PCFS_PLL_PHI0_D, PCFS_PLL_PHI0_E, \
CMU_FXOSC_CLK_A,CMU_FXOSC_CLK_B,CMU_CORE_CLK_A,CMU_CORE_CLK_B,CMU_AIPS_PLAT_CLK_A,CMU_AIPS_PLAT_CLK_B,CMU_HSE_CLK_A,CMU_HSE_CLK_B, \
CallEmptyCallbacks, \
CallbackDelay, \
};
static uint32 get_ADC0_CLK_Frequency(void);
static uint32 get_ADC1_CLK_Frequency(void);
static uint32 get_ADC2_CLK_Frequency(void);
static uint32 get_BCTU0_CLK_Frequency(void);
static uint32 get_CLKOUT_STANDBY_CLK_Frequency(void);
static uint32 get_CMP0_CLK_Frequency(void);
static uint32 get_CMP1_CLK_Frequency(void);
static uint32 get_CMP2_CLK_Frequency(void);
static uint32 get_CRC0_CLK_Frequency(void);
static uint32 get_DCM0_CLK_Frequency(void);
static uint32 get_DMAMUX0_CLK_Frequency(void);
static uint32 get_DMAMUX1_CLK_Frequency(void);
static uint32 get_EDMA0_CLK_Frequency(void);
static uint32 get_EDMA0_TCD0_CLK_Frequency(void);
static uint32 get_EDMA0_TCD10_CLK_Frequency(void);
static uint32 get_EDMA0_TCD11_CLK_Frequency(void);
static uint32 get_EDMA0_TCD12_CLK_Frequency(void);
static uint32 get_EDMA0_TCD13_CLK_Frequency(void);
static uint32 get_EDMA0_TCD14_CLK_Frequency(void);
static uint32 get_EDMA0_TCD15_CLK_Frequency(void);
static uint32 get_EDMA0_TCD16_CLK_Frequency(void);
static uint32 get_EDMA0_TCD17_CLK_Frequency(void);
static uint32 get_EDMA0_TCD18_CLK_Frequency(void);
static uint32 get_EDMA0_TCD19_CLK_Frequency(void);
static uint32 get_EDMA0_TCD1_CLK_Frequency(void);
static uint32 get_EDMA0_TCD20_CLK_Frequency(void);
static uint32 get_EDMA0_TCD21_CLK_Frequency(void);
static uint32 get_EDMA0_TCD22_CLK_Frequency(void);
static uint32 get_EDMA0_TCD23_CLK_Frequency(void);
static uint32 get_EDMA0_TCD24_CLK_Frequency(void);
static uint32 get_EDMA0_TCD25_CLK_Frequency(void);
static uint32 get_EDMA0_TCD26_CLK_Frequency(void);
static uint32 get_EDMA0_TCD27_CLK_Frequency(void);
static uint32 get_EDMA0_TCD28_CLK_Frequency(void);
static uint32 get_EDMA0_TCD29_CLK_Frequency(void);
static uint32 get_EDMA0_TCD2_CLK_Frequency(void);
static uint32 get_EDMA0_TCD30_CLK_Frequency(void);
static uint32 get_EDMA0_TCD31_CLK_Frequency(void);
static uint32 get_EDMA0_TCD3_CLK_Frequency(void);
static uint32 get_EDMA0_TCD4_CLK_Frequency(void);
static uint32 get_EDMA0_TCD5_CLK_Frequency(void);
static uint32 get_EDMA0_TCD6_CLK_Frequency(void);
static uint32 get_EDMA0_TCD7_CLK_Frequency(void);
static uint32 get_EDMA0_TCD8_CLK_Frequency(void);
static uint32 get_EDMA0_TCD9_CLK_Frequency(void);
static uint32 get_EIM0_CLK_Frequency(void);
static uint32 get_EMAC_RX_CLK_Frequency(void);
static uint32 get_EMAC0_RX_CLK_Frequency(void);
static uint32 get_EMAC_TS_CLK_Frequency(void);
static uint32 get_EMAC0_TS_CLK_Frequency(void);
static uint32 get_EMAC_TX_CLK_Frequency(void);
static uint32 get_EMAC0_TX_CLK_Frequency(void);
static uint32 get_EMIOS0_CLK_Frequency(void);
static uint32 get_EMIOS1_CLK_Frequency(void);
static uint32 get_EMIOS2_CLK_Frequency(void);
static uint32 get_ERM0_CLK_Frequency(void);
static uint32 get_FLASH0_CLK_Frequency(void);
static uint32 get_FLEXCANA_CLK_Frequency(void);
static uint32 get_FLEXCAN0_CLK_Frequency(void);
static uint32 get_FLEXCAN1_CLK_Frequency(void);
static uint32 get_FLEXCAN2_CLK_Frequency(void);
static uint32 get_FLEXCANB_CLK_Frequency(void);
static uint32 get_FLEXCAN3_CLK_Frequency(void);
static uint32 get_FLEXCAN4_CLK_Frequency(void);
static uint32 get_FLEXCAN5_CLK_Frequency(void);
static uint32 get_FLEXIO0_CLK_Frequency(void);
static uint32 get_INTM_CLK_Frequency(void);
static uint32 get_LCU0_CLK_Frequency(void);
static uint32 get_LCU1_CLK_Frequency(void);
static uint32 get_LPI2C0_CLK_Frequency(void);
static uint32 get_LPI2C1_CLK_Frequency(void);
static uint32 get_LPSPI0_CLK_Frequency(void);
static uint32 get_LPSPI1_CLK_Frequency(void);
static uint32 get_LPSPI2_CLK_Frequency(void);
static uint32 get_LPSPI3_CLK_Frequency(void);
static uint32 get_LPSPI4_CLK_Frequency(void);
static uint32 get_LPSPI5_CLK_Frequency(void);
static uint32 get_LPUART0_CLK_Frequency(void);
static uint32 get_LPUART10_CLK_Frequency(void);
static uint32 get_LPUART11_CLK_Frequency(void);
static uint32 get_LPUART12_CLK_Frequency(void);
static uint32 get_LPUART13_CLK_Frequency(void);
static uint32 get_LPUART14_CLK_Frequency(void);
static uint32 get_LPUART15_CLK_Frequency(void);
static uint32 get_LPUART1_CLK_Frequency(void);
static uint32 get_LPUART2_CLK_Frequency(void);
static uint32 get_LPUART3_CLK_Frequency(void);
static uint32 get_LPUART4_CLK_Frequency(void);
static uint32 get_LPUART5_CLK_Frequency(void);
static uint32 get_LPUART6_CLK_Frequency(void);
static uint32 get_LPUART7_CLK_Frequency(void);
static uint32 get_LPUART8_CLK_Frequency(void);
static uint32 get_LPUART9_CLK_Frequency(void);
static uint32 get_MSCM_CLK_Frequency(void);
static uint32 get_MUA_CLK_Frequency(void);
static uint32 get_MUB_CLK_Frequency(void);
static uint32 get_PIT0_CLK_Frequency(void);
static uint32 get_PIT1_CLK_Frequency(void);
static uint32 get_PIT2_CLK_Frequency(void);
static uint32 get_QSPI0_RAM_CLK_Frequency(void);
static uint32 get_QSPI_SFCK_CLK_Frequency(void);
static uint32 get_QSPI0_SFCK_CLK_Frequency(void);
static uint32 get_QSPI0_TX_MEM_CLK_Frequency(void);
static uint32 get_RTC_CLK_Frequency(void);
static uint32 get_RTC0_CLK_Frequency(void);
static uint32 get_SAI0_CLK_Frequency(void);
static uint32 get_SAI1_CLK_Frequency(void);
static uint32 get_SEMA42_CLK_Frequency(void);
static uint32 get_SIUL0_CLK_Frequency(void);
static uint32 get_STCU0_CLK_Frequency(void);
static uint32 get_STMA_CLK_Frequency(void);
static uint32 get_STM0_CLK_Frequency(void);
#ifdef FEATURE_CLOCK_IP_HAS_STMB_CLK
static uint32 get_STMB_CLK_Frequency(void);
#endif
#ifdef FEATURE_CLOCK_IP_HAS_STM1_CLK
static uint32 get_STM1_CLK_Frequency(void);
#endif
static uint32 get_SWT0_CLK_Frequency(void);
static uint32 get_SWT1_CLK_Frequency(void);
static uint32 get_TCM_CM7_0_CLK_Frequency(void);
static uint32 get_TCM_CM7_1_CLK_Frequency(void);
static uint32 get_TEMPSENSE_CLK_Frequency(void);
static uint32 get_TRACE_CLK_Frequency(void);
static uint32 get_TRGMUX0_CLK_Frequency(void);
static uint32 get_TSENSE0_CLK_Frequency(void);
static uint32 get_WKPU0_CLK_Frequency(void);
const consumerClockCallback consumerClockCallbacks[CONSUMER_CALLBACKS_COUNT] =
{
get_ADC0_CLK_Frequency,
get_ADC1_CLK_Frequency,
get_ADC2_CLK_Frequency,
get_BCTU0_CLK_Frequency,
get_CLKOUT_STANDBY_CLK_Frequency,
get_CMP0_CLK_Frequency,
get_CMP1_CLK_Frequency,
get_CMP2_CLK_Frequency,
get_CRC0_CLK_Frequency,
get_DCM0_CLK_Frequency,
get_DMAMUX0_CLK_Frequency,
get_DMAMUX1_CLK_Frequency,
get_EDMA0_CLK_Frequency,
get_EDMA0_TCD0_CLK_Frequency,
get_EDMA0_TCD10_CLK_Frequency,
get_EDMA0_TCD11_CLK_Frequency,
get_EDMA0_TCD12_CLK_Frequency,
get_EDMA0_TCD13_CLK_Frequency,
get_EDMA0_TCD14_CLK_Frequency,
get_EDMA0_TCD15_CLK_Frequency,
get_EDMA0_TCD16_CLK_Frequency,
get_EDMA0_TCD17_CLK_Frequency,
get_EDMA0_TCD18_CLK_Frequency,
get_EDMA0_TCD19_CLK_Frequency,
get_EDMA0_TCD1_CLK_Frequency,
get_EDMA0_TCD20_CLK_Frequency,
get_EDMA0_TCD21_CLK_Frequency,
get_EDMA0_TCD22_CLK_Frequency,
get_EDMA0_TCD23_CLK_Frequency,
get_EDMA0_TCD24_CLK_Frequency,
get_EDMA0_TCD25_CLK_Frequency,
get_EDMA0_TCD26_CLK_Frequency,
get_EDMA0_TCD27_CLK_Frequency,
get_EDMA0_TCD28_CLK_Frequency,
get_EDMA0_TCD29_CLK_Frequency,
get_EDMA0_TCD2_CLK_Frequency,
get_EDMA0_TCD30_CLK_Frequency,
get_EDMA0_TCD31_CLK_Frequency,
get_EDMA0_TCD3_CLK_Frequency,
get_EDMA0_TCD4_CLK_Frequency,
get_EDMA0_TCD5_CLK_Frequency,
get_EDMA0_TCD6_CLK_Frequency,
get_EDMA0_TCD7_CLK_Frequency,
get_EDMA0_TCD8_CLK_Frequency,
get_EDMA0_TCD9_CLK_Frequency,
get_EIM0_CLK_Frequency,
get_EMAC_RX_CLK_Frequency,
get_EMAC0_RX_CLK_Frequency,
get_EMAC_TS_CLK_Frequency,
get_EMAC0_TS_CLK_Frequency,
get_EMAC_TX_CLK_Frequency,
get_EMAC0_TX_CLK_Frequency,
get_EMIOS0_CLK_Frequency,
get_EMIOS1_CLK_Frequency,
get_EMIOS2_CLK_Frequency,
get_ERM0_CLK_Frequency,
get_FLASH0_CLK_Frequency,
get_FLEXCANA_CLK_Frequency,
get_FLEXCAN0_CLK_Frequency,
get_FLEXCAN1_CLK_Frequency,
get_FLEXCAN2_CLK_Frequency,
get_FLEXCANB_CLK_Frequency,
get_FLEXCAN3_CLK_Frequency,
get_FLEXCAN4_CLK_Frequency,
get_FLEXCAN5_CLK_Frequency,
get_FLEXIO0_CLK_Frequency,
get_INTM_CLK_Frequency,
get_LCU0_CLK_Frequency,
get_LCU1_CLK_Frequency,
get_LPI2C0_CLK_Frequency,
get_LPI2C1_CLK_Frequency,
get_LPSPI0_CLK_Frequency,
get_LPSPI1_CLK_Frequency,
get_LPSPI2_CLK_Frequency,
get_LPSPI3_CLK_Frequency,
get_LPSPI4_CLK_Frequency,
get_LPSPI5_CLK_Frequency,
get_LPUART0_CLK_Frequency,
get_LPUART10_CLK_Frequency,
get_LPUART11_CLK_Frequency,
get_LPUART12_CLK_Frequency,
get_LPUART13_CLK_Frequency,
get_LPUART14_CLK_Frequency,
get_LPUART15_CLK_Frequency,
get_LPUART1_CLK_Frequency,
get_LPUART2_CLK_Frequency,
get_LPUART3_CLK_Frequency,
get_LPUART4_CLK_Frequency,
get_LPUART5_CLK_Frequency,
get_LPUART6_CLK_Frequency,
get_LPUART7_CLK_Frequency,
get_LPUART8_CLK_Frequency,
get_LPUART9_CLK_Frequency,
get_MSCM_CLK_Frequency,
get_MUA_CLK_Frequency,
get_MUB_CLK_Frequency,
get_PIT0_CLK_Frequency,
get_PIT1_CLK_Frequency,
get_PIT2_CLK_Frequency,
get_QSPI0_RAM_CLK_Frequency,
get_QSPI_SFCK_CLK_Frequency,
get_QSPI0_SFCK_CLK_Frequency,
get_QSPI0_TX_MEM_CLK_Frequency,
get_RTC_CLK_Frequency,
get_RTC0_CLK_Frequency,
get_SAI0_CLK_Frequency,
get_SAI1_CLK_Frequency,
get_SEMA42_CLK_Frequency,
get_SIUL0_CLK_Frequency,
get_STCU0_CLK_Frequency,
get_STMA_CLK_Frequency,
get_STM0_CLK_Frequency,
#ifdef FEATURE_CLOCK_IP_HAS_STMB_CLK
get_STMB_CLK_Frequency,
#endif
#ifdef FEATURE_CLOCK_IP_HAS_STM1_CLK
get_STM1_CLK_Frequency,
#endif
get_SWT0_CLK_Frequency,
get_SWT1_CLK_Frequency,
get_TCM_CM7_0_CLK_Frequency,
get_TCM_CM7_1_CLK_Frequency,
get_TEMPSENSE_CLK_Frequency,
get_TRACE_CLK_Frequency,
get_TRGMUX0_CLK_Frequency,
get_TSENSE0_CLK_Frequency,
get_WKPU0_CLK_Frequency,
};
static uint32 get_ADC0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_ADC1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_ADC2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_BCTU0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_DMAMUX0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_DMAMUX1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD10_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD11_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD12_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD13_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD14_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD15_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD16_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD17_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD18_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD19_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD20_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD21_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD22_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD23_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD24_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD25_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD26_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD27_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD28_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD29_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD30_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD31_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD3_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD4_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD5_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD6_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD7_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD8_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EDMA0_TCD9_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EMIOS0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EMIOS1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_EMIOS2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_LCU0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_LCU1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_TCM_CM7_0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_TCM_CM7_1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_TEMPSENSE_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[CORE_CLK]];
}
static uint32 get_CMP0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_CMP1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_CMP2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_EIM0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_ERM0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_FLASH0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPI2C0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPI2C1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPSPI1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPSPI2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPSPI3_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPSPI4_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPSPI5_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART10_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART11_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART12_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART13_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART14_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART15_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART3_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART4_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART5_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART6_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART7_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_LPUART9_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_MUA_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_MUB_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_PIT0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_PIT1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_PIT2_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_SAI0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_SAI1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_STCU0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_TRGMUX0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_TSENSE0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_WKPU0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_SLOW_CLK]];
}
static uint32 get_CRC0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_FLEXIO0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_INTM_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_LPSPI0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_LPUART0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_LPUART8_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_MSCM_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_SEMA42_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[AIPS_PLAT_CLK]];
}
static uint32 get_DCM0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[DCM_CLK]];
}
static uint32 get_QSPI0_RAM_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[QSPI_MEM_CLK]];
}
static uint32 get_QSPI0_TX_MEM_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[QSPI_MEM_CLK]];
}
static uint32 get_SIUL0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[FIRC_CLK]];
}
static uint32 get_SWT0_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[SIRC_CLK]];
}
static uint32 get_SWT1_CLK_Frequency(void) {
/* Retrun frequency of a given clock */
return bufferFreqs[freqPointers[SIRC_CLK]];
}
static uint32 get_CLKOUT_STANDBY_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][5U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][5U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][5U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC_RX_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][7U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][7U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][7U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC0_RX_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][7U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][7U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][7U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC_TS_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][9U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][9U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][9U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC0_TS_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][9U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][9U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][9U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC_TX_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][8U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][8U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][8U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_EMAC0_TX_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][8U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][8U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][8U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCANA_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][3U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN0_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][3U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN1_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][3U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN2_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][3U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][3U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCANB_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][4U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN3_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][4U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN4_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][4U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_FLEXCAN5_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][4U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][4U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_QSPI_SFCK_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][10U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][10U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][10U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_QSPI0_SFCK_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][10U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][10U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][10U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_RTC_CLK_Frequency(void) {
return 0U;
}
static uint32 get_RTC0_CLK_Frequency(void) {
return 0U;
}
static uint32 get_STMA_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][1U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][1U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][1U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
static uint32 get_STM0_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][1U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][1U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][1U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
#ifdef FEATURE_CLOCK_IP_HAS_STMB_CLK
static uint32 get_STMB_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][2U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][2U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][2U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
#endif
#ifdef FEATURE_CLOCK_IP_HAS_STM1_CLK
static uint32 get_STM1_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][2U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][2U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][2U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
#endif
static uint32 get_TRACE_CLK_Frequency(void) {
uint32 frequency;
frequency = bufferFreqs[freqPointers[hardwareValue_selectorEntry[((cgm[0U][11U]->CSS & MC_CGM_MUX_CSS_SELSTAT_MASK) >> MC_CGM_MUX_CSS_SELSTAT_SHIFT)]]]; /* Selector value */
frequency &= enableDisableMask[((cgm[0U][11U]->divider[0U] & MC_CGM_MUX_DC_DE_MASK) >> MC_CGM_MUX_DC_DE_SHIFT)]; /* Divider enable/disable */
frequency /= (((cgm[0U][11U]->divider[0U] & MC_CGM_MUX_DC_DIV_MASK) >> MC_CGM_MUX_DC_DIV_SHIFT) + (uint32)1U); /* Apply divider value */
return frequency;
}
#if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
void SpecificSetUserAccessAllowed(void)
{
/* PLLDIG SetUserAccessAllowed */
#if ( defined(MCAL_PLLDIG_REG_PROT_AVAILABLE))
#if (STD_ON == MCAL_PLLDIG_REG_PROT_AVAILABLE)
#if (defined(PLL_BASE))
/* Check clock status for PLL */
if (McMeGetPllStatus() == FALSE)
{
McMeEnablePll();
}
SET_USER_ACCESS_ALLOWED(PLL_BASE, PLLDIG_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_PLLDIG_REG_PROT_AVAILABLE */
/* FXOSC SetUserAccessAllowed */
#if (defined(MCAL_FXOSC_REG_PROT_AVAILABLE))
#if (STD_ON == MCAL_FXOSC_REG_PROT_AVAILABLE)
#if (defined(FXOSC_BASE))
SET_USER_ACCESS_ALLOWED(FXOSC_BASE, FXOSC_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_FXOSC_REG_PROT_AVAILABLE */
/* MC_CGM SetUserAccessAllowed */
#if ( defined(MCAL_MC_CGM_REG_PROT_AVAILABLE))
#if (STD_ON == MCAL_MC_CGM_REG_PROT_AVAILABLE)
#if (defined(MC_CGM_BASE))
SET_USER_ACCESS_ALLOWED(MC_CGM_BASE, MC_CGM_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_MC_CGM_REG_PROT_AVAILABLE */
/* CMU SetUserAccessAllowed */
#if (defined(MCAL_CMU_REG_PROT_AVAILABLE))
#if (STD_ON == MCAL_CMU_REG_PROT_AVAILABLE)
#if (defined(CMU_0_BASE)) || (defined(CMU_3_BASE)) || (defined(CMU_4_BASE)) || (defined(CMU_5_BASE))
/* Check clock status for CMU0 */
if (McMeGetCmuStatus() == FALSE)
{
McMeEnableCmu();
}
#endif
#if (defined(CMU_0_BASE))
/* Check clock status for CMU0 */
SET_USER_ACCESS_ALLOWED(CMU_0_BASE, CMU_PROT_MEM_U32);
#endif
#if (defined(CMU_3_BASE))
/* Check clock status for CMU3 */
SET_USER_ACCESS_ALLOWED(CMU_3_BASE, CMU_PROT_MEM_U32);
#endif
#if (defined(CMU_4_BASE))
/* Check clock status for CMU3 */
SET_USER_ACCESS_ALLOWED(CMU_4_BASE, CMU_PROT_MEM_U32);
#endif
#if (defined(CMU_5_BASE))
/* Check clock status for CMU5 */
SET_USER_ACCESS_ALLOWED(CMU_5_BASE, CMU_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_CMU_REG_PROT_AVAILABLE */
/* SRAM SetUserAccessAllowed */
#if (defined(MCAL_PRAMC_REG_PROT_AVAILABLE))
#if (STD_ON == MCAL_PRAMC_REG_PROT_AVAILABLE)
#if (defined(PRAMC_0_BASE))
SET_USER_ACCESS_ALLOWED(PRAMC_0_BASE, PRAMC_PROT_MEM_U32);
#endif
#if (defined(PRAMC_1_BASE))
SET_USER_ACCESS_ALLOWED(PRAMC_1_BASE, PRAMC_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_PRAMC_REG_PROT_AVAILABLE */
/* MC_ME SetUserAccessAllowed */
#if (defined(MCAL_MC_ME_REG_PROT_AVAILABLE ))
#if (STD_ON == MCAL_MC_ME_REG_PROT_AVAILABLE )
#if (defined(MC_ME_BASE))
SET_USER_ACCESS_ALLOWED(MC_ME_BASE, MC_ME_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_MC_ME_REG_PROT_AVAILABLE */
/* FLASH_C40ASF SetUserAccessAllowed */
#if (defined(MCAL_C40ASF_REG_PROT_AVAILABLE ))
#if (STD_ON == MCAL_C40ASF_REG_PROT_AVAILABLE )
#if (defined(FLASH_BASE))
SET_USER_ACCESS_ALLOWED(FLASH_BASE, C40ASF_PROT_MEM_U32);
#endif
#endif
#endif /* MCAL_C40ASF_REG_PROT_AVAILABLE */
}
#endif
#endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
/* Clock stop section code */
#define MCU_STOP_SEC_CODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#ifdef FEATURE_CLOCK_IP_HAS_RAM_WAIT_STATES
/* Clock start rom section code */
#define MCU_START_SEC_CODE_AC
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static void PRAMC_SetRamIWS(void)
{
/* CORE_CLK frequency is greater than 80MHz or CORE_CLK and AIPS_PLAT_CLK have the same frequency */
if ((configuredCoreClock > 80000000U) || (configuredCoreClock == configuredAipsPlatClock))
{
/* Enable RAM WS */
PRAMC_0->PRCR1 |= PRAMC_PRCR1_FT_DIS_MASK;
PRAMC_1->PRCR1 |= PRAMC_PRCR1_FT_DIS_MASK;
}
else
{
/* Disable RAM WS */
PRAMC_0->PRCR1 &= ~PRAMC_PRCR1_FT_DIS_MASK;
PRAMC_1->PRCR1 &= ~PRAMC_PRCR1_FT_DIS_MASK;
}
}
/* Clock stop rom section code */
#define MCU_STOP_SEC_CODE_AC
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#endif
#ifdef FEATURE_CLOCK_IP_HAS_FLASH_WAIT_STATES
/* Clock start ram section code */
#define MCU_START_SEC_RAMCODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
static void CodeInRam_SetFlashWaitStates(void)
{
uint32 rwsc_setting = 0U;
if (configuredCoreClock <= 167000000U)
{
if (configuredCoreClock <= 66000000U)
{
rwsc_setting = 1U;
}
else if (configuredCoreClock <= 100000000U)
{
rwsc_setting = 2U;
}
else if (configuredCoreClock <= 133000000U)
{
rwsc_setting = 3U;
}
else
{
rwsc_setting = 4U;
}
}
else
{
if (configuredCoreClock <= 200000000U)
{
rwsc_setting = 5U;
}
else if (configuredCoreClock <= 233000000U)
{
rwsc_setting = 6U;
}
else if (configuredCoreClock <= 250000000U)
{
rwsc_setting = 7U;
}
else
{
rwsc_setting = 7U;
}
}
FLASH->CTL &= ~FLASH_CTL_RWSL_MASK;
FLASH->CTL &= ~FLASH_CTL_RWSC_MASK;
FLASH->CTL |= FLASH_CTL_RWSC(rwsc_setting);
}
/* Clock stop ram section code */
#define MCU_STOP_SEC_RAMCODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start initialized section data */
#define MCU_START_SEC_VAR_INIT_UNSPECIFIED
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
typedef void (*SetFlashWaitStatesCallbackType)(void);
SetFlashWaitStatesCallbackType SetFlashWaitStatesCallback = CodeInRam_SetFlashWaitStates; /* Set Flash Wait States callback */
/* Clock stop initialized section data */
#define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
/* Clock start section code */
#define MCU_START_SEC_CODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
void FLASH_SetFlashIWS(void)
{
SetFlashWaitStatesCallback();
}
/* Clock stop section code */
#define MCU_STOP_SEC_CODE
/**
* @violates @ref Clock_Ip_Specific_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*/
#include "Mcu_MemMap.h"
#endif
#endif /* (S32K3XX) */
/*! @}*/
/*******************************************************************************
* EOF
******************************************************************************/
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