mirror of
https://github.com/Dev-KATECH/ADM.git
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301 lines
13 KiB
C
301 lines
13 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral :
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0_D2102_ASR_REL_4_4_REV_0000_20201127
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*
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* (c) Copyright 2020 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file Clock_Ip_Cfg_Defines.h
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* @version 0.9.0
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*
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* @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template.
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* @details Code template for Post-Build(PB) configuration file generation.
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*
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* @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver
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* @{
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*/
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#ifndef CLOCK_IP_CFG_DEFINES_H
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#define CLOCK_IP_CFG_DEFINES_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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INCLUDE FILES
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1) system and project includes
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2) needed interfaces from external units
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3) internal and external interfaces from this unit
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==================================================================================================*/
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/*==================================================================================================
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SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define CLOCK_IP_CFG_DEFINES_VENDOR_ID 43
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#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4
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#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 4
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#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0
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#define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION 0
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#define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION 9
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#define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION 0
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/*==================================================================================================
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DEFINES AND MACROS
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==================================================================================================*/
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/**
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* @brief Max number of internal oscillators
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*/
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#define FEATURE_CLOCK_IRCOSCS_COUNT (2U)
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/**
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* @brief Max number of external oscillators
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*/
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#define FEATURE_CLOCK_XOSCS_COUNT (2U)
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/**
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* @brief Max number of pll devices
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*/
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#define FEATURE_CLOCK_PLLS_COUNT (1U)
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/**
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* @brief Max number of selectors
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*/
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#define FEATURE_CLOCK_SELECTORS_COUNT (12U)
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/**
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* @brief Max number of dividers
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*/
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#define FEATURE_CLOCK_DIVIDERS_COUNT (21U)
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/**
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* @brief Max number of divider triggers
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*/
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#define FEATURE_CLOCK_DIVIDER_TRIGGERS_COUNT (1U)
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/**
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* @brief Max number of fractional dividers
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*/
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#define FEATURE_CLOCK_FRACTIONAL_DIVIDERS_COUNT (0U)
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/**
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* @brief Max number of external clocks
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*/
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#define FEATURE_CLOCK_EXT_CLKS_COUNT (2U)
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/**
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* @brief Max number of pcfs
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*/
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#define FEATURE_CLOCK_PCFS_COUNT (0U)
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/**
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* @brief Max number of clock gates
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*/
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#define FEATURE_CLOCK_GATES_COUNT (105U)
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/**
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* @brief Max number of clock monitoring units
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*/
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#define FEATURE_CLOCK_CMUS_COUNT (4U)
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/**
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* @brief Max number of specific peripheral (eMIOS) units
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*/
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#define FEATURE_CLOCK_SPECIFIC_PERIPH_COUNT (0U)
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/**
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* @brief Max number of consumer clocks
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*/
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#define FEATURE_CLOCK_CONSUMER_COUNT (123U)
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/**
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* @brief Supported power mode.
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*/
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#define FEATURE_CLOCK_IP_HAS_RUN_MODE 0U
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/**
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* @brief Supported clocks.
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*/
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#define FEATURE_CLOCK_IP_HAS_FIRC_CLK 0U
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#define FEATURE_CLOCK_IP_HAS_FIRC_STANDBY_CLK 1U
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#define FEATURE_CLOCK_IP_HAS_SIRC_CLK 2U
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#define FEATURE_CLOCK_IP_HAS_SIRC_STANDBY_CLK 3U
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#define FEATURE_CLOCK_IP_HAS_FXOSC_CLK 4U
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#define FEATURE_CLOCK_IP_HAS_SXOSC_CLK 5U
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#define FEATURE_CLOCK_IP_HAS_PLL_CLK 6U
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#define FEATURE_CLOCK_IP_HAS_PLL_POSTDIV_CLK 7U
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#define FEATURE_CLOCK_IP_HAS_PLL_PHI0_CLK 8U
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#define FEATURE_CLOCK_IP_HAS_PLL_PHI1_CLK 9U
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#define FEATURE_CLOCK_IP_HAS_EMAC_MII_RX_CLK 10U
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#define FEATURE_CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK 11U
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#define FEATURE_CLOCK_IP_HAS_SCS_CLK 12U
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#define FEATURE_CLOCK_IP_HAS_CORE_CLK 13U
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#define FEATURE_CLOCK_IP_HAS_AIPS_PLAT_CLK 14U
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#define FEATURE_CLOCK_IP_HAS_AIPS_SLOW_CLK 15U
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#define FEATURE_CLOCK_IP_HAS_HSE_CLK 16U
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#define FEATURE_CLOCK_IP_HAS_DCM_CLK 17U
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#define FEATURE_CLOCK_IP_HAS_LBIST_CLK 18U
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#define FEATURE_CLOCK_IP_HAS_QSPI_MEM_CLK 19U
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#define FEATURE_CLOCK_IP_HAS_CLKOUT_RUN_CLK 20U
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#define FEATURE_CLOCK_PRODUCERS_NO 21U
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#define FEATURE_CLOCK_IP_HAS_ADC0_CLK 22U
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#define FEATURE_CLOCK_IP_HAS_ADC1_CLK 23U
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#define FEATURE_CLOCK_IP_HAS_ADC2_CLK 24U
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#define FEATURE_CLOCK_IP_HAS_BCTU0_CLK 25U
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#define FEATURE_CLOCK_IP_HAS_CLKOUT_STANDBY_CLK 26U
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#define FEATURE_CLOCK_IP_HAS_CMP0_CLK 27U
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#define FEATURE_CLOCK_IP_HAS_CMP1_CLK 28U
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#define FEATURE_CLOCK_IP_HAS_CMP2_CLK 29U
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#define FEATURE_CLOCK_IP_HAS_CRC0_CLK 30U
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#define FEATURE_CLOCK_IP_HAS_DCM0_CLK 31U
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#define FEATURE_CLOCK_IP_HAS_DMAMUX0_CLK 32U
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#define FEATURE_CLOCK_IP_HAS_DMAMUX1_CLK 33U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_CLK 34U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD0_CLK 35U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD10_CLK 36U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD11_CLK 37U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD12_CLK 38U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD13_CLK 39U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD14_CLK 40U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD15_CLK 41U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD16_CLK 42U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD17_CLK 43U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD18_CLK 44U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD19_CLK 45U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD1_CLK 46U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD20_CLK 47U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD21_CLK 48U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD22_CLK 49U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD23_CLK 50U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD24_CLK 51U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD25_CLK 52U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD26_CLK 53U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD27_CLK 54U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD28_CLK 55U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD29_CLK 56U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD2_CLK 57U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD30_CLK 58U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD31_CLK 59U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD3_CLK 60U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD4_CLK 61U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD5_CLK 62U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD6_CLK 63U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD7_CLK 64U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD8_CLK 65U
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#define FEATURE_CLOCK_IP_HAS_EDMA0_TCD9_CLK 66U
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#define FEATURE_CLOCK_IP_HAS_EIM0_CLK 67U
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#define FEATURE_CLOCK_IP_HAS_EMAC_RX_CLK 68U
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#define FEATURE_CLOCK_IP_HAS_EMAC0_RX_CLK 69U
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#define FEATURE_CLOCK_IP_HAS_EMAC_TS_CLK 70U
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#define FEATURE_CLOCK_IP_HAS_EMAC0_TS_CLK 71U
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#define FEATURE_CLOCK_IP_HAS_EMAC_TX_CLK 72U
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#define FEATURE_CLOCK_IP_HAS_EMAC0_TX_CLK 73U
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#define FEATURE_CLOCK_IP_HAS_EMIOS0_CLK 74U
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#define FEATURE_CLOCK_IP_HAS_EMIOS1_CLK 75U
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#define FEATURE_CLOCK_IP_HAS_EMIOS2_CLK 76U
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#define FEATURE_CLOCK_IP_HAS_ERM0_CLK 77U
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#define FEATURE_CLOCK_IP_HAS_FLASH0_CLK 78U
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#define FEATURE_CLOCK_IP_HAS_FLEXCANA_CLK 79U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN0_CLK 80U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN1_CLK 81U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN2_CLK 82U
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#define FEATURE_CLOCK_IP_HAS_FLEXCANB_CLK 83U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN3_CLK 84U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN4_CLK 85U
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#define FEATURE_CLOCK_IP_HAS_FLEXCAN5_CLK 86U
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#define FEATURE_CLOCK_IP_HAS_FLEXIO0_CLK 87U
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#define FEATURE_CLOCK_IP_HAS_INTM_CLK 88U
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#define FEATURE_CLOCK_IP_HAS_LCU0_CLK 89U
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#define FEATURE_CLOCK_IP_HAS_LCU1_CLK 90U
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#define FEATURE_CLOCK_IP_HAS_LPI2C0_CLK 91U
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#define FEATURE_CLOCK_IP_HAS_LPI2C1_CLK 92U
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#define FEATURE_CLOCK_IP_HAS_LPSPI0_CLK 93U
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#define FEATURE_CLOCK_IP_HAS_LPSPI1_CLK 94U
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#define FEATURE_CLOCK_IP_HAS_LPSPI2_CLK 95U
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#define FEATURE_CLOCK_IP_HAS_LPSPI3_CLK 96U
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#define FEATURE_CLOCK_IP_HAS_LPSPI4_CLK 97U
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#define FEATURE_CLOCK_IP_HAS_LPSPI5_CLK 98U
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#define FEATURE_CLOCK_IP_HAS_LPUART0_CLK 99U
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#define FEATURE_CLOCK_IP_HAS_LPUART10_CLK 100U
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#define FEATURE_CLOCK_IP_HAS_LPUART11_CLK 101U
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#define FEATURE_CLOCK_IP_HAS_LPUART12_CLK 102U
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#define FEATURE_CLOCK_IP_HAS_LPUART13_CLK 103U
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#define FEATURE_CLOCK_IP_HAS_LPUART14_CLK 104U
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#define FEATURE_CLOCK_IP_HAS_LPUART15_CLK 105U
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#define FEATURE_CLOCK_IP_HAS_LPUART1_CLK 106U
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#define FEATURE_CLOCK_IP_HAS_LPUART2_CLK 107U
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#define FEATURE_CLOCK_IP_HAS_LPUART3_CLK 108U
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#define FEATURE_CLOCK_IP_HAS_LPUART4_CLK 109U
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#define FEATURE_CLOCK_IP_HAS_LPUART5_CLK 110U
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#define FEATURE_CLOCK_IP_HAS_LPUART6_CLK 111U
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#define FEATURE_CLOCK_IP_HAS_LPUART7_CLK 112U
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#define FEATURE_CLOCK_IP_HAS_LPUART8_CLK 113U
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#define FEATURE_CLOCK_IP_HAS_LPUART9_CLK 114U
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#define FEATURE_CLOCK_IP_HAS_MSCM_CLK 115U
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#define FEATURE_CLOCK_IP_HAS_MUA_CLK 116U
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#define FEATURE_CLOCK_IP_HAS_MUB_CLK 117U
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#define FEATURE_CLOCK_IP_HAS_PIT0_CLK 118U
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#define FEATURE_CLOCK_IP_HAS_PIT1_CLK 119U
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#define FEATURE_CLOCK_IP_HAS_PIT2_CLK 120U
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#define FEATURE_CLOCK_IP_HAS_QSPI0_RAM_CLK 121U
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#define FEATURE_CLOCK_IP_HAS_QSPI_SFCK_CLK 122U
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#define FEATURE_CLOCK_IP_HAS_QSPI0_SFCK_CLK 123U
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#define FEATURE_CLOCK_IP_HAS_QSPI0_TX_MEM_CLK 124U
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#define FEATURE_CLOCK_IP_HAS_RTC_CLK 125U
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#define FEATURE_CLOCK_IP_HAS_RTC0_CLK 126U
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#define FEATURE_CLOCK_IP_HAS_SAI0_CLK 127U
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#define FEATURE_CLOCK_IP_HAS_SAI1_CLK 128U
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#define FEATURE_CLOCK_IP_HAS_SEMA42_CLK 129U
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#define FEATURE_CLOCK_IP_HAS_SIUL0_CLK 130U
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#define FEATURE_CLOCK_IP_HAS_STCU0_CLK 131U
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#define FEATURE_CLOCK_IP_HAS_STMA_CLK 132U
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#define FEATURE_CLOCK_IP_HAS_STM0_CLK 133U
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#define FEATURE_CLOCK_IP_HAS_STMB_CLK 134U
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#define FEATURE_CLOCK_IP_HAS_STM1_CLK 135U
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#define FEATURE_CLOCK_IP_HAS_SWT0_CLK 136U
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#define FEATURE_CLOCK_IP_HAS_SWT1_CLK 137U
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#define FEATURE_CLOCK_IP_HAS_TCM_CM7_0_CLK 138U
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#define FEATURE_CLOCK_IP_HAS_TCM_CM7_1_CLK 139U
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#define FEATURE_CLOCK_IP_HAS_TEMPSENSE_CLK 140U
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#define FEATURE_CLOCK_IP_HAS_TRACE_CLK 141U
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#define FEATURE_CLOCK_IP_HAS_TRGMUX0_CLK 142U
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#define FEATURE_CLOCK_IP_HAS_TSENSE0_CLK 143U
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#define FEATURE_CLOCK_IP_HAS_WKPU0_CLK 144U
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#define FEATURE_CLOCKS_NO 145U
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/*==================================================================================================
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ENUMS
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==================================================================================================*/
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/*==================================================================================================
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STRUCTURES AND OTHER TYPEDEFS
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==================================================================================================*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */
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/** @} */
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