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ADM/GW/RTD/src/Adc_Sar_Ip_HwAccess.h
S2-CHICKEN 77297108b6 VCU C code first commit
2024-08-08 10:00:15 +09:00

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/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral : ADC_SAR
* Dependencies : none
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
#ifndef ADC_SAR_HW_ACCESS_H
#define ADC_SAR_HW_ACCESS_H
/**
* @file
*
* @internal
* @addtogroup adc_sar_ip Adc Sar IPL
* @{
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macro defines a bitmask used to access status flags.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* Function-like macros are used to calculate bit positions based on channel index
*
*/
#include "StandardTypes.h"
#include "Adc_Sar_Ip_DeviceRegisters.h"
/*******************************************************************************
* Source file version information
******************************************************************************/
#define ADC_SAR_IP_VENDOR_ID_HWACCESS_H 43
#define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H 4
#define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H 4
#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H 0
#define ADC_SAR_IP_SW_MAJOR_VERSION_HWACCESS_H 0
#define ADC_SAR_IP_SW_MINOR_VERSION_HWACCESS_H 9
#define ADC_SAR_IP_SW_PATCH_VERSION_HWACCESS_H 0
/*******************************************************************************
* File version checks
******************************************************************************/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if Adc_Sar_Ip_HwAccess.h file and StandardTypes.h file are of the same Autosar version */
#if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MAJOR_VERSION) || \
(ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MINOR_VERSION) \
)
#error "AutoSar Version Numbers of Adc_Sar_Ip_HwAccess.h and StandardTypes.h are different"
#endif
#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
/* Check if Adc_Sar_Ip_HwAccess.h file and Adc_Sar_Ip_DeviceRegisters.h file are of the same vendor */
#if (ADC_SAR_IP_VENDOR_ID_HWACCESS_H != ADC_SAR_IP_VENDOR_ID_DEVICEREGISTERS_H)
#error "Adc_Sar_Ip_HwAccess.h and Adc_Sar_Ip_DeviceRegisters.h have different vendor ids"
#endif
/* Check if Adc_Sar_Ip_HwAccess.h file and Adc_Sar_Ip_DeviceRegisters.h file are of the same Autosar version */
#if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_DEVICEREGISTERS_H) || \
(ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_DEVICEREGISTERS_H) || \
(ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_DEVICEREGISTERS_H) \
)
#error "AutoSar Version Numbers of Adc_Sar_Ip_HwAccess.h and Adc_Sar_Ip_DeviceRegisters.h are different"
#endif
/* Check if Adc_Sar_Ip_HwAccess.h file and Adc_Sar_Ip_DeviceRegisters.h file are of the same Software version */
#if ((ADC_SAR_IP_SW_MAJOR_VERSION_HWACCESS_H != ADC_SAR_IP_SW_MAJOR_VERSION_DEVICEREGISTERS_H) || \
(ADC_SAR_IP_SW_MINOR_VERSION_HWACCESS_H != ADC_SAR_IP_SW_MINOR_VERSION_DEVICEREGISTERS_H) || \
(ADC_SAR_IP_SW_PATCH_VERSION_HWACCESS_H != ADC_SAR_IP_SW_PATCH_VERSION_DEVICEREGISTERS_H) \
)
#error "Software Version Numbers of Adc_Sar_Ip_HwAccess.h and Adc_Sar_Ip_DeviceRegisters.h are different"
#endif
/*******************************************************************************
* Defines
******************************************************************************/
/* Define the hardware register size when calculating bit positions */
#define ADC_HW_REG_SIZE (32u)
/* Definitions to compute bit positions from channel index */
#define CHAN_2_VECT(CHNIDX) ((CHNIDX) / ADC_HW_REG_SIZE)
#define CHAN_2_BIT(CHNIDX) ((CHNIDX) % ADC_HW_REG_SIZE)
/* Define ADC Channel Groups */
#define ADC_GROUP_0 (0u)
#define ADC_GROUP_1 (1u)
#if ((ADC_SAR_CIMR_COUNT > 2u) || (ADC_SAR_CTR_COUNT > 2u))
/* Define the group only if it exists in hardware */
#define ADC_GROUP_2 (2u)
#endif /* ((ADC_SAR_CIMR_COUNT > 2u) || (ADC_SAR_CTR_COUNT > 2u)) */
/*******************************************************************************
* Code
******************************************************************************/
#define ADC_START_SEC_CODE
#include "Adc_MemMap.h"
static inline void Adc_Sar_Powerup(ADC_Type * const pBase)
{
pBase->MCR &= ~(ADC_MCR_PWDN(1u));
}
static inline void Adc_Sar_Powerdown(ADC_Type * const pBase)
{
pBase->MCR |= ADC_MCR_PWDN(1u);
}
static inline void Adc_Sar_EnablePresampleConversion(ADC_Type * const pBase, boolean bBypassSampling)
{
uint32 u32Pscr = pBase->PSCR;
u32Pscr &= ~(ADC_PSCR_PRECONV_MASK);
u32Pscr |= ADC_PSCR_PRECONV(bBypassSampling ? 1u : 0u);
pBase->PSCR = u32Pscr;
}
/*FUNCTION*********************************************************************
*
* Function Name : Adc_Sar_WriteThresholds
* Description : Write Watchdog low, high thresholds for a wdog register
*
*END*************************************************************************/
static inline void Adc_Sar_WriteThresholds(ADC_Type * const pBase,
uint8 u8RegisterNumber,
uint16 u16HighThreshold,
uint16 u16LowThreshold)
{
#if ADC_HAS_THRHLR_ARRAY
#if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
ADC_SAR_DEV_ASSERT(u8RegisterNumber < ADC_SAR_THRHLR_COUNT);
#endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
uint32 u32Value = ADC_THRHLR_THRH(u16HighThreshold) |
ADC_THRHLR_THRL(u16LowThreshold);
pBase->THRHLR[u8RegisterNumber] = u32Value;
#else /* ADC_HAS_THRHLR_ARRAY == 0 */
uint32 u32Value = ADC_THRHLR0_THRH(u16HighThreshold) |
ADC_THRHLR0_THRL(u16LowThreshold);
switch (u8RegisterNumber)
{
case 0:
pBase->THRHLR0 = u32Value;
break;
case 1:
pBase->THRHLR1 = u32Value;
break;
case 2:
pBase->THRHLR2 = u32Value;
break;
case 3:
pBase->THRHLR3 = u32Value;
break;
case 4:
pBase->THRHLR4 = u32Value;
break;
case 5:
pBase->THRHLR5 = u32Value;
break;
#if (ADC_SAR_THRHLR_COUNT > 6u)
case 6:
pBase->THRHLR6 = u32Value;
break;
case 7:
pBase->THRHLR7 = u32Value;
break;
#if (ADC_SAR_THRHLR_COUNT > 8u)
case 8:
pBase->THRHLR8 = u32Value;
break;
case 9:
pBase->THRHLR9 = u32Value;
break;
case 10:
pBase->THRHLR10 = u32Value;
break;
case 11:
pBase->THRHLR11 = u32Value;
break;
case 12:
pBase->THRHLR12 = u32Value;
break;
case 13:
pBase->THRHLR13 = u32Value;
break;
case 14:
pBase->THRHLR14 = u32Value;
break;
case 15:
pBase->THRHLR15 = u32Value;
break;
#endif /* (ADC_SAR_THRHLR_COUNT > 8u) */
#endif /* (ADC_SAR_THRHLR_COUNT > 6u) */
default:
; /* no-op */
break;
}
#endif /* ADC_HAS_THRHLR_ARRAY */
}
/*FUNCTION*********************************************************************
*
* Function Name : Adc_Sar_WriteChannelMapping
* Description :
*
*END*************************************************************************/
static inline void Adc_Sar_WriteChannelMapping(ADC_Type * const pBase, uint32 u32RegisterNumber, uint32 u32FieldPosition, uint32 u32Value)
{
#if (ADC_HAS_CWSELR_UNROLLED == 1u)
volatile uint32 * pCWSELR = NULL_PTR;
switch (u32RegisterNumber)
{
#if ADC_HAS_CWSELR0
case 0u:
pCWSELR = &(pBase->CWSELR0);
break;
#endif /* ADC_HAS_CWSELR0 */
#if ADC_HAS_CWSELR1
case 1u:
pCWSELR = &(pBase->CWSELR1);
break;
#endif /* ADC_HAS_CWSELR1 */
#if ADC_HAS_CWSELR2
case 2u:
pCWSELR = &(pBase->CWSELR2);
break;
#endif /* ADC_HAS_CWSELR2 */
#if ADC_HAS_CWSELR3
case 3u:
pCWSELR = &(pBase->CWSELR3);
break;
#endif /* ADC_HAS_CWSELR3 */
#if ADC_HAS_CWSELR4
case 4u:
pCWSELR = &(pBase->CWSELR4);
break;
#endif /* ADC_HAS_CWSELR4 */
#if ADC_HAS_CWSELR5
case 5u:
pCWSELR = &(pBase->CWSELR5);
break;
#endif /* ADC_HAS_CWSELR5 */
#if ADC_HAS_CWSELR6
case 6u:
pCWSELR = &(pBase->CWSELR6);
break;
#endif /* ADC_HAS_CWSELR6 */
#if ADC_HAS_CWSELR7
case 7u:
pCWSELR = &(pBase->CWSELR7);
break;
#endif /* ADC_HAS_CWSELR7 */
#if ADC_HAS_CWSELR8
case 8u:
pCWSELR = &(pBase->CWSELR8);
break;
#endif /* ADC_HAS_CWSELR8 */
#if ADC_HAS_CWSELR9
case 9u:
pCWSELR = &(pBase->CWSELR9);
break;
#endif /* ADC_HAS_CWSELR9 */
#if ADC_HAS_CWSELR10
case 10u:
pCWSELR = &(pBase->CWSELR10);
break;
#endif /* ADC_HAS_CWSELR10 */
#if ADC_HAS_CWSELR11
case 11u:
pCWSELR = &(pBase->CWSELR11);
break;
#endif /* ADC_HAS_CWSELR11 */
default:
; /* the u32RegisterNumber does not exist */
#if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
ADC_SAR_DEV_ASSERT(FALSE);
#endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
break;
}
#if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
ADC_SAR_DEV_ASSERT(pCWSELR != NULL_PTR);
#endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
switch (u32FieldPosition)
{
case 0:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH0_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH0(u32Value);
break;
case 1:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH1_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH1(u32Value);
break;
case 2:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH2_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH2(u32Value);
break;
case 3:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH3_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH3(u32Value);
break;
case 4:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH4_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH4(u32Value);
break;
case 5:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH5_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH5(u32Value);
break;
case 6:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH6_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH6(u32Value);
break;
case 7:
*pCWSELR &= ~ADC_CWSELR0_WSEL_CH7_MASK;
*pCWSELR |= ADC_CWSELR0_WSEL_CH7(u32Value);
break;
default:
; /* no-op */
break;
}
#else /* ADC_HAS_CWSELR_UNROLLED == 0 */
switch (u32FieldPosition)
{
case 0:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH0_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH0(u32Value);
break;
case 1:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH1_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH1(u32Value);
break;
case 2:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH2_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH2(u32Value);
break;
case 3:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH3_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH3(u32Value);
break;
case 4:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH4_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH4(u32Value);
break;
case 5:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH5_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH5(u32Value);
break;
case 6:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH6_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH6(u32Value);
break;
case 7:
CWSELR(pBase, u32RegisterNumber) &= ~ADC_CWSELR_WSEL_CH7_MASK;
CWSELR(pBase, u32RegisterNumber) |= ADC_CWSELR_WSEL_CH7(u32Value);
break;
default:
; /* no-op */
break;
}
#endif /* (ADC_HAS_CWSELR_UNROLLED == 1u) */
}
static inline void Adc_Sar_ResetWdogCWSELR(ADC_Type * const pBase, uint8 u8CwselrId)
{
#if (ADC_HAS_CWSELR_UNROLLED == 1u)
switch (u8CwselrId)
{
#if ADC_HAS_CWSELR0
case 0u:
pBase->CWSELR0 = 0u;
break;
#endif /* ADC_HAS_CWSELR0 */
#if ADC_HAS_CWSELR1
case 1u:
pBase->CWSELR1 = 0u;
break;
#endif /* ADC_HAS_CWSELR1 */
#if ADC_HAS_CWSELR2
case 2u:
pBase->CWSELR2 = 0u;
break;
#endif /* ADC_HAS_CWSELR2 */
#if ADC_HAS_CWSELR3
case 3u:
pBase->CWSELR3 = 0u;
break;
#endif /* ADC_HAS_CWSELR3 */
#if ADC_HAS_CWSELR4
case 4u:
pBase->CWSELR4 = 0u;
break;
#endif /* ADC_HAS_CWSELR4 */
#if ADC_HAS_CWSELR5
case 5u:
pBase->CWSELR5 = 0u;
break;
#endif /* ADC_HAS_CWSELR5 */
#if ADC_HAS_CWSELR6
case 6u:
pBase->CWSELR6 = 0u;
break;
#endif /* ADC_HAS_CWSELR6 */
#if ADC_HAS_CWSELR7
case 7u:
pBase->CWSELR7 = 0u;
break;
#endif /* ADC_HAS_CWSELR7 */
#if ADC_HAS_CWSELR8
case 8u:
pBase->CWSELR8 = 0u;
break;
#endif /* ADC_HAS_CWSELR8 */
#if ADC_HAS_CWSELR9
case 9u:
pBase->CWSELR9 = 0u;
break;
#endif /* ADC_HAS_CWSELR9 */
#if ADC_HAS_CWSELR10
case 10u:
pBase->CWSELR10 = 0u;
break;
#endif /* ADC_HAS_CWSELR10 */
#if ADC_HAS_CWSELR11
case 11u:
pBase->CWSELR11 = 0u;
break;
#endif /* ADC_HAS_CWSELR11 */
default:
; /* no-op */
break;
}
#else /* ADC_HAS_CWSELR_UNROLLED == 0 */
CWSELR(pBase, u8CwselrId) = 0u;
#endif /* (ADC_HAS_CWSELR_UNROLLED == 1u) */
}
#define ADC_STOP_SEC_CODE
#include "Adc_MemMap.h"
#if defined (__cplusplus)
extern "C" {
#endif
#if defined (__cplusplus)
}
#endif
/** @} */
#endif /* ADC_SAR_HW_ACCESS_H */
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