mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 01:43:59 +09:00
579 lines
23 KiB
C
579 lines
23 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral :
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file
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*
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* @addtogroup IntCtrl_Ip
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* @{
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*/
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/*==================================================================================================
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* INCLUDE FILES
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==================================================================================================*/
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#include "IntCtrl_Ip.h"
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#include "Mcal.h"
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/*==================================================================================================
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* GLOBAL VARIABLES
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==================================================================================================*/
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extern uint32 __INT_SRAM_START[];
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/*==================================================================================================
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* LOCAL FUNCTIONS
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==================================================================================================*/
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#if ((STD_ON == INTCTRL_PLATFORM_ENABLE_USER_MODE_SUPPORT) && (defined (MCAL_ENABLE_USER_MODE_SUPPORT)))
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#define Call_IntCtrl_Ip_InstallHandlerPrivileged(eIrqNumber,pfNewHandler,pfOldHandler) \
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OsIf_Trusted_Call3params(IntCtrl_Ip_InstallHandlerPrivileged,(eIrqNumber),(pfNewHandler),(pfOldHandler))
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#define Call_IntCtrl_Ip_EnableIrqPrivileged(eIrqNumber) \
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OsIf_Trusted_Call1param(IntCtrl_Ip_EnableIrqPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_DisableIrqPrivileged(eIrqNumber) \
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OsIf_Trusted_Call1param(IntCtrl_Ip_DisableIrqPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_SetPriorityPrivileged(eIrqNumber,u8Priority) \
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OsIf_Trusted_Call2params(IntCtrl_Ip_SetPriorityPrivileged,(eIrqNumber),(u8Priority))
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#define Call_IntCtrl_Ip_GetPriorityPrivileged(eIrqNumber) \
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OsIf_Trusted_Call_Return1param(IntCtrl_Ip_GetPriorityPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_ClearPendingPrivileged(eIrqNumber) \
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OsIf_Trusted_Call1param(IntCtrl_Ip_ClearPendingPrivileged,(eIrqNumber))
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#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)
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#define Call_IntCtrl_Ip_SetPendingPrivileged(eIrqNumber) \
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OsIf_Trusted_Call1param(IntCtrl_Ip_SetPendingPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_GetPendingPrivileged(eIrqNumber) \
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OsIf_Trusted_Call_Return1param(IntCtrl_Ip_GetPendingPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_GetActivePrivileged(eIrqNumber) \
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OsIf_Trusted_Call_Return1param(IntCtrl_Ip_GetActivePrivileged,(eIrqNumber))
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#endif
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#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
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#define Call_IntCtrl_Ip_SetTargetCoresPrivileged(eIrqNumber,u8TargetCores) \
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OsIf_Trusted_Call2params(IntCtrl_Ip_SetTargetCoresPrivileged,(eIrqNumber),(u8TargetCores))
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#endif
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#if (INT_CTRL_IP_MSI_AVAILABLE == STD_ON)
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#define Call_IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged(eIrqNumber,eCpuTarget) \
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OsIf_Trusted_Call2params(IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged,(eIrqNumber),(eCpuTarget))
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#define Call_IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(eIrqNumber) \
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OsIf_Trusted_Call1param(IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged,(eIrqNumber))
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#define Call_IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(eIrqNumber) \
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OsIf_Trusted_Call_Return1param(IntCtrl_Ip_GetDirectedCpuInterruptPrivileged,(eIrqNumber))
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#endif
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#else /*STD_ON == INTCTRL_PLATFORM_ENABLE_USER_MODE_SUPPORT*/
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#define Call_IntCtrl_Ip_InstallHandlerPrivileged(eIrqNumber,pfNewHandler,pfOldHandler) \
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IntCtrl_Ip_InstallHandlerPrivileged((eIrqNumber),(pfNewHandler),(pfOldHandler))
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#define Call_IntCtrl_Ip_EnableIrqPrivileged(eIrqNumber) \
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IntCtrl_Ip_EnableIrqPrivileged((eIrqNumber))
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#define Call_IntCtrl_Ip_DisableIrqPrivileged(eIrqNumber) \
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IntCtrl_Ip_DisableIrqPrivileged((eIrqNumber))
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#define Call_IntCtrl_Ip_SetPriorityPrivileged(eIrqNumber,u8Priority) \
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IntCtrl_Ip_SetPriorityPrivileged((eIrqNumber),(u8Priority))
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#define Call_IntCtrl_Ip_GetPriorityPrivileged(eIrqNumber) \
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IntCtrl_Ip_GetPriorityPrivileged((eIrqNumber))
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#define Call_IntCtrl_Ip_ClearPendingPrivileged(eIrqNumber) \
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IntCtrl_Ip_ClearPendingPrivileged((eIrqNumber))
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#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)
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#define Call_IntCtrl_Ip_SetPendingPrivileged(eIrqNumber) \
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IntCtrl_Ip_SetPendingPrivileged((eIrqNumber))
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#define Call_IntCtrl_Ip_GetPendingPrivileged(eIrqNumber) \
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IntCtrl_Ip_GetPendingPrivileged((eIrqNumber))
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#define Call_IntCtrl_Ip_GetActivePrivileged(eIrqNumber) \
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IntCtrl_Ip_GetActivePrivileged((eIrqNumber))
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#endif
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#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
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#define Call_IntCtrl_Ip_SetTargetCoresPrivileged(eIrqNumber,u8TargetCores) \
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IntCtrl_Ip_SetTargetCoresPrivileged((eIrqNumber),(u8TargetCores))
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#endif
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#if (INT_CTRL_IP_MSI_AVAILABLE == STD_ON)
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#define Call_IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged(eIrqNumber,eCpuTarget) \
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IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged((eIrqNumber),(eCpuTarget))
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#define Call_IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(eIrqNumber) \
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IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(eIrqNumber)
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#define Call_IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(eIrqNumber) \
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IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(eIrqNumber)
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#endif
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#endif /*STD_ON == INTCTRL_PLATFORM_ENABLE_USER_MODE_SUPPORT*/
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#define PLATFORM_START_SEC_CODE
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#include "Platform_MemMap.h"
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static inline void IntCtrl_Ip_InstallHandlerPrivileged(IRQn_Type eIrqNumber,
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const IntCtrl_Ip_IrqHandlerType pfNewHandler,
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IntCtrl_Ip_IrqHandlerType* const pfOldHandler);
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static inline void IntCtrl_Ip_EnableIrqPrivileged(IRQn_Type eIrqNumber);
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static inline void IntCtrl_Ip_DisableIrqPrivileged(IRQn_Type eIrqNumber);
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static inline void IntCtrl_Ip_SetPriorityPrivileged(IRQn_Type eIrqNumber, uint8 u8Priority);
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static inline uint8 IntCtrl_Ip_GetPriorityPrivileged(IRQn_Type eIrqNumber);
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static inline void IntCtrl_Ip_ClearPendingPrivileged(IRQn_Type eIrqNumber);
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#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)
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static inline void IntCtrl_Ip_SetPendingPrivileged(IRQn_Type eIrqNumber);
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static inline boolean IntCtrl_Ip_GetPendingPrivileged(IRQn_Type eIrqNumber);
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static inline boolean IntCtrl_Ip_GetActivePrivileged(IRQn_Type eIrqNumber);
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#endif
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#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
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static inline void IntCtrl_Ip_SetTargetCoresPrivileged(IRQn_Type eIrqNumber, uint8 u8TargetCores);
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#endif
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#if (INT_CTRL_IP_MSI_AVAILABLE == STD_ON)
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static inline void IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber, IntCtrl_Ip_IrqTargetType eCpuTarget);
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static inline void IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber);
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static inline boolean IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber);
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#endif
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static inline void IntCtrl_Ip_InstallHandlerPrivileged(IRQn_Type eIrqNumber,
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const IntCtrl_Ip_IrqHandlerType pfNewHandler,
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IntCtrl_Ip_IrqHandlerType* const pfOldHandler)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number - dev_irqNumber is used to avoid compiler warning */
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sint32 dev_irqNumber = (sint32)eIrqNumber;
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DevAssert(INT_CTRL_IP_IRQ_MIN <= dev_irqNumber);
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DevAssert(dev_irqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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DevAssert(S32_SCB->VTOR >= (uint32)__INT_SRAM_START);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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uint32 * pVectorRam = (uint32 *)S32_SCB->VTOR;
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/* Save the former handler pointer */
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if (pfOldHandler != NULL_PTR)
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{
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*pfOldHandler = (IntCtrl_Ip_IrqHandlerType)pVectorRam[((sint32)eIrqNumber) + 16];
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}
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/* Set handler into vector table */
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pVectorRam[((sint32)eIrqNumber) + 16] = (uint32)pfNewHandler;
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/* Invalidate ICache */
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S32_SCB->ICIALLU = 0UL;
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ASM_KEYWORD("dsb");
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ASM_KEYWORD("isb");
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}
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static inline void IntCtrl_Ip_EnableIrqPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number - dev_irqNumber is used to avoid compiler warning */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert((sint32)eIrqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Enable interrupt */
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S32_NVIC->ISER[(uint32)(eIrqNumber) >> 5U] = (uint32)(1UL << ((uint32)(eIrqNumber) & (uint32)0x1FU));
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}
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static inline void IntCtrl_Ip_DisableIrqPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number - dev_irqNumber is used to avoid compiler warning */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert((sint32)eIrqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Disable interrupt */
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S32_NVIC->ICER[((uint32)(eIrqNumber) >> 5U)] = (uint32)(1UL << ((uint32)(eIrqNumber) & (uint32)0x1FU));
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}
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static inline void IntCtrl_Ip_SetPriorityPrivileged(IRQn_Type eIrqNumber, uint8 u8Priority)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number and priority - dev_irqNumber is used to avoid compiler warning */
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DevAssert(INT_CTRL_IP_IRQ_MIN <= (sint32)eIrqNumber);
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DevAssert((sint32)eIrqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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DevAssert(u8Priority < (uint8)(1U << INT_CTRL_IP_NVIC_PRIO_BITS));
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#endif /* (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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uint8 shift = (uint8) (8U - INT_CTRL_IP_NVIC_PRIO_BITS);
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/* Set Priority for device specific Interrupts */
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S32_NVIC->IP[(uint32)(eIrqNumber)] = (uint8)((((uint32)u8Priority) << shift) & 0xFFUL);
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}
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static inline uint8 IntCtrl_Ip_GetPriorityPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(INT_CTRL_IP_IRQ_MIN <= eIrqNumber);
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DevAssert((sint32)eIrqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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uint8 priority;
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uint8 shift = (uint8) (8U - INT_CTRL_IP_NVIC_PRIO_BITS);
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/* Get Priority for device specific Interrupts */
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priority = (uint8)(S32_NVIC->IP[(uint32)(eIrqNumber)] >> shift);
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return priority;
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}
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static inline void IntCtrl_Ip_ClearPendingPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert((sint32)eIrqNumber <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /* (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Clear Pending Interrupt */
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S32_NVIC->ICPR[(uint32)(eIrqNumber) >> 5U] = (uint32)(1UL << ((uint32)(eIrqNumber) & (uint32)0x1FU));
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}
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#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)
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static inline void IntCtrl_Ip_SetPendingPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number - dev_irqNumber is used to avoid compiler warning */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert(((sint32)eIrqNumber) <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Set Pending Interrupt */
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S32_NVIC->ISPR[(uint32)(eIrqNumber) >> 5U] = (uint32)(1UL << ((uint32)(eIrqNumber) & (uint32)0x1FU));
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}
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static inline boolean IntCtrl_Ip_GetPendingPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert(((sint32)eIrqNumber) <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Get Pending Interrupt */
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return ((((S32_NVIC->ISPR[(((uint32)eIrqNumber) >> 5UL)] & (1UL << (((uint32)eIrqNumber) & 0x1FUL))) != 0UL) ? TRUE : FALSE));
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}
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static inline boolean IntCtrl_Ip_GetActivePrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert(((sint32)eIrqNumber) <= (sint32)INT_CTRL_IP_IRQ_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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/* Get Active Interrupt */
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return ((((S32_NVIC->IABR[(((uint32)eIrqNumber) >> 5UL)] & (1UL << (((uint32)eIrqNumber) & 0x1FUL))) != 0UL) ? TRUE : FALSE));
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}
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#endif /*#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)*/
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#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
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/**
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* @internal
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* @brief Sets the target cores for an interrupt request.
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* @implements IntCtrl_Ip_SetTargetCores_Activity
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*/
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static inline void IntCtrl_Ip_SetTargetCoresPrivileged(IRQn_Type eIrqNumber, uint8 u8TargetCores)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(0 <= (sint32)eIrqNumber);
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DevAssert(((sint32)eIrqNumber) <= (sint32)INT_CTRL_IP_IRQ_MAX);
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/* Check interrupt routing is not locked for this IRQ */
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DevAssert((MSCM->IRSPRC[eIrqNumber] & (uint16)(MSCM_IRSPRC_LOCK_MASK)) == (uint16)MSCM_IRSPRC_LOCK(0));
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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MSCM->IRSPRC[eIrqNumber] = (uint16)u8TargetCores;
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}
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#endif
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#if (INT_CTRL_IP_MSI_AVAILABLE == STD_ON)
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static inline void IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(INTCTRL_IP_DIRECTED_CPU_INT_MIN <= eIrqNumber);
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DevAssert((sint32)eIrqNumber <= INTCTRL_IP_DIRECTED_CPU_INT_MAX);
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#endif /* (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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uint32 currentCpu;
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uint32 irqId;
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currentCpu = MSCM_CPXNUM_CPN_MASK & (MSCM->CPXNUM);
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irqId = (uint32)eIrqNumber - (uint32)INTCTRL_IP_DIRECTED_CPU_INT_MIN;
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/* Clear Directed CPU Pending Interrupt */
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MSCM_IRCPnIRx->IRCPnIRx[currentCpu][irqId].IntStatusR = 0x7FU;
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}
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static inline boolean IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(INTCTRL_IP_DIRECTED_CPU_INT_MIN <= eIrqNumber);
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DevAssert(eIrqNumber <= INTCTRL_IP_DIRECTED_CPU_INT_MAX);
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#endif /*(INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON) */
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uint32 currentCpu;
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uint32 irqId;
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currentCpu = MSCM_CPXNUM_CPN_MASK & (MSCM->CPXNUM);
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irqId = (uint32)eIrqNumber - (uint32)INTCTRL_IP_DIRECTED_CPU_INT_MIN;
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return ((MSCM_IRCPnIRx->IRCPnIRx[currentCpu][irqId].IntStatusR != 0U) ? TRUE : FALSE);
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}
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static inline void IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged(IRQn_Type eIrqNumber, IntCtrl_Ip_IrqTargetType eCpuTarget)
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{
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#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
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/* Check IRQ number */
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DevAssert(INTCTRL_IP_DIRECTED_CPU_INT_MIN <= (sint32)eIrqNumber);
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DevAssert((sint32)eIrqNumber <= INTCTRL_IP_DIRECTED_CPU_INT_MAX);
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#endif
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uint32 irqId = (uint32)eIrqNumber - (uint32)INTCTRL_IP_DIRECTED_CPU_INT_MIN;
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uint32 core;
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uint32 target;
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if (eCpuTarget == INTCTRL_IP_TARGET_OTHERS)
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{
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for (core = 0U; core < INTCTRL_IP_MSI_CORE_CNT; core++)
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{
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/* Generate a Directed CPU Interrupt to every other core */
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if (core != (MSCM_CPXNUM_CPN_MASK & (MSCM->CPXNUM)))
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{
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MSCM_IRCPnIRx->IRCPnIRx[core][irqId].IGR = 0x1U;
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}
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}
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}
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else
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{
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if (eCpuTarget == INTCTRL_IP_TARGET_SELF)
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{
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target = MSCM_CPXNUM_CPN_MASK & (MSCM->CPXNUM);
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}
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else
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{
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target = (uint32)eCpuTarget;
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}
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/* Generate Directed CPU Interrupt to target core */
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MSCM_IRCPnIRx->IRCPnIRx[target][irqId].IGR = 0x1U;
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}
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}
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#endif /* INT_CTRL_IP_MSI_AVAILABLE == STD_ON */
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/*==================================================================================================
|
|
* GLOBAL FUNCTIONS
|
|
==================================================================================================*/
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|
|
|
|
|
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/**
|
|
* @internal
|
|
* @brief Initializes the configured interrupts at interrupt controller level.
|
|
* @implements IntCtrl_Ip_Init_Activity
|
|
*/
|
|
IntCtrl_Ip_StatusType IntCtrl_Ip_Init(const IntCtrl_Ip_CtrlConfigType *pIntCtrlCtrlConfig)
|
|
{
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|
#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
|
|
DevAssert(pIntCtrlCtrlConfig != NULL_PTR);
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|
DevAssert(pIntCtrlCtrlConfig->u32ConfigIrqCount < INT_CTRL_IP_IRQ_MAX);
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|
#endif
|
|
uint32 irqIdx;
|
|
for (irqIdx = 0; irqIdx < pIntCtrlCtrlConfig->u32ConfigIrqCount; irqIdx++)
|
|
{
|
|
IntCtrl_Ip_SetPriority(pIntCtrlCtrlConfig->aIrqConfig[irqIdx].eIrqNumber,
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|
pIntCtrlCtrlConfig->aIrqConfig[irqIdx].u8IrqPriority);
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|
|
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if (pIntCtrlCtrlConfig->aIrqConfig[irqIdx].bIrqEnabled)
|
|
{
|
|
IntCtrl_Ip_EnableIrq(pIntCtrlCtrlConfig->aIrqConfig[irqIdx].eIrqNumber);
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|
}
|
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else
|
|
{
|
|
IntCtrl_Ip_DisableIrq(pIntCtrlCtrlConfig->aIrqConfig[irqIdx].eIrqNumber);
|
|
}
|
|
}
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|
|
|
return INTCTRL_IP_STATUS_SUCCESS;
|
|
}
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|
|
|
#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
|
|
/**
|
|
* @internal
|
|
* @brief Initializes the configured routing interrupts.
|
|
* @implements IntCtrl_Ip_ConfigIrqRouting_Activity
|
|
*/
|
|
IntCtrl_Ip_StatusType IntCtrl_Ip_ConfigIrqRouting(const IntCtrl_Ip_GlobalRouteConfigType *routeConfig)
|
|
{
|
|
#if (INT_CTRL_IP_DEV_ERROR_DETECT == STD_ON)
|
|
DevAssert(routeConfig != NULL_PTR);
|
|
DevAssert(routeConfig->u32ConfigIrqCount < INT_CTRL_IP_IRQ_MAX);
|
|
#endif
|
|
uint32 irqIdx;
|
|
for (irqIdx = 0; irqIdx < routeConfig->u32ConfigIrqCount; irqIdx++)
|
|
{
|
|
/* Configure routing */
|
|
IntCtrl_Ip_SetTargetCores(routeConfig->aIrqConfig[irqIdx].eIrqNumber,
|
|
routeConfig->aIrqConfig[irqIdx].u8TargetCores);
|
|
/* Install the configured handler */
|
|
IntCtrl_Ip_InstallHandler(routeConfig->aIrqConfig[irqIdx].eIrqNumber,
|
|
routeConfig->aIrqConfig[irqIdx].pfHandler,
|
|
NULL_PTR);
|
|
}
|
|
return INTCTRL_IP_STATUS_SUCCESS;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Installs a handler for an IRQ.
|
|
* @implements IntCtrl_Ip_InstallHandler_Activity
|
|
*/
|
|
void IntCtrl_Ip_InstallHandler(IRQn_Type eIrqNumber,
|
|
const IntCtrl_Ip_IrqHandlerType pfNewHandler,
|
|
IntCtrl_Ip_IrqHandlerType* const pfOldHandler)
|
|
{
|
|
Call_IntCtrl_Ip_InstallHandlerPrivileged(eIrqNumber,pfNewHandler,pfOldHandler);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Enables an interrupt request.
|
|
* @implements IntCtrl_Ip_EnableIrq_Activity
|
|
*/
|
|
void IntCtrl_Ip_EnableIrq(IRQn_Type eIrqNumber)
|
|
{
|
|
Call_IntCtrl_Ip_EnableIrqPrivileged(eIrqNumber);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Disables an interrupt request.
|
|
* @implements IntCtrl_Ip_DisableIrq_Activity
|
|
*/
|
|
void IntCtrl_Ip_DisableIrq(IRQn_Type eIrqNumber)
|
|
{
|
|
Call_IntCtrl_Ip_DisableIrqPrivileged(eIrqNumber);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Sets the priority for an interrupt request.
|
|
* @implements IntCtrl_Ip_SetPriority_Activity
|
|
*/
|
|
void IntCtrl_Ip_SetPriority(IRQn_Type eIrqNumber, uint8 u8Priority)
|
|
{
|
|
Call_IntCtrl_Ip_SetPriorityPrivileged(eIrqNumber,u8Priority);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Gets the priority for an interrupt request.
|
|
* @implements IntCtrl_Ip_GetPriority_Activity
|
|
*/
|
|
uint8 IntCtrl_Ip_GetPriority(IRQn_Type eIrqNumber)
|
|
{
|
|
return Call_IntCtrl_Ip_GetPriorityPrivileged(eIrqNumber);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Clears the pending flag for an interrupt request.
|
|
* @implements IntCtrl_Ip_ClearPending_Activity
|
|
*/
|
|
void IntCtrl_Ip_ClearPending(IRQn_Type eIrqNumber)
|
|
{
|
|
Call_IntCtrl_Ip_ClearPendingPrivileged(eIrqNumber);
|
|
}
|
|
|
|
#if (INT_CTRL_IP_STANDALONE_APIS == STD_ON)
|
|
/**
|
|
* @internal
|
|
* @brief Sets the pending flag for an interrupt request.
|
|
* @implements IntCtrl_Ip_SetPending_Activity
|
|
*/
|
|
void IntCtrl_Ip_SetPending(IRQn_Type eIrqNumber)
|
|
{
|
|
Call_IntCtrl_Ip_SetPendingPrivileged(eIrqNumber);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Gets the pending flag for an interrupt request.
|
|
* @implements IntCtrl_Ip_GetPending_Activity
|
|
*/
|
|
boolean IntCtrl_Ip_GetPending(IRQn_Type eIrqNumber)
|
|
{
|
|
return Call_IntCtrl_Ip_GetPendingPrivileged(eIrqNumber);
|
|
}
|
|
|
|
/**
|
|
* @internal
|
|
* @brief Gets the active flag for an interrupt request.
|
|
* @implements IntCtrl_Ip_GetActive_Activity
|
|
*/
|
|
boolean IntCtrl_Ip_GetActive(IRQn_Type eIrqNumber)
|
|
{
|
|
return Call_IntCtrl_Ip_GetActivePrivileged(eIrqNumber);
|
|
}
|
|
#endif /* INT_CTRL_IP_STANDALONE_APIS*/
|
|
|
|
#if (INT_CTRL_IP_MSCM_SYSTEM_INTERRUPT_ROUTER == STD_ON)
|
|
/**
|
|
* @internal
|
|
* @brief Sets the target cores for an interrupt request.
|
|
* @implements IntCtrl_Ip_SetTargetCores_Activity
|
|
*/
|
|
void IntCtrl_Ip_SetTargetCores(IRQn_Type eIrqNumber, uint8 u8TargetCores)
|
|
{
|
|
Call_IntCtrl_Ip_SetTargetCoresPrivileged(eIrqNumber,u8TargetCores);
|
|
}
|
|
#endif
|
|
|
|
#if (INT_CTRL_IP_MSI_AVAILABLE == STD_ON)
|
|
/**
|
|
* @internal
|
|
* @brief Clear directed cpu Interrupt interrupt flag.
|
|
* @implements IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged_Activity
|
|
*/
|
|
void IntCtrl_Ip_ClearDirectedCpuInterrupt(IRQn_Type eIrqNumber)
|
|
{
|
|
Call_IntCtrl_Ip_ClearDirectedCpuInterruptPrivileged(eIrqNumber);
|
|
}
|
|
/**
|
|
* @internal
|
|
* @brief Get directed cpu Interrupt interrupt flag.
|
|
* @implements IntCtrl_Ip_GetDirectedCpuInterrupt_Activity
|
|
*/
|
|
boolean IntCtrl_Ip_GetDirectedCpuInterrupt(IRQn_Type eIrqNumber)
|
|
{
|
|
return Call_IntCtrl_Ip_GetDirectedCpuInterruptPrivileged(eIrqNumber);
|
|
}
|
|
/**
|
|
* @internal
|
|
* @brief Generates an interrupt request to a CPU target.
|
|
* @implements IntCtrl_Ip_GenerateDirectedCpuInterrupt_Activity
|
|
*/
|
|
void IntCtrl_Ip_GenerateDirectedCpuInterrupt(IRQn_Type eIrqNumber, IntCtrl_Ip_IrqTargetType eCpuTarget)
|
|
{
|
|
Call_IntCtrl_Ip_GenerateDirectedCpuInterruptPrivileged(eIrqNumber,eCpuTarget);
|
|
}
|
|
#endif /* INT_CTRL_IP_MSI_AVAILABLE == STD_ON */
|
|
|
|
#define PLATFORM_STOP_SEC_CODE
|
|
#include "Platform_MemMap.h"
|
|
|
|
/** @} */
|