mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 01:43:59 +09:00
10419 lines
248 KiB
Plaintext
10419 lines
248 KiB
Plaintext
Parsed function:CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS.part.0
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Parsed function:NOT_UNDER_MCU_CONTROL_A.part.0
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Parsed function:CONFIG_ELEMENTS_MAPPINGS_01.part.0
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Parsed function:get_TRACE_CLK_Frequency
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Parsed function:get_STM1_CLK_Frequency
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Parsed function:get_STMB_CLK_Frequency
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Parsed function:get_STM0_CLK_Frequency
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Parsed function:get_STMA_CLK_Frequency
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Parsed function:get_RTC0_CLK_Frequency
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Parsed function:get_RTC_CLK_Frequency
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Parsed function:get_QSPI0_SFCK_CLK_Frequency
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Parsed function:get_QSPI_SFCK_CLK_Frequency
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Parsed function:get_FLEXCAN5_CLK_Frequency
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Parsed function:get_FLEXCAN4_CLK_Frequency
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Parsed function:get_FLEXCAN3_CLK_Frequency
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Parsed function:get_FLEXCANB_CLK_Frequency
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Parsed function:get_FLEXCAN2_CLK_Frequency
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Parsed function:get_FLEXCAN1_CLK_Frequency
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Parsed function:get_FLEXCAN0_CLK_Frequency
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Parsed function:get_FLEXCANA_CLK_Frequency
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Parsed function:get_EMAC0_TX_CLK_Frequency
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Parsed function:get_EMAC_TX_CLK_Frequency
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Parsed function:get_EMAC0_TS_CLK_Frequency
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Parsed function:get_EMAC_TS_CLK_Frequency
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Parsed function:get_EMAC0_RX_CLK_Frequency
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Parsed function:get_EMAC_RX_CLK_Frequency
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Parsed function:get_CLKOUT_STANDBY_CLK_Frequency
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Parsed function:get_SWT1_CLK_Frequency
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Parsed function:get_SWT0_CLK_Frequency
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Parsed function:get_SIUL0_CLK_Frequency
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Parsed function:get_QSPI0_TX_MEM_CLK_Frequency
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Parsed function:get_QSPI0_RAM_CLK_Frequency
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Parsed function:get_DCM0_CLK_Frequency
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Parsed function:get_SEMA42_CLK_Frequency
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Parsed function:get_MSCM_CLK_Frequency
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Parsed function:get_LPUART8_CLK_Frequency
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Parsed function:get_LPUART0_CLK_Frequency
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Parsed function:get_LPSPI0_CLK_Frequency
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Parsed function:get_INTM_CLK_Frequency
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Parsed function:get_FLEXIO0_CLK_Frequency
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Parsed function:get_CRC0_CLK_Frequency
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Parsed function:get_WKPU0_CLK_Frequency
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Parsed function:get_TSENSE0_CLK_Frequency
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Parsed function:get_TRGMUX0_CLK_Frequency
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Parsed function:get_STCU0_CLK_Frequency
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Parsed function:get_SAI1_CLK_Frequency
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Parsed function:get_SAI0_CLK_Frequency
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Parsed function:get_PIT2_CLK_Frequency
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Parsed function:get_PIT1_CLK_Frequency
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Parsed function:get_PIT0_CLK_Frequency
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Parsed function:get_MUB_CLK_Frequency
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Parsed function:get_MUA_CLK_Frequency
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Parsed function:get_LPUART9_CLK_Frequency
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Parsed function:get_LPUART7_CLK_Frequency
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Parsed function:get_LPUART6_CLK_Frequency
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Parsed function:get_LPUART5_CLK_Frequency
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Parsed function:get_LPUART4_CLK_Frequency
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Parsed function:get_LPUART3_CLK_Frequency
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Parsed function:get_LPUART2_CLK_Frequency
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Parsed function:get_LPUART1_CLK_Frequency
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Parsed function:get_LPUART15_CLK_Frequency
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Parsed function:get_LPUART14_CLK_Frequency
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Parsed function:get_LPUART13_CLK_Frequency
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Parsed function:get_LPUART12_CLK_Frequency
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Parsed function:get_LPUART11_CLK_Frequency
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Parsed function:get_LPUART10_CLK_Frequency
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Parsed function:get_LPSPI5_CLK_Frequency
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Parsed function:get_LPSPI4_CLK_Frequency
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Parsed function:get_LPSPI3_CLK_Frequency
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Parsed function:get_LPSPI2_CLK_Frequency
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Parsed function:get_LPSPI1_CLK_Frequency
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Parsed function:get_LPI2C1_CLK_Frequency
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Parsed function:get_LPI2C0_CLK_Frequency
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Parsed function:get_FLASH0_CLK_Frequency
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Parsed function:get_ERM0_CLK_Frequency
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Parsed function:get_EIM0_CLK_Frequency
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Parsed function:get_CMP2_CLK_Frequency
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Parsed function:get_CMP1_CLK_Frequency
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Parsed function:get_CMP0_CLK_Frequency
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Parsed function:get_TEMPSENSE_CLK_Frequency
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Parsed function:get_TCM_CM7_1_CLK_Frequency
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Parsed function:get_TCM_CM7_0_CLK_Frequency
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Parsed function:get_LCU1_CLK_Frequency
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Parsed function:get_LCU0_CLK_Frequency
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Parsed function:get_EMIOS2_CLK_Frequency
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Parsed function:get_EMIOS1_CLK_Frequency
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Parsed function:get_EMIOS0_CLK_Frequency
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Parsed function:get_EDMA0_TCD9_CLK_Frequency
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Parsed function:get_EDMA0_TCD8_CLK_Frequency
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Parsed function:get_EDMA0_TCD7_CLK_Frequency
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Parsed function:get_EDMA0_TCD6_CLK_Frequency
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Parsed function:get_EDMA0_TCD5_CLK_Frequency
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Parsed function:get_EDMA0_TCD4_CLK_Frequency
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Parsed function:get_EDMA0_TCD3_CLK_Frequency
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Parsed function:get_EDMA0_TCD31_CLK_Frequency
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Parsed function:get_EDMA0_TCD30_CLK_Frequency
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Parsed function:get_EDMA0_TCD2_CLK_Frequency
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Parsed function:get_EDMA0_TCD29_CLK_Frequency
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Parsed function:get_EDMA0_TCD28_CLK_Frequency
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Parsed function:get_EDMA0_TCD27_CLK_Frequency
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Parsed function:get_EDMA0_TCD26_CLK_Frequency
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Parsed function:get_EDMA0_TCD25_CLK_Frequency
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Parsed function:get_EDMA0_TCD24_CLK_Frequency
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Parsed function:get_EDMA0_TCD23_CLK_Frequency
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Parsed function:get_EDMA0_TCD22_CLK_Frequency
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Parsed function:get_EDMA0_TCD21_CLK_Frequency
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Parsed function:get_EDMA0_TCD20_CLK_Frequency
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Parsed function:get_EDMA0_TCD1_CLK_Frequency
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Parsed function:get_EDMA0_TCD19_CLK_Frequency
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Parsed function:get_EDMA0_TCD18_CLK_Frequency
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Parsed function:get_EDMA0_TCD17_CLK_Frequency
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Parsed function:get_EDMA0_TCD16_CLK_Frequency
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Parsed function:get_EDMA0_TCD15_CLK_Frequency
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Parsed function:get_EDMA0_TCD14_CLK_Frequency
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Parsed function:get_EDMA0_TCD13_CLK_Frequency
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Parsed function:get_EDMA0_TCD12_CLK_Frequency
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Parsed function:get_EDMA0_TCD11_CLK_Frequency
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Parsed function:get_EDMA0_TCD10_CLK_Frequency
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Parsed function:get_EDMA0_TCD0_CLK_Frequency
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Parsed function:get_EDMA0_CLK_Frequency
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Parsed function:get_DMAMUX1_CLK_Frequency
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Parsed function:get_DMAMUX0_CLK_Frequency
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Parsed function:get_BCTU0_CLK_Frequency
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Parsed function:get_ADC2_CLK_Frequency
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Parsed function:get_ADC1_CLK_Frequency
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Parsed function:get_ADC0_CLK_Frequency
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Parsed function:CallbackDelay
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Parsed function:CallEmptyCallbacks
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Parsed function:McMeEnterKey
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Parsed function:CMU_HSE_CLK_B
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Parsed function:CMU_HSE_CLK_A
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Parsed function:CMU_AIPS_PLAT_CLK_B
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Parsed function:CMU_AIPS_PLAT_CLK_A
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Parsed function:CMU_CORE_CLK_B
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Parsed function:CMU_CORE_CLK_A
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Parsed function:CMU_FXOSC_CLK_B
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Parsed function:CMU_FXOSC_CLK_A
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Parsed function:PCFS_PLL_PHI0_E
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Parsed function:PCFS_PLL_PHI0_D
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Parsed function:PCFS_PLL_PHI0_C
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Parsed function:PCFS_PLL_PHI0_B
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Parsed function:PCFS_PLL_PHI0_A
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Parsed function:CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS
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Parsed function:IntegerDividers_K
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Parsed function:IntegerDividers_J
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Parsed function:IntegerDividers_I
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Parsed function:IntegerDividers_H
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Parsed function:IntegerDividers_G
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Parsed function:IntegerDividers_F
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Parsed function:IntegerDividers_E
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Parsed function:IntegerDividers_D
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Parsed function:IntegerDividers_C
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Parsed function:IntegerDividers_B
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Parsed function:IntegerDividers_A
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Parsed function:PLL_C
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Parsed function:PLL_B
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Parsed function:PLL_A
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Parsed function:IRCOSCS_XOSCS_SERDES_EXTERNAL_CLOCKS
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Parsed function:NOT_UNDER_MCU_CONTROL_B
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Parsed function:NOT_UNDER_MCU_CONTROL_A
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Parsed function:CONFIG_ELEMENTS_MAPPINGS_02
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Parsed function:CONFIG_ELEMENTS_MAPPINGS_01
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Parsed function:UpdateFrequencies
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Parsed function:GetProducerClockFreq
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Parsed function:SpecificPlatformInitClock
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Parsed function:SpecificPeripheralClockInitialization
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Parsed function:GetClockState
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Parsed function:UpdateClockState
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Dump after hash based groups
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Congruence classes: 88 (unique hash values: 88), with total: 209 items
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Class size histogram [num of members]: number of classe number of classess
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[1]: 74 classes
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[2]: 8 classes
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[4]: 5 classes
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[99]: 1 classes
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Dump after WPA based types groups
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Congruence classes: 88 (unique hash values: 88), with total: 209 items
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Class size histogram [num of members]: number of classe number of classess
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[1]: 74 classes
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[2]: 8 classes
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[4]: 5 classes
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[99]: 1 classes
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Worklist has been filled with: 58
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Address reference subdivision created: 0 new classes.
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Dump after callgraph-based congruence reduction
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Congruence classes: 88 (unique hash values: 88), with total: 209 items
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Class size histogram [num of members]: number of classe number of classess
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[1]: 74 classes
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[2]: 8 classes
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[4]: 5 classes
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[99]: 1 classes
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Init called for 135 items (64.59%).
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Dump after full equality comparison of groups
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Congruence classes: 103 (unique hash values: 88), with total: 209 items
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Class size histogram [num of members]: number of classe number of classess
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[1]: 88 classes
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[2]: 10 classes
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[4]: 2 classes
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[8]: 1 classes
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[38]: 1 classes
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[47]: 1 classes
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Worklist has been filled with: 73
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Address reference subdivision created: 0 new classes.
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Congruence classes: 103 (unique hash values: 88), with total: 209 items
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Class size histogram [num of members]: number of classe number of classess
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[1]: 88 classes
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[2]: 10 classes
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[4]: 2 classes
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[8]: 1 classes
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[38]: 1 classes
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[47]: 1 classes
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Item count: 209
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Congruent classes before: 103, after: 103
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Average class size before: 2.03, after: 2.03
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Average non-singular class size: 8.07, count: 15
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Equal symbols: 106
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Fraction of visited symbols: 50.72%
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Semantic equality hit:pllCallbackIndex->gateCallbackIndex
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Assembler symbol names:pllCallbackIndex->gateCallbackIndex
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Not unifying; address of original may be compared.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_ADC1_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_ADC1_CLK_Frequency
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Symbols to be put in SSA form
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{ D.6990 D.6991 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_ADC1_CLK_Frequency/81
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_ADC1_CLK_Frequency
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IPA function summary for get_ADC1_CLK_Frequency/81 inlinable
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global time: 13.000000
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self size: 5
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global size: 0
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min size: 0
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self stack: 0
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global stack: 0
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size:0.000000, time:0.000000
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size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
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get_ADC0_CLK_Frequency/80 function not considered for inlining
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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Unified; Wrapper has been created.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_ADC2_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_ADC2_CLK_Frequency
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Symbols to be put in SSA form
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{ D.6992 D.6993 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_ADC2_CLK_Frequency/82
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_ADC2_CLK_Frequency
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IPA function summary for get_ADC2_CLK_Frequency/82 inlinable
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global time: 13.000000
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self size: 5
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global size: 0
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min size: 0
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self stack: 0
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global stack: 0
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size:0.000000, time:0.000000
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size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
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get_ADC0_CLK_Frequency/80 function not considered for inlining
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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Unified; Wrapper has been created.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_BCTU0_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_BCTU0_CLK_Frequency
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Symbols to be put in SSA form
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{ D.6994 D.6995 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_BCTU0_CLK_Frequency/83
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_BCTU0_CLK_Frequency
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IPA function summary for get_BCTU0_CLK_Frequency/83 inlinable
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global time: 13.000000
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self size: 5
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global size: 0
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min size: 0
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self stack: 0
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global stack: 0
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size:0.000000, time:0.000000
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size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
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get_ADC0_CLK_Frequency/80 function not considered for inlining
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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Unified; Wrapper has been created.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_DMAMUX0_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_DMAMUX0_CLK_Frequency
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Symbols to be put in SSA form
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{ D.6996 D.6997 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_DMAMUX0_CLK_Frequency/84
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_DMAMUX0_CLK_Frequency
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IPA function summary for get_DMAMUX0_CLK_Frequency/84 inlinable
|
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global time: 13.000000
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self size: 5
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global size: 0
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min size: 0
|
|
self stack: 0
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global stack: 0
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|
size:0.000000, time:0.000000
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size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
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get_ADC0_CLK_Frequency/80 function not considered for inlining
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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Unified; Wrapper has been created.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_DMAMUX1_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_DMAMUX1_CLK_Frequency
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Symbols to be put in SSA form
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{ D.6998 D.6999 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_DMAMUX1_CLK_Frequency/85
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_DMAMUX1_CLK_Frequency
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IPA function summary for get_DMAMUX1_CLK_Frequency/85 inlinable
|
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global time: 13.000000
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self size: 5
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global size: 0
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min size: 0
|
|
self stack: 0
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global stack: 0
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|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
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get_ADC0_CLK_Frequency/80 function not considered for inlining
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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Unified; Wrapper has been created.
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Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_CLK_Frequency
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Symbols to be put in SSA form
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{ D.7000 D.7001 }
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Incremental SSA update started at block: 0
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Number of blocks in CFG: 3
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Number of blocks to update: 2 ( 67%)
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Analyzing function: get_EDMA0_CLK_Frequency/86
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;; 1 loops found
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;;
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;; Loop 0
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;; header 0, latch 1
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;; depth 0, outer -1
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;; nodes: 0 1 2
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;; 2 succs { 1 }
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Analyzing function body size: get_EDMA0_CLK_Frequency
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IPA function summary for get_EDMA0_CLK_Frequency/86 inlinable
|
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global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
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global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
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calls:
|
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get_ADC0_CLK_Frequency/80 function not considered for inlining
|
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loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
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|
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Unified; Wrapper has been created.
|
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Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD0_CLK_Frequency
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Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD0_CLK_Frequency
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|
|
Symbols to be put in SSA form
|
|
{ D.7002 D.7003 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD0_CLK_Frequency/87
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD0_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD0_CLK_Frequency/87 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD10_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD10_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7004 D.7005 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD10_CLK_Frequency/88
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD10_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD10_CLK_Frequency/88 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD11_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD11_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7006 D.7007 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD11_CLK_Frequency/89
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD11_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD11_CLK_Frequency/89 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD12_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD12_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7008 D.7009 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD12_CLK_Frequency/90
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD12_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD12_CLK_Frequency/90 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD13_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD13_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7010 D.7011 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD13_CLK_Frequency/91
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD13_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD13_CLK_Frequency/91 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD14_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD14_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7012 D.7013 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD14_CLK_Frequency/92
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD14_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD14_CLK_Frequency/92 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD15_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD15_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7014 D.7015 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD15_CLK_Frequency/93
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD15_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD15_CLK_Frequency/93 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD16_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD16_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7016 D.7017 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD16_CLK_Frequency/94
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD16_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD16_CLK_Frequency/94 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD17_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD17_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7018 D.7019 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD17_CLK_Frequency/95
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD17_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD17_CLK_Frequency/95 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD18_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD18_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7020 D.7021 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD18_CLK_Frequency/96
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD18_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD18_CLK_Frequency/96 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD19_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD19_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7022 D.7023 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD19_CLK_Frequency/97
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD19_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD19_CLK_Frequency/97 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD1_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7024 D.7025 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD1_CLK_Frequency/98
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD1_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD1_CLK_Frequency/98 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD20_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD20_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7026 D.7027 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD20_CLK_Frequency/99
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD20_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD20_CLK_Frequency/99 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD21_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD21_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7028 D.7029 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD21_CLK_Frequency/100
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD21_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD21_CLK_Frequency/100 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD22_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD22_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7030 D.7031 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD22_CLK_Frequency/101
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD22_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD22_CLK_Frequency/101 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD23_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD23_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7032 D.7033 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD23_CLK_Frequency/102
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD23_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD23_CLK_Frequency/102 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD24_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD24_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7034 D.7035 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD24_CLK_Frequency/103
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD24_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD24_CLK_Frequency/103 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD25_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD25_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7036 D.7037 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD25_CLK_Frequency/104
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD25_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD25_CLK_Frequency/104 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD26_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD26_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7038 D.7039 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD26_CLK_Frequency/105
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD26_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD26_CLK_Frequency/105 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD27_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD27_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7040 D.7041 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD27_CLK_Frequency/106
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD27_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD27_CLK_Frequency/106 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD28_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD28_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7042 D.7043 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD28_CLK_Frequency/107
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD28_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD28_CLK_Frequency/107 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD29_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD29_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7044 D.7045 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD29_CLK_Frequency/108
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD29_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD29_CLK_Frequency/108 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD2_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7046 D.7047 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD2_CLK_Frequency/109
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD2_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD2_CLK_Frequency/109 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD30_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD30_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7048 D.7049 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD30_CLK_Frequency/110
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD30_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD30_CLK_Frequency/110 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD31_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD31_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7050 D.7051 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD31_CLK_Frequency/111
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD31_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD31_CLK_Frequency/111 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD3_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD3_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7052 D.7053 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD3_CLK_Frequency/112
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD3_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD3_CLK_Frequency/112 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD4_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD4_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7054 D.7055 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD4_CLK_Frequency/113
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD4_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD4_CLK_Frequency/113 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD5_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD5_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7056 D.7057 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD5_CLK_Frequency/114
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD5_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD5_CLK_Frequency/114 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD6_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD6_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7058 D.7059 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD6_CLK_Frequency/115
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD6_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD6_CLK_Frequency/115 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD7_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD7_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7060 D.7061 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD7_CLK_Frequency/116
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD7_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD7_CLK_Frequency/116 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD8_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD8_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7062 D.7063 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD8_CLK_Frequency/117
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD8_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD8_CLK_Frequency/117 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EDMA0_TCD9_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EDMA0_TCD9_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7064 D.7065 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EDMA0_TCD9_CLK_Frequency/118
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EDMA0_TCD9_CLK_Frequency
|
|
|
|
IPA function summary for get_EDMA0_TCD9_CLK_Frequency/118 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EMIOS0_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EMIOS0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7066 D.7067 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMIOS0_CLK_Frequency/119
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMIOS0_CLK_Frequency
|
|
|
|
IPA function summary for get_EMIOS0_CLK_Frequency/119 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EMIOS1_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EMIOS1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7068 D.7069 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMIOS1_CLK_Frequency/120
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMIOS1_CLK_Frequency
|
|
|
|
IPA function summary for get_EMIOS1_CLK_Frequency/120 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_EMIOS2_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_EMIOS2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7070 D.7071 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMIOS2_CLK_Frequency/121
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMIOS2_CLK_Frequency
|
|
|
|
IPA function summary for get_EMIOS2_CLK_Frequency/121 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_LCU0_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_LCU0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7072 D.7073 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LCU0_CLK_Frequency/122
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LCU0_CLK_Frequency
|
|
|
|
IPA function summary for get_LCU0_CLK_Frequency/122 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_LCU1_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_LCU1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7074 D.7075 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LCU1_CLK_Frequency/123
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LCU1_CLK_Frequency
|
|
|
|
IPA function summary for get_LCU1_CLK_Frequency/123 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_TCM_CM7_0_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_TCM_CM7_0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7076 D.7077 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_TCM_CM7_0_CLK_Frequency/124
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_TCM_CM7_0_CLK_Frequency
|
|
|
|
IPA function summary for get_TCM_CM7_0_CLK_Frequency/124 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_TCM_CM7_1_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_TCM_CM7_1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7078 D.7079 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_TCM_CM7_1_CLK_Frequency/125
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_TCM_CM7_1_CLK_Frequency
|
|
|
|
IPA function summary for get_TCM_CM7_1_CLK_Frequency/125 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_ADC0_CLK_Frequency->get_TEMPSENSE_CLK_Frequency
|
|
Assembler symbol names:get_ADC0_CLK_Frequency->get_TEMPSENSE_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7080 D.7081 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_TEMPSENSE_CLK_Frequency/126
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_TEMPSENSE_CLK_Frequency
|
|
|
|
IPA function summary for get_TEMPSENSE_CLK_Frequency/126 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_ADC0_CLK_Frequency/80 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_CMP1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_CMP1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7082 D.7083 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_CMP1_CLK_Frequency/128
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_CMP1_CLK_Frequency
|
|
|
|
IPA function summary for get_CMP1_CLK_Frequency/128 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_CMP2_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_CMP2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7084 D.7085 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_CMP2_CLK_Frequency/129
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_CMP2_CLK_Frequency
|
|
|
|
IPA function summary for get_CMP2_CLK_Frequency/129 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_EIM0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_EIM0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7086 D.7087 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EIM0_CLK_Frequency/130
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EIM0_CLK_Frequency
|
|
|
|
IPA function summary for get_EIM0_CLK_Frequency/130 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_ERM0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_ERM0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7088 D.7089 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_ERM0_CLK_Frequency/131
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_ERM0_CLK_Frequency
|
|
|
|
IPA function summary for get_ERM0_CLK_Frequency/131 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_FLASH0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_FLASH0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7090 D.7091 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLASH0_CLK_Frequency/132
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLASH0_CLK_Frequency
|
|
|
|
IPA function summary for get_FLASH0_CLK_Frequency/132 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPI2C0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPI2C0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7092 D.7093 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPI2C0_CLK_Frequency/133
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPI2C0_CLK_Frequency
|
|
|
|
IPA function summary for get_LPI2C0_CLK_Frequency/133 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPI2C1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPI2C1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7094 D.7095 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPI2C1_CLK_Frequency/134
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPI2C1_CLK_Frequency
|
|
|
|
IPA function summary for get_LPI2C1_CLK_Frequency/134 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPSPI1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPSPI1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7096 D.7097 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI1_CLK_Frequency/135
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI1_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI1_CLK_Frequency/135 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPSPI2_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPSPI2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7098 D.7099 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI2_CLK_Frequency/136
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI2_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI2_CLK_Frequency/136 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPSPI3_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPSPI3_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7100 D.7101 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI3_CLK_Frequency/137
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI3_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI3_CLK_Frequency/137 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPSPI4_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPSPI4_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7102 D.7103 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI4_CLK_Frequency/138
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI4_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI4_CLK_Frequency/138 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPSPI5_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPSPI5_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7104 D.7105 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI5_CLK_Frequency/139
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI5_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI5_CLK_Frequency/139 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART10_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART10_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7106 D.7107 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART10_CLK_Frequency/140
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART10_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART10_CLK_Frequency/140 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART11_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART11_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7108 D.7109 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART11_CLK_Frequency/141
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART11_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART11_CLK_Frequency/141 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART12_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART12_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7110 D.7111 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART12_CLK_Frequency/142
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART12_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART12_CLK_Frequency/142 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART13_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART13_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7112 D.7113 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART13_CLK_Frequency/143
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART13_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART13_CLK_Frequency/143 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART14_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART14_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7114 D.7115 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART14_CLK_Frequency/144
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART14_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART14_CLK_Frequency/144 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART15_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART15_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7116 D.7117 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART15_CLK_Frequency/145
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART15_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART15_CLK_Frequency/145 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7118 D.7119 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART1_CLK_Frequency/146
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART1_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART1_CLK_Frequency/146 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART2_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7120 D.7121 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART2_CLK_Frequency/147
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART2_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART2_CLK_Frequency/147 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART3_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART3_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7122 D.7123 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART3_CLK_Frequency/148
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART3_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART3_CLK_Frequency/148 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART4_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART4_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7124 D.7125 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART4_CLK_Frequency/149
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART4_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART4_CLK_Frequency/149 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART5_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART5_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7126 D.7127 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART5_CLK_Frequency/150
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART5_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART5_CLK_Frequency/150 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART6_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART6_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7128 D.7129 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART6_CLK_Frequency/151
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART6_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART6_CLK_Frequency/151 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART7_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART7_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7130 D.7131 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART7_CLK_Frequency/152
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART7_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART7_CLK_Frequency/152 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_LPUART9_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_LPUART9_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7132 D.7133 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART9_CLK_Frequency/153
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART9_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART9_CLK_Frequency/153 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_MUA_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_MUA_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7134 D.7135 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_MUA_CLK_Frequency/154
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_MUA_CLK_Frequency
|
|
|
|
IPA function summary for get_MUA_CLK_Frequency/154 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_MUB_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_MUB_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7136 D.7137 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_MUB_CLK_Frequency/155
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_MUB_CLK_Frequency
|
|
|
|
IPA function summary for get_MUB_CLK_Frequency/155 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_PIT0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_PIT0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7138 D.7139 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_PIT0_CLK_Frequency/156
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_PIT0_CLK_Frequency
|
|
|
|
IPA function summary for get_PIT0_CLK_Frequency/156 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_PIT1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_PIT1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7140 D.7141 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_PIT1_CLK_Frequency/157
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_PIT1_CLK_Frequency
|
|
|
|
IPA function summary for get_PIT1_CLK_Frequency/157 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_PIT2_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_PIT2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7142 D.7143 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_PIT2_CLK_Frequency/158
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_PIT2_CLK_Frequency
|
|
|
|
IPA function summary for get_PIT2_CLK_Frequency/158 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_SAI0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_SAI0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7144 D.7145 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_SAI0_CLK_Frequency/159
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_SAI0_CLK_Frequency
|
|
|
|
IPA function summary for get_SAI0_CLK_Frequency/159 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_SAI1_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_SAI1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7146 D.7147 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_SAI1_CLK_Frequency/160
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_SAI1_CLK_Frequency
|
|
|
|
IPA function summary for get_SAI1_CLK_Frequency/160 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_STCU0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_STCU0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7148 D.7149 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_STCU0_CLK_Frequency/161
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_STCU0_CLK_Frequency
|
|
|
|
IPA function summary for get_STCU0_CLK_Frequency/161 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_TRGMUX0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_TRGMUX0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7150 D.7151 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_TRGMUX0_CLK_Frequency/162
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_TRGMUX0_CLK_Frequency
|
|
|
|
IPA function summary for get_TRGMUX0_CLK_Frequency/162 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_TSENSE0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_TSENSE0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7152 D.7153 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_TSENSE0_CLK_Frequency/163
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_TSENSE0_CLK_Frequency
|
|
|
|
IPA function summary for get_TSENSE0_CLK_Frequency/163 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CMP0_CLK_Frequency->get_WKPU0_CLK_Frequency
|
|
Assembler symbol names:get_CMP0_CLK_Frequency->get_WKPU0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7154 D.7155 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_WKPU0_CLK_Frequency/164
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_WKPU0_CLK_Frequency
|
|
|
|
IPA function summary for get_WKPU0_CLK_Frequency/164 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CMP0_CLK_Frequency/127 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_FLEXIO0_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_FLEXIO0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7156 D.7157 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXIO0_CLK_Frequency/166
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXIO0_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXIO0_CLK_Frequency/166 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_INTM_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_INTM_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7158 D.7159 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_INTM_CLK_Frequency/167
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_INTM_CLK_Frequency
|
|
|
|
IPA function summary for get_INTM_CLK_Frequency/167 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_LPSPI0_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_LPSPI0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7160 D.7161 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPSPI0_CLK_Frequency/168
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPSPI0_CLK_Frequency
|
|
|
|
IPA function summary for get_LPSPI0_CLK_Frequency/168 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_LPUART0_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_LPUART0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7162 D.7163 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART0_CLK_Frequency/169
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART0_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART0_CLK_Frequency/169 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_LPUART8_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_LPUART8_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7164 D.7165 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_LPUART8_CLK_Frequency/170
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_LPUART8_CLK_Frequency
|
|
|
|
IPA function summary for get_LPUART8_CLK_Frequency/170 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_MSCM_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_MSCM_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7166 D.7167 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_MSCM_CLK_Frequency/171
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_MSCM_CLK_Frequency
|
|
|
|
IPA function summary for get_MSCM_CLK_Frequency/171 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_CRC0_CLK_Frequency->get_SEMA42_CLK_Frequency
|
|
Assembler symbol names:get_CRC0_CLK_Frequency->get_SEMA42_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7168 D.7169 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_SEMA42_CLK_Frequency/172
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_SEMA42_CLK_Frequency
|
|
|
|
IPA function summary for get_SEMA42_CLK_Frequency/172 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_CRC0_CLK_Frequency/165 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_QSPI0_RAM_CLK_Frequency->get_QSPI0_TX_MEM_CLK_Frequency
|
|
Assembler symbol names:get_QSPI0_RAM_CLK_Frequency->get_QSPI0_TX_MEM_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7170 D.7171 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_QSPI0_TX_MEM_CLK_Frequency/175
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_QSPI0_TX_MEM_CLK_Frequency
|
|
|
|
IPA function summary for get_QSPI0_TX_MEM_CLK_Frequency/175 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_QSPI0_RAM_CLK_Frequency/174 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_SWT0_CLK_Frequency->get_SWT1_CLK_Frequency
|
|
Assembler symbol names:get_SWT0_CLK_Frequency->get_SWT1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7172 D.7173 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_SWT1_CLK_Frequency/178
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_SWT1_CLK_Frequency
|
|
|
|
IPA function summary for get_SWT1_CLK_Frequency/178 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_SWT0_CLK_Frequency/177 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 2 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_EMAC_RX_CLK_Frequency->get_EMAC0_RX_CLK_Frequency
|
|
Assembler symbol names:get_EMAC_RX_CLK_Frequency->get_EMAC0_RX_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7174 D.7175 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMAC0_RX_CLK_Frequency/181
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMAC0_RX_CLK_Frequency
|
|
|
|
IPA function summary for get_EMAC0_RX_CLK_Frequency/181 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_EMAC_RX_CLK_Frequency/180 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_EMAC_TS_CLK_Frequency->get_EMAC0_TS_CLK_Frequency
|
|
Assembler symbol names:get_EMAC_TS_CLK_Frequency->get_EMAC0_TS_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7176 D.7177 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMAC0_TS_CLK_Frequency/183
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMAC0_TS_CLK_Frequency
|
|
|
|
IPA function summary for get_EMAC0_TS_CLK_Frequency/183 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_EMAC_TS_CLK_Frequency/182 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_EMAC_TX_CLK_Frequency->get_EMAC0_TX_CLK_Frequency
|
|
Assembler symbol names:get_EMAC_TX_CLK_Frequency->get_EMAC0_TX_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7178 D.7179 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_EMAC0_TX_CLK_Frequency/185
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_EMAC0_TX_CLK_Frequency
|
|
|
|
IPA function summary for get_EMAC0_TX_CLK_Frequency/185 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_EMAC_TX_CLK_Frequency/184 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANA_CLK_Frequency->get_FLEXCAN0_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANA_CLK_Frequency->get_FLEXCAN0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7180 D.7181 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN0_CLK_Frequency/187
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN0_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN0_CLK_Frequency/187 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANA_CLK_Frequency/186 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANA_CLK_Frequency->get_FLEXCAN1_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANA_CLK_Frequency->get_FLEXCAN1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7182 D.7183 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN1_CLK_Frequency/188
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN1_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN1_CLK_Frequency/188 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANA_CLK_Frequency/186 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANA_CLK_Frequency->get_FLEXCAN2_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANA_CLK_Frequency->get_FLEXCAN2_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7184 D.7185 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN2_CLK_Frequency/189
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN2_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN2_CLK_Frequency/189 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANA_CLK_Frequency/186 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANB_CLK_Frequency->get_FLEXCAN3_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANB_CLK_Frequency->get_FLEXCAN3_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7186 D.7187 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN3_CLK_Frequency/191
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN3_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN3_CLK_Frequency/191 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANB_CLK_Frequency/190 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANB_CLK_Frequency->get_FLEXCAN4_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANB_CLK_Frequency->get_FLEXCAN4_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7188 D.7189 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN4_CLK_Frequency/192
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN4_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN4_CLK_Frequency/192 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANB_CLK_Frequency/190 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_FLEXCANB_CLK_Frequency->get_FLEXCAN5_CLK_Frequency
|
|
Assembler symbol names:get_FLEXCANB_CLK_Frequency->get_FLEXCAN5_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7190 D.7191 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_FLEXCAN5_CLK_Frequency/193
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_FLEXCAN5_CLK_Frequency
|
|
|
|
IPA function summary for get_FLEXCAN5_CLK_Frequency/193 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_FLEXCANB_CLK_Frequency/190 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_QSPI_SFCK_CLK_Frequency->get_QSPI0_SFCK_CLK_Frequency
|
|
Assembler symbol names:get_QSPI_SFCK_CLK_Frequency->get_QSPI0_SFCK_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7192 D.7193 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_QSPI0_SFCK_CLK_Frequency/195
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_QSPI0_SFCK_CLK_Frequency
|
|
|
|
IPA function summary for get_QSPI0_SFCK_CLK_Frequency/195 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_QSPI_SFCK_CLK_Frequency/194 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_RTC_CLK_Frequency->get_RTC0_CLK_Frequency
|
|
Assembler symbol names:get_RTC_CLK_Frequency->get_RTC0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7194 D.7195 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_RTC0_CLK_Frequency/197
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_RTC0_CLK_Frequency
|
|
|
|
IPA function summary for get_RTC0_CLK_Frequency/197 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_RTC_CLK_Frequency/196 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 1 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_STMA_CLK_Frequency->get_STM0_CLK_Frequency
|
|
Assembler symbol names:get_STMA_CLK_Frequency->get_STM0_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7196 D.7197 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_STM0_CLK_Frequency/199
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_STM0_CLK_Frequency
|
|
|
|
IPA function summary for get_STM0_CLK_Frequency/199 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_STMA_CLK_Frequency/198 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
Semantic equality hit:get_STMB_CLK_Frequency->get_STM1_CLK_Frequency
|
|
Assembler symbol names:get_STMB_CLK_Frequency->get_STM1_CLK_Frequency
|
|
|
|
Symbols to be put in SSA form
|
|
{ D.7198 D.7199 }
|
|
Incremental SSA update started at block: 0
|
|
Number of blocks in CFG: 3
|
|
Number of blocks to update: 2 ( 67%)
|
|
|
|
|
|
|
|
Analyzing function: get_STM1_CLK_Frequency/201
|
|
;; 1 loops found
|
|
;;
|
|
;; Loop 0
|
|
;; header 0, latch 1
|
|
;; depth 0, outer -1
|
|
;; nodes: 0 1 2
|
|
;; 2 succs { 1 }
|
|
|
|
Analyzing function body size: get_STM1_CLK_Frequency
|
|
|
|
IPA function summary for get_STM1_CLK_Frequency/201 inlinable
|
|
global time: 13.000000
|
|
self size: 5
|
|
global size: 0
|
|
min size: 0
|
|
self stack: 0
|
|
global stack: 0
|
|
size:0.000000, time:0.000000
|
|
size:3.000000, time:2.000000, executed if:(not inlined)
|
|
calls:
|
|
get_STMB_CLK_Frequency/200 function not considered for inlining
|
|
loop depth: 0 freq:1.00 size: 2 time: 11callee size: 9 stack: 0
|
|
|
|
Unified; Wrapper has been created.
|
|
|
|
|
|
Reclaiming functions:
|
|
Reclaiming variables:
|
|
Clearing address taken flags:
|
|
CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS.part.0 ()
|
|
{
|
|
uint32 i;
|
|
const struct Clock_Ip_SelectorConfigType * selectorSCS_CLK;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = bufferFreqs[8];
|
|
configuredCoreClock = _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = bufferFreqs[9];
|
|
configuredAipsPlatClock = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = bufferFreqs[10];
|
|
configuredAipsSlowClock = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = bufferFreqs[11];
|
|
configuredHseClock = _4;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 3> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
NOT_UNDER_MCU_CONTROL_A.part.0 ()
|
|
{
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
<unnamed type> iftmp.61_5;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(struct MC_ME_Type *)1076740096B].PRTN1_COFB1_STAT;
|
|
_2 = _1 & 16777216;
|
|
if (_2 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLSR;
|
|
_4 = _3 & 4;
|
|
if (_4 == 0)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# iftmp.61_5 = PHI <0(3), 255(4)>
|
|
clkState[6] = iftmp.61_5;
|
|
goto <bb 7>; [100.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[6] = 0;
|
|
|
|
<bb 7> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CONFIG_ELEMENTS_MAPPINGS_01.part.0 ()
|
|
{
|
|
uint8 i;
|
|
int _2;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.85_3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
unsigned char _7;
|
|
int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.85_10;
|
|
<unnamed type> _11;
|
|
int _12;
|
|
unsigned char _13;
|
|
unsigned char _14;
|
|
int _16;
|
|
<unnamed type> _17;
|
|
int _18;
|
|
unsigned char _19;
|
|
unsigned char _20;
|
|
int _22;
|
|
<unnamed type> _23;
|
|
int _24;
|
|
unsigned char _25;
|
|
unsigned char _26;
|
|
|
|
<bb 14> [local count: 118111598]:
|
|
goto <bb 3>; [100.00%]
|
|
|
|
<bb 2> [local count: 955630209]:
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) i_1;
|
|
_4 = config_clock.85_3->ircoscs[_2].name;
|
|
_5 = (int) _4;
|
|
_6 = i_1 + 1;
|
|
freqPointers[_5] = _6;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => _6
|
|
|
|
<bb 3> [local count: 1073741809]:
|
|
# i_1 = PHI <_6(2), 0(14)>
|
|
# DEBUG i => i_1
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.85_3 = config_clock;
|
|
_7 = config_clock.85_3->ircoscsCount;
|
|
if (i_1 < _7)
|
|
goto <bb 2>; [89.00%]
|
|
else
|
|
goto <bb 4>; [11.00%]
|
|
|
|
<bb 4> [local count: 118111599]:
|
|
# config_clock.85_10 = PHI <config_clock.85_3(3)>
|
|
goto <bb 6>; [100.00%]
|
|
|
|
<bb 5> [local count: 955630212]:
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) i_8;
|
|
_11 = config_clock.85_10->xoscs[_9].name;
|
|
_12 = (int) _11;
|
|
_13 = i_8 + 1;
|
|
freqPointers[_12] = _13;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => _13
|
|
|
|
<bb 6> [local count: 1073741812]:
|
|
# i_8 = PHI <0(4), _13(5)>
|
|
# DEBUG i => i_8
|
|
# DEBUG BEGIN_STMT
|
|
_14 = config_clock.85_10->xoscsCount;
|
|
if (i_8 < _14)
|
|
goto <bb 5>; [89.00%]
|
|
else
|
|
goto <bb 7>; [11.00%]
|
|
|
|
<bb 7> [local count: 118111599]:
|
|
goto <bb 9>; [100.00%]
|
|
|
|
<bb 8> [local count: 955630219]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = (int) i_15;
|
|
_17 = config_clock.85_10->plls[_16].name;
|
|
_18 = (int) _17;
|
|
_19 = i_15 + 1;
|
|
freqPointers[_18] = _19;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => _19
|
|
|
|
<bb 9> [local count: 1073741819]:
|
|
# i_15 = PHI <0(7), _19(8)>
|
|
# DEBUG i => i_15
|
|
# DEBUG BEGIN_STMT
|
|
_20 = config_clock.85_10->pllsCount;
|
|
if (i_15 < _20)
|
|
goto <bb 8>; [89.00%]
|
|
else
|
|
goto <bb 10>; [11.00%]
|
|
|
|
<bb 10> [local count: 118111600]:
|
|
goto <bb 12>; [100.00%]
|
|
|
|
<bb 11> [local count: 955630225]:
|
|
# DEBUG BEGIN_STMT
|
|
_22 = (int) i_21;
|
|
_23 = config_clock.85_10->extClks[_22].name;
|
|
_24 = (int) _23;
|
|
_25 = i_21 + 1;
|
|
freqPointers[_24] = _25;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => _25
|
|
|
|
<bb 12> [local count: 1073741824]:
|
|
# i_21 = PHI <0(10), _25(11)>
|
|
# DEBUG i => i_21
|
|
# DEBUG BEGIN_STMT
|
|
_26 = config_clock.85_10->extClksCount;
|
|
if (i_21 < _26)
|
|
goto <bb 11>; [89.00%]
|
|
else
|
|
goto <bb 13>; [11.00%]
|
|
|
|
<bb 13> [local count: 118111601]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
get_TRACE_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076725184B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076725184B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076725184B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_STM1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.364;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.364_3 = get_STMB_CLK_Frequency (); [tail call]
|
|
return retval.364_3;
|
|
|
|
}
|
|
|
|
|
|
get_STMB_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724608B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724608B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724608B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_STM0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.363;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.363_3 = get_STMA_CLK_Frequency (); [tail call]
|
|
return retval.363_3;
|
|
|
|
}
|
|
|
|
|
|
get_STMA_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724544B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724544B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724544B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_RTC0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.362;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.362_1 = get_RTC_CLK_Frequency (); [tail call]
|
|
return retval.362_1;
|
|
|
|
}
|
|
|
|
|
|
get_RTC_CLK_Frequency ()
|
|
{
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
get_QSPI0_SFCK_CLK_Frequency ()
|
|
{
|
|
uint32 retval.361;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.361_3 = get_QSPI_SFCK_CLK_Frequency (); [tail call]
|
|
return retval.361_3;
|
|
|
|
}
|
|
|
|
|
|
get_QSPI_SFCK_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076725120B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076725120B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076725120B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN5_CLK_Frequency ()
|
|
{
|
|
uint32 retval.360;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.360_3 = get_FLEXCANB_CLK_Frequency (); [tail call]
|
|
return retval.360_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN4_CLK_Frequency ()
|
|
{
|
|
uint32 retval.359;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.359_3 = get_FLEXCANB_CLK_Frequency (); [tail call]
|
|
return retval.359_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN3_CLK_Frequency ()
|
|
{
|
|
uint32 retval.358;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.358_3 = get_FLEXCANB_CLK_Frequency (); [tail call]
|
|
return retval.358_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCANB_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724736B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724736B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724736B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.357;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.357_3 = get_FLEXCANA_CLK_Frequency (); [tail call]
|
|
return retval.357_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.356;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.356_3 = get_FLEXCANA_CLK_Frequency (); [tail call]
|
|
return retval.356_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCAN0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.355;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.355_3 = get_FLEXCANA_CLK_Frequency (); [tail call]
|
|
return retval.355_3;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXCANA_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724672B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724672B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724672B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC0_TX_CLK_Frequency ()
|
|
{
|
|
uint32 retval.354;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.354_3 = get_EMAC_TX_CLK_Frequency (); [tail call]
|
|
return retval.354_3;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC_TX_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724992B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724992B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724992B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC0_TS_CLK_Frequency ()
|
|
{
|
|
uint32 retval.353;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.353_3 = get_EMAC_TS_CLK_Frequency (); [tail call]
|
|
return retval.353_3;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC_TS_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076725056B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076725056B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076725056B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC0_RX_CLK_Frequency ()
|
|
{
|
|
uint32 retval.352;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.352_3 = get_EMAC_RX_CLK_Frequency (); [tail call]
|
|
return retval.352_3;
|
|
|
|
}
|
|
|
|
|
|
get_EMAC_RX_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724928B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724928B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724928B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_CLKOUT_STANDBY_CLK_Frequency ()
|
|
{
|
|
uint32 frequency;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
<unnamed type> _4;
|
|
int _5;
|
|
unsigned char _6;
|
|
int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _15;
|
|
long unsigned int _17;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 ={v} MEM[(volatile struct cgmMux_Type *)1076724800B].CSS;
|
|
_2 = _1 >> 24;
|
|
_3 = _2 & 63;
|
|
_4 = hardwareValue_selectorEntry[_3];
|
|
_5 = (int) _4;
|
|
_6 = freqPointers[_5];
|
|
_7 = (int) _6;
|
|
frequency_14 = bufferFreqs[_7];
|
|
# DEBUG frequency => frequency_14
|
|
# DEBUG BEGIN_STMT
|
|
_8 ={v} MEM[(volatile struct cgmMux_Type *)1076724800B].divider[0];
|
|
_9 = _8 >> 31;
|
|
_15 = enableDisableMask[_9];
|
|
frequency_16 = frequency_14 & _15;
|
|
# DEBUG frequency => frequency_16
|
|
# DEBUG BEGIN_STMT
|
|
_10 ={v} MEM[(volatile struct cgmMux_Type *)1076724800B].divider[0];
|
|
_11 = _10 >> 16;
|
|
_12 = _11 & 63;
|
|
_17 = _12 + 1;
|
|
frequency_18 = frequency_16 / _17;
|
|
# DEBUG frequency => frequency_18
|
|
# DEBUG BEGIN_STMT
|
|
return frequency_18;
|
|
|
|
}
|
|
|
|
|
|
get_SWT1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.351;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.351_2 = get_SWT0_CLK_Frequency (); [tail call]
|
|
return retval.351_2;
|
|
|
|
}
|
|
|
|
|
|
get_SWT0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[2];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_SIUL0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[0];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_QSPI0_TX_MEM_CLK_Frequency ()
|
|
{
|
|
uint32 retval.350;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.350_2 = get_QSPI0_RAM_CLK_Frequency (); [tail call]
|
|
return retval.350_2;
|
|
|
|
}
|
|
|
|
|
|
get_QSPI0_RAM_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[19];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_DCM0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[17];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_SEMA42_CLK_Frequency ()
|
|
{
|
|
uint32 retval.349;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.349_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.349_2;
|
|
|
|
}
|
|
|
|
|
|
get_MSCM_CLK_Frequency ()
|
|
{
|
|
uint32 retval.348;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.348_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.348_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART8_CLK_Frequency ()
|
|
{
|
|
uint32 retval.347;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.347_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.347_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.346;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.346_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.346_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.345;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.345_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.345_2;
|
|
|
|
}
|
|
|
|
|
|
get_INTM_CLK_Frequency ()
|
|
{
|
|
uint32 retval.344;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.344_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.344_2;
|
|
|
|
}
|
|
|
|
|
|
get_FLEXIO0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.343;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.343_2 = get_CRC0_CLK_Frequency (); [tail call]
|
|
return retval.343_2;
|
|
|
|
}
|
|
|
|
|
|
get_CRC0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[14];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_WKPU0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.342;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.342_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.342_2;
|
|
|
|
}
|
|
|
|
|
|
get_TSENSE0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.341;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.341_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.341_2;
|
|
|
|
}
|
|
|
|
|
|
get_TRGMUX0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.340;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.340_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.340_2;
|
|
|
|
}
|
|
|
|
|
|
get_STCU0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.339;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.339_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.339_2;
|
|
|
|
}
|
|
|
|
|
|
get_SAI1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.338;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.338_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.338_2;
|
|
|
|
}
|
|
|
|
|
|
get_SAI0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.337;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.337_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.337_2;
|
|
|
|
}
|
|
|
|
|
|
get_PIT2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.336;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.336_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.336_2;
|
|
|
|
}
|
|
|
|
|
|
get_PIT1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.335;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.335_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.335_2;
|
|
|
|
}
|
|
|
|
|
|
get_PIT0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.334;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.334_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.334_2;
|
|
|
|
}
|
|
|
|
|
|
get_MUB_CLK_Frequency ()
|
|
{
|
|
uint32 retval.333;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.333_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.333_2;
|
|
|
|
}
|
|
|
|
|
|
get_MUA_CLK_Frequency ()
|
|
{
|
|
uint32 retval.332;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.332_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.332_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART9_CLK_Frequency ()
|
|
{
|
|
uint32 retval.331;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.331_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.331_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART7_CLK_Frequency ()
|
|
{
|
|
uint32 retval.330;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.330_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.330_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART6_CLK_Frequency ()
|
|
{
|
|
uint32 retval.329;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.329_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.329_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART5_CLK_Frequency ()
|
|
{
|
|
uint32 retval.328;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.328_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.328_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART4_CLK_Frequency ()
|
|
{
|
|
uint32 retval.327;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.327_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.327_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART3_CLK_Frequency ()
|
|
{
|
|
uint32 retval.326;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.326_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.326_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.325;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.325_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.325_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.324;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.324_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.324_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART15_CLK_Frequency ()
|
|
{
|
|
uint32 retval.323;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.323_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.323_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART14_CLK_Frequency ()
|
|
{
|
|
uint32 retval.322;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.322_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.322_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART13_CLK_Frequency ()
|
|
{
|
|
uint32 retval.321;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.321_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.321_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART12_CLK_Frequency ()
|
|
{
|
|
uint32 retval.320;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.320_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.320_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART11_CLK_Frequency ()
|
|
{
|
|
uint32 retval.319;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.319_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.319_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPUART10_CLK_Frequency ()
|
|
{
|
|
uint32 retval.318;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.318_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.318_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI5_CLK_Frequency ()
|
|
{
|
|
uint32 retval.317;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.317_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.317_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI4_CLK_Frequency ()
|
|
{
|
|
uint32 retval.316;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.316_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.316_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI3_CLK_Frequency ()
|
|
{
|
|
uint32 retval.315;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.315_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.315_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.314;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.314_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.314_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPSPI1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.313;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.313_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.313_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPI2C1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.312;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.312_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.312_2;
|
|
|
|
}
|
|
|
|
|
|
get_LPI2C0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.311;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.311_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.311_2;
|
|
|
|
}
|
|
|
|
|
|
get_FLASH0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.310;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.310_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.310_2;
|
|
|
|
}
|
|
|
|
|
|
get_ERM0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.309;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.309_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.309_2;
|
|
|
|
}
|
|
|
|
|
|
get_EIM0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.308;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.308_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.308_2;
|
|
|
|
}
|
|
|
|
|
|
get_CMP2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.307;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.307_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.307_2;
|
|
|
|
}
|
|
|
|
|
|
get_CMP1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.306;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.306_2 = get_CMP0_CLK_Frequency (); [tail call]
|
|
return retval.306_2;
|
|
|
|
}
|
|
|
|
|
|
get_CMP0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[15];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
get_TEMPSENSE_CLK_Frequency ()
|
|
{
|
|
uint32 retval.305;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.305_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.305_2;
|
|
|
|
}
|
|
|
|
|
|
get_TCM_CM7_1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.304;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.304_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.304_2;
|
|
|
|
}
|
|
|
|
|
|
get_TCM_CM7_0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.303;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.303_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.303_2;
|
|
|
|
}
|
|
|
|
|
|
get_LCU1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.302;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.302_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.302_2;
|
|
|
|
}
|
|
|
|
|
|
get_LCU0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.301;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.301_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.301_2;
|
|
|
|
}
|
|
|
|
|
|
get_EMIOS2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.300;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.300_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.300_2;
|
|
|
|
}
|
|
|
|
|
|
get_EMIOS1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.299;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.299_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.299_2;
|
|
|
|
}
|
|
|
|
|
|
get_EMIOS0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.298;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.298_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.298_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD9_CLK_Frequency ()
|
|
{
|
|
uint32 retval.297;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.297_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.297_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD8_CLK_Frequency ()
|
|
{
|
|
uint32 retval.296;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.296_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.296_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD7_CLK_Frequency ()
|
|
{
|
|
uint32 retval.295;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.295_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.295_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD6_CLK_Frequency ()
|
|
{
|
|
uint32 retval.294;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.294_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.294_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD5_CLK_Frequency ()
|
|
{
|
|
uint32 retval.293;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.293_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.293_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD4_CLK_Frequency ()
|
|
{
|
|
uint32 retval.292;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.292_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.292_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD3_CLK_Frequency ()
|
|
{
|
|
uint32 retval.291;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.291_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.291_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD31_CLK_Frequency ()
|
|
{
|
|
uint32 retval.290;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.290_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.290_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD30_CLK_Frequency ()
|
|
{
|
|
uint32 retval.289;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.289_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.289_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.288;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.288_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.288_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD29_CLK_Frequency ()
|
|
{
|
|
uint32 retval.287;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.287_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.287_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD28_CLK_Frequency ()
|
|
{
|
|
uint32 retval.286;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.286_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.286_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD27_CLK_Frequency ()
|
|
{
|
|
uint32 retval.285;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.285_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.285_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD26_CLK_Frequency ()
|
|
{
|
|
uint32 retval.284;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.284_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.284_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD25_CLK_Frequency ()
|
|
{
|
|
uint32 retval.283;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.283_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.283_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD24_CLK_Frequency ()
|
|
{
|
|
uint32 retval.282;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.282_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.282_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD23_CLK_Frequency ()
|
|
{
|
|
uint32 retval.281;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.281_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.281_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD22_CLK_Frequency ()
|
|
{
|
|
uint32 retval.280;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.280_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.280_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD21_CLK_Frequency ()
|
|
{
|
|
uint32 retval.279;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.279_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.279_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD20_CLK_Frequency ()
|
|
{
|
|
uint32 retval.278;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.278_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.278_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.277;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.277_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.277_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD19_CLK_Frequency ()
|
|
{
|
|
uint32 retval.276;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.276_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.276_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD18_CLK_Frequency ()
|
|
{
|
|
uint32 retval.275;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.275_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.275_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD17_CLK_Frequency ()
|
|
{
|
|
uint32 retval.274;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.274_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.274_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD16_CLK_Frequency ()
|
|
{
|
|
uint32 retval.273;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.273_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.273_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD15_CLK_Frequency ()
|
|
{
|
|
uint32 retval.272;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.272_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.272_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD14_CLK_Frequency ()
|
|
{
|
|
uint32 retval.271;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.271_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.271_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD13_CLK_Frequency ()
|
|
{
|
|
uint32 retval.270;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.270_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.270_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD12_CLK_Frequency ()
|
|
{
|
|
uint32 retval.269;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.269_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.269_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD11_CLK_Frequency ()
|
|
{
|
|
uint32 retval.268;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.268_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.268_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD10_CLK_Frequency ()
|
|
{
|
|
uint32 retval.267;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.267_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.267_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_TCD0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.266;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.266_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.266_2;
|
|
|
|
}
|
|
|
|
|
|
get_EDMA0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.265;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.265_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.265_2;
|
|
|
|
}
|
|
|
|
|
|
get_DMAMUX1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.264;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.264_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.264_2;
|
|
|
|
}
|
|
|
|
|
|
get_DMAMUX0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.263;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.263_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.263_2;
|
|
|
|
}
|
|
|
|
|
|
get_BCTU0_CLK_Frequency ()
|
|
{
|
|
uint32 retval.262;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.262_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.262_2;
|
|
|
|
}
|
|
|
|
|
|
get_ADC2_CLK_Frequency ()
|
|
{
|
|
uint32 retval.261;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.261_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.261_2;
|
|
|
|
}
|
|
|
|
|
|
get_ADC1_CLK_Frequency ()
|
|
{
|
|
uint32 retval.260;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
retval.260_2 = get_ADC0_CLK_Frequency (); [tail call]
|
|
return retval.260_2;
|
|
|
|
}
|
|
|
|
|
|
get_ADC0_CLK_Frequency ()
|
|
{
|
|
unsigned char _1;
|
|
int _2;
|
|
uint32 _4;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[13];
|
|
_2 = (int) _1;
|
|
_4 = bufferFreqs[_2];
|
|
return _4;
|
|
|
|
}
|
|
|
|
|
|
CallbackDelay ()
|
|
{
|
|
uint32 TimeoutTicks;
|
|
uint32 ElapsedTime;
|
|
uint32 StartTime;
|
|
boolean TimeoutOccurred;
|
|
long unsigned int TimeoutTicks.0_1;
|
|
|
|
<bb 2> [local count: 118111600]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG TimeoutOccurred => 0
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
ClockStartTimeout (&StartTime, &ElapsedTime, &TimeoutTicks, 10);
|
|
|
|
<bb 3> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
TimeoutTicks.0_1 = TimeoutTicks;
|
|
TimeoutOccurred_6 = ClockTimeoutExpired (&StartTime, &ElapsedTime, TimeoutTicks.0_1);
|
|
# DEBUG TimeoutOccurred => TimeoutOccurred_6
|
|
# DEBUG BEGIN_STMT
|
|
if (TimeoutOccurred_6 != 0)
|
|
goto <bb 4>; [11.00%]
|
|
else
|
|
goto <bb 5>; [89.00%]
|
|
|
|
<bb 5> [local count: 955630223]:
|
|
goto <bb 3>; [100.00%]
|
|
|
|
<bb 4> [local count: 118111601]:
|
|
StartTime ={v} {CLOBBER};
|
|
ElapsedTime ={v} {CLOBBER};
|
|
TimeoutTicks ={v} {CLOBBER};
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CallEmptyCallbacks ()
|
|
{
|
|
void (*<T494>) (const struct Clock_Ip_CmuConfigType *) _1;
|
|
void (*<T498>) (Clock_Ip_NameType) _2;
|
|
void (*<T498>) (Clock_Ip_NameType) _3;
|
|
Clock_Ip_CmuStatusType (*<T49c>) (Clock_Ip_NameType) _4;
|
|
void (*<T43f>) (const struct Clock_Ip_DividerConfigType *) _5;
|
|
void (*<T44a>) (const struct Clock_Ip_DividerTriggerConfigType *) _6;
|
|
void (*<T433>) (const struct Clock_Ip_XoscConfigType *) _7;
|
|
void (*<T456>) (const struct Clock_Ip_FracDivConfigType *) _8;
|
|
clock_dfs_status_t (*<T45c>) (Clock_Ip_NameType) _9;
|
|
void (*<T484>) (const struct Clock_Ip_GateConfigType *) _10;
|
|
void (*<T489>) (Clock_Ip_NameType, boolean) _11;
|
|
void (*<T428>) (const struct Clock_Ip_IrcoscConfigType *) _12;
|
|
void (*<T467>) (const struct Clock_Ip_PllConfigType *) _13;
|
|
clock_pll_status_t (*<T46d>) (Clock_Ip_NameType) _14;
|
|
void (*<T478>) (const struct Clock_Ip_SelectorConfigType *) _15;
|
|
void (*<T4a7>) (const struct Clock_Ip_PcfsConfigType *) _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = cmuCallbacks[0].Set;
|
|
_1 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = cmuCallbacks[0].Disable;
|
|
_2 (145);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = cmuCallbacks[0].Clear;
|
|
_3 (145);
|
|
# DEBUG BEGIN_STMT
|
|
_4 = cmuCallbacks[0].GetStatus;
|
|
_4 (145);
|
|
# DEBUG BEGIN_STMT
|
|
_5 = dividerCallbacks[0].Set;
|
|
_5 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_6 = dividerTriggerCallbacks[0].Configure;
|
|
_6 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_7 = extOscCallbacks[0].Reset;
|
|
_7 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_8 = fracDivCallbacks[0].Set;
|
|
_8 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_9 = fracDivCallbacks[0].Complete;
|
|
_9 (145);
|
|
# DEBUG BEGIN_STMT
|
|
_10 = gateCallbacks[0].Set;
|
|
_10 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_11 = gateCallbacks[0].Update;
|
|
_11 (145, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_12 = intOscCallbacks[0].Set;
|
|
_12 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_13 = pllCallbacks[0].Set;
|
|
_13 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_14 = pllCallbacks[0].Complete;
|
|
_14 (145);
|
|
# DEBUG BEGIN_STMT
|
|
_15 = selectorCallbacks[0].Set;
|
|
_15 (0B);
|
|
# DEBUG BEGIN_STMT
|
|
_16 = pcfsCallbacks[0].Set;
|
|
_16 (0B);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
McMeEnterKey ()
|
|
{
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
MEM[(struct MC_ME_Type *)1076740096B].CTL_KEY ={v} 23280;
|
|
# DEBUG BEGIN_STMT
|
|
MEM[(struct MC_ME_Type *)1076740096B].CTL_KEY ={v} 42255;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_HSE_CLK_B ()
|
|
{
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
float _1;
|
|
float _2;
|
|
float _3;
|
|
float _4;
|
|
float _5;
|
|
long unsigned int _6;
|
|
float _7;
|
|
float _8;
|
|
float _9;
|
|
long unsigned int _10;
|
|
float _11;
|
|
float _12;
|
|
float _13;
|
|
float _14;
|
|
float _15;
|
|
long unsigned int _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
fReferenceClk_19 = tmpData.input2;
|
|
# DEBUG fReferenceClk => fReferenceClk_19
|
|
# DEBUG BEGIN_STMT
|
|
fMonitoredClk_20 = tmpData.input3;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_20
|
|
# DEBUG BEGIN_STMT
|
|
if (fReferenceClk_19 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (float) fMonitoredClk_20;
|
|
_2 = _1 * 1.011e+3;
|
|
_3 = (float) fReferenceClk_19;
|
|
_4 = _3 * 9.67e+2;
|
|
_5 = _2 / _4;
|
|
_6 = cmuEntries[3].refCount;
|
|
_7 = (float) _6;
|
|
_8 = _5 * _7;
|
|
_9 = _8 + 3.0e+0;
|
|
_10 = (long unsigned int) _9;
|
|
cmuEntries[3].hfRef = _10;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = _1 * 9.89e+2;
|
|
_12 = _3 * 1.033e+3;
|
|
_13 = _11 / _12;
|
|
_14 = _7 * _13;
|
|
_15 = _14 - 3.0e+0;
|
|
_16 = (long unsigned int) _15;
|
|
cmuEntries[3].lfRef = _16;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_HSE_CLK_A ()
|
|
{
|
|
uint8 enable;
|
|
uint32 cmp2;
|
|
uint32 cmp1;
|
|
uint32 fBusClk;
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.1_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int configuredHseClock.2_6;
|
|
long unsigned int configuredAipsSlowClock.3_7;
|
|
long unsigned int _8;
|
|
float _9;
|
|
float _10;
|
|
float _11;
|
|
float _12;
|
|
long unsigned int _13;
|
|
float _14;
|
|
float _15;
|
|
float _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = cmuEntries[3].configIndex;
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.1_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#10 => &config_clock.1_2->cmus[_4]
|
|
# DEBUG cmuConfig => D#10
|
|
# DEBUG BEGIN_STMT
|
|
enable_23 = MEM[(const struct Clock_Ip_CmuConfigType *)config_clock.1_2].cmus[_4].enable;
|
|
# DEBUG enable => enable_23
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# enable_21 = PHI <enable_23(3), 0(2)>
|
|
# DEBUG enable => enable_21
|
|
# DEBUG BEGIN_STMT
|
|
_5 = bufferFreqs[1];
|
|
fReferenceClk_24 = _5 / 1000;
|
|
# DEBUG fReferenceClk => fReferenceClk_24
|
|
# DEBUG BEGIN_STMT
|
|
configuredHseClock.2_6 = configuredHseClock;
|
|
fMonitoredClk_25 = configuredHseClock.2_6 / 1000;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_25
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock.3_7 = configuredAipsSlowClock;
|
|
fBusClk_26 = configuredAipsSlowClock.3_7 / 1000;
|
|
# DEBUG fBusClk => fBusClk_26
|
|
# DEBUG BEGIN_STMT
|
|
_8 = (long unsigned int) enable_21;
|
|
tmpData.input1 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input2 = fReferenceClk_24;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input3 = fMonitoredClk_25;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input4 = fBusClk_26;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (float) fReferenceClk_24;
|
|
_10 = _9 * 3.0e+0;
|
|
_11 = (float) fBusClk_26;
|
|
_12 = _10 / _11;
|
|
_13 = (long unsigned int) _12;
|
|
cmp1_31 = _13 + 1;
|
|
# DEBUG cmp1 => cmp1_31
|
|
# DEBUG BEGIN_STMT
|
|
if (configuredHseClock.2_6 > 999)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 = _9 * 5.0e+0;
|
|
_15 = (float) fMonitoredClk_25;
|
|
_16 = _14 / _15;
|
|
_17 = (long unsigned int) _16;
|
|
cmp2_32 = _17 + 9;
|
|
# DEBUG cmp2 => cmp2_32
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# cmp2_20 = PHI <cmp2_32(5), 0(4)>
|
|
# DEBUG cmp2 => cmp2_20
|
|
# DEBUG BEGIN_STMT
|
|
cmuEntries[3].enable = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = MAX_EXPR <cmp2_20, cmp1_31>;
|
|
_19 = _18 * 10;
|
|
cmuEntries[3].refCount = _19;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_AIPS_PLAT_CLK_B ()
|
|
{
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
float _1;
|
|
float _2;
|
|
float _3;
|
|
float _4;
|
|
float _5;
|
|
long unsigned int _6;
|
|
float _7;
|
|
float _8;
|
|
float _9;
|
|
long unsigned int _10;
|
|
float _11;
|
|
float _12;
|
|
float _13;
|
|
float _14;
|
|
float _15;
|
|
long unsigned int _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
fReferenceClk_19 = tmpData.input2;
|
|
# DEBUG fReferenceClk => fReferenceClk_19
|
|
# DEBUG BEGIN_STMT
|
|
fMonitoredClk_20 = tmpData.input3;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_20
|
|
# DEBUG BEGIN_STMT
|
|
if (fReferenceClk_19 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (float) fMonitoredClk_20;
|
|
_2 = _1 * 1.011e+3;
|
|
_3 = (float) fReferenceClk_19;
|
|
_4 = _3 * 9.67e+2;
|
|
_5 = _2 / _4;
|
|
_6 = cmuEntries[2].refCount;
|
|
_7 = (float) _6;
|
|
_8 = _5 * _7;
|
|
_9 = _8 + 3.0e+0;
|
|
_10 = (long unsigned int) _9;
|
|
cmuEntries[2].hfRef = _10;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = _1 * 9.89e+2;
|
|
_12 = _3 * 1.033e+3;
|
|
_13 = _11 / _12;
|
|
_14 = _7 * _13;
|
|
_15 = _14 - 3.0e+0;
|
|
_16 = (long unsigned int) _15;
|
|
cmuEntries[2].lfRef = _16;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_AIPS_PLAT_CLK_A ()
|
|
{
|
|
uint8 enable;
|
|
uint32 cmp2;
|
|
uint32 cmp1;
|
|
uint32 fBusClk;
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.4_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int configuredAipsPlatClock.5_6;
|
|
long unsigned int configuredAipsSlowClock.6_7;
|
|
long unsigned int _8;
|
|
float _9;
|
|
float _10;
|
|
float _11;
|
|
float _12;
|
|
long unsigned int _13;
|
|
float _14;
|
|
float _15;
|
|
float _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = cmuEntries[2].configIndex;
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.4_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#9 => &config_clock.4_2->cmus[_4]
|
|
# DEBUG cmuConfig => D#9
|
|
# DEBUG BEGIN_STMT
|
|
enable_23 = MEM[(const struct Clock_Ip_CmuConfigType *)config_clock.4_2].cmus[_4].enable;
|
|
# DEBUG enable => enable_23
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# enable_21 = PHI <enable_23(3), 0(2)>
|
|
# DEBUG enable => enable_21
|
|
# DEBUG BEGIN_STMT
|
|
_5 = bufferFreqs[1];
|
|
fReferenceClk_24 = _5 / 1000;
|
|
# DEBUG fReferenceClk => fReferenceClk_24
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsPlatClock.5_6 = configuredAipsPlatClock;
|
|
fMonitoredClk_25 = configuredAipsPlatClock.5_6 / 1000;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_25
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock.6_7 = configuredAipsSlowClock;
|
|
fBusClk_26 = configuredAipsSlowClock.6_7 / 1000;
|
|
# DEBUG fBusClk => fBusClk_26
|
|
# DEBUG BEGIN_STMT
|
|
_8 = (long unsigned int) enable_21;
|
|
tmpData.input1 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input2 = fReferenceClk_24;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input3 = fMonitoredClk_25;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input4 = fBusClk_26;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (float) fReferenceClk_24;
|
|
_10 = _9 * 3.0e+0;
|
|
_11 = (float) fBusClk_26;
|
|
_12 = _10 / _11;
|
|
_13 = (long unsigned int) _12;
|
|
cmp1_31 = _13 + 1;
|
|
# DEBUG cmp1 => cmp1_31
|
|
# DEBUG BEGIN_STMT
|
|
if (configuredAipsPlatClock.5_6 > 999)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 = _9 * 5.0e+0;
|
|
_15 = (float) fMonitoredClk_25;
|
|
_16 = _14 / _15;
|
|
_17 = (long unsigned int) _16;
|
|
cmp2_32 = _17 + 9;
|
|
# DEBUG cmp2 => cmp2_32
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# cmp2_20 = PHI <cmp2_32(5), 0(4)>
|
|
# DEBUG cmp2 => cmp2_20
|
|
# DEBUG BEGIN_STMT
|
|
cmuEntries[2].enable = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = MAX_EXPR <cmp2_20, cmp1_31>;
|
|
_19 = _18 * 10;
|
|
cmuEntries[2].refCount = _19;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_CORE_CLK_B ()
|
|
{
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
float _1;
|
|
float _2;
|
|
float _3;
|
|
float _4;
|
|
float _5;
|
|
long unsigned int _6;
|
|
float _7;
|
|
float _8;
|
|
float _9;
|
|
long unsigned int _10;
|
|
float _11;
|
|
float _12;
|
|
float _13;
|
|
float _14;
|
|
float _15;
|
|
long unsigned int _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
fReferenceClk_19 = tmpData.input2;
|
|
# DEBUG fReferenceClk => fReferenceClk_19
|
|
# DEBUG BEGIN_STMT
|
|
fMonitoredClk_20 = tmpData.input3;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_20
|
|
# DEBUG BEGIN_STMT
|
|
if (fReferenceClk_19 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (float) fMonitoredClk_20;
|
|
_2 = _1 * 1.011e+3;
|
|
_3 = (float) fReferenceClk_19;
|
|
_4 = _3 * 9.67e+2;
|
|
_5 = _2 / _4;
|
|
_6 = cmuEntries[1].refCount;
|
|
_7 = (float) _6;
|
|
_8 = _5 * _7;
|
|
_9 = _8 + 3.0e+0;
|
|
_10 = (long unsigned int) _9;
|
|
cmuEntries[1].hfRef = _10;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = _1 * 9.89e+2;
|
|
_12 = _3 * 1.033e+3;
|
|
_13 = _11 / _12;
|
|
_14 = _7 * _13;
|
|
_15 = _14 - 3.0e+0;
|
|
_16 = (long unsigned int) _15;
|
|
cmuEntries[1].lfRef = _16;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_CORE_CLK_A ()
|
|
{
|
|
uint8 enable;
|
|
uint32 cmp2;
|
|
uint32 cmp1;
|
|
uint32 fBusClk;
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.7_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int configuredCoreClock.8_6;
|
|
long unsigned int configuredAipsSlowClock.9_7;
|
|
long unsigned int _8;
|
|
float _9;
|
|
float _10;
|
|
float _11;
|
|
float _12;
|
|
long unsigned int _13;
|
|
float _14;
|
|
float _15;
|
|
float _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = cmuEntries[1].configIndex;
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.7_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#8 => &config_clock.7_2->cmus[_4]
|
|
# DEBUG cmuConfig => D#8
|
|
# DEBUG BEGIN_STMT
|
|
enable_23 = MEM[(const struct Clock_Ip_CmuConfigType *)config_clock.7_2].cmus[_4].enable;
|
|
# DEBUG enable => enable_23
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# enable_21 = PHI <enable_23(3), 0(2)>
|
|
# DEBUG enable => enable_21
|
|
# DEBUG BEGIN_STMT
|
|
_5 = bufferFreqs[3];
|
|
fReferenceClk_24 = _5 / 1000;
|
|
# DEBUG fReferenceClk => fReferenceClk_24
|
|
# DEBUG BEGIN_STMT
|
|
configuredCoreClock.8_6 = configuredCoreClock;
|
|
fMonitoredClk_25 = configuredCoreClock.8_6 / 1000;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_25
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock.9_7 = configuredAipsSlowClock;
|
|
fBusClk_26 = configuredAipsSlowClock.9_7 / 1000;
|
|
# DEBUG fBusClk => fBusClk_26
|
|
# DEBUG BEGIN_STMT
|
|
_8 = (long unsigned int) enable_21;
|
|
tmpData.input1 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input2 = fReferenceClk_24;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input3 = fMonitoredClk_25;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input4 = fBusClk_26;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (float) fReferenceClk_24;
|
|
_10 = _9 * 3.0e+0;
|
|
_11 = (float) fBusClk_26;
|
|
_12 = _10 / _11;
|
|
_13 = (long unsigned int) _12;
|
|
cmp1_31 = _13 + 1;
|
|
# DEBUG cmp1 => cmp1_31
|
|
# DEBUG BEGIN_STMT
|
|
if (configuredCoreClock.8_6 > 999)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 = _9 * 5.0e+0;
|
|
_15 = (float) fMonitoredClk_25;
|
|
_16 = _14 / _15;
|
|
_17 = (long unsigned int) _16;
|
|
cmp2_32 = _17 + 9;
|
|
# DEBUG cmp2 => cmp2_32
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# cmp2_20 = PHI <cmp2_32(5), 0(4)>
|
|
# DEBUG cmp2 => cmp2_20
|
|
# DEBUG BEGIN_STMT
|
|
cmuEntries[1].enable = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = MAX_EXPR <cmp2_20, cmp1_31>;
|
|
_19 = _18 * 10;
|
|
cmuEntries[1].refCount = _19;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_FXOSC_CLK_B ()
|
|
{
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
float _1;
|
|
float _2;
|
|
float _3;
|
|
float _4;
|
|
float _5;
|
|
long unsigned int _6;
|
|
float _7;
|
|
float _8;
|
|
float _9;
|
|
long unsigned int _10;
|
|
float _11;
|
|
float _12;
|
|
float _13;
|
|
float _14;
|
|
float _15;
|
|
long unsigned int _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
fReferenceClk_19 = tmpData.input2;
|
|
# DEBUG fReferenceClk => fReferenceClk_19
|
|
# DEBUG BEGIN_STMT
|
|
fMonitoredClk_20 = tmpData.input3;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_20
|
|
# DEBUG BEGIN_STMT
|
|
if (fReferenceClk_19 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (float) fMonitoredClk_20;
|
|
_2 = _1 * 1.011e+3;
|
|
_3 = (float) fReferenceClk_19;
|
|
_4 = _3 * 9.67e+2;
|
|
_5 = _2 / _4;
|
|
_6 = cmuEntries[0].refCount;
|
|
_7 = (float) _6;
|
|
_8 = _5 * _7;
|
|
_9 = _8 + 3.0e+0;
|
|
_10 = (long unsigned int) _9;
|
|
cmuEntries[0].hfRef = _10;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = _1 * 9.89e+2;
|
|
_12 = _3 * 1.033e+3;
|
|
_13 = _11 / _12;
|
|
_14 = _7 * _13;
|
|
_15 = _14 - 3.0e+0;
|
|
_16 = (long unsigned int) _15;
|
|
cmuEntries[0].lfRef = _16;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CMU_FXOSC_CLK_A ()
|
|
{
|
|
uint8 enable;
|
|
uint32 cmp2;
|
|
uint32 cmp1;
|
|
uint32 fBusClk;
|
|
uint32 fMonitoredClk;
|
|
uint32 fReferenceClk;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.10_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int configuredAipsSlowClock.11_7;
|
|
long unsigned int _8;
|
|
float _9;
|
|
float _10;
|
|
float _11;
|
|
float _12;
|
|
long unsigned int _13;
|
|
float _14;
|
|
float _15;
|
|
float _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = cmuEntries[0].configIndex;
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.10_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#7 => &config_clock.10_2->cmus[_4]
|
|
# DEBUG cmuConfig => D#7
|
|
# DEBUG BEGIN_STMT
|
|
enable_23 = MEM[(const struct Clock_Ip_CmuConfigType *)config_clock.10_2].cmus[_4].enable;
|
|
# DEBUG enable => enable_23
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# enable_21 = PHI <enable_23(3), 0(2)>
|
|
# DEBUG enable => enable_21
|
|
# DEBUG BEGIN_STMT
|
|
_5 = bufferFreqs[1];
|
|
fReferenceClk_24 = _5 / 1000;
|
|
# DEBUG fReferenceClk => fReferenceClk_24
|
|
# DEBUG BEGIN_STMT
|
|
_6 = bufferFreqs[3];
|
|
fMonitoredClk_25 = _6 / 1000;
|
|
# DEBUG fMonitoredClk => fMonitoredClk_25
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock.11_7 = configuredAipsSlowClock;
|
|
fBusClk_26 = configuredAipsSlowClock.11_7 / 1000;
|
|
# DEBUG fBusClk => fBusClk_26
|
|
# DEBUG BEGIN_STMT
|
|
_8 = (long unsigned int) enable_21;
|
|
tmpData.input1 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input2 = fReferenceClk_24;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input3 = fMonitoredClk_25;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input4 = fBusClk_26;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (float) fReferenceClk_24;
|
|
_10 = _9 * 3.0e+0;
|
|
_11 = (float) fBusClk_26;
|
|
_12 = _10 / _11;
|
|
_13 = (long unsigned int) _12;
|
|
cmp1_31 = _13 + 1;
|
|
# DEBUG cmp1 => cmp1_31
|
|
# DEBUG BEGIN_STMT
|
|
if (_6 > 999)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 = _9 * 5.0e+0;
|
|
_15 = (float) fMonitoredClk_25;
|
|
_16 = _14 / _15;
|
|
_17 = (long unsigned int) _16;
|
|
cmp2_32 = _17 + 9;
|
|
# DEBUG cmp2 => cmp2_32
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# cmp2_20 = PHI <cmp2_32(5), 0(4)>
|
|
# DEBUG cmp2 => cmp2_20
|
|
# DEBUG BEGIN_STMT
|
|
cmuEntries[0].enable = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = MAX_EXPR <cmp2_20, cmp1_31>;
|
|
_19 = _18 * 10;
|
|
cmuEntries[0].refCount = _19;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PCFS_PLL_PHI0_E ()
|
|
{
|
|
uint32 K;
|
|
uint32 RATE;
|
|
uint32 fsafe;
|
|
uint32 finput;
|
|
uint32 stepDuration;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
stepDuration_14 = tmpData.input1;
|
|
# DEBUG stepDuration => stepDuration_14
|
|
# DEBUG BEGIN_STMT
|
|
finput_15 = tmpData.input2;
|
|
# DEBUG finput => finput_15
|
|
# DEBUG BEGIN_STMT
|
|
fsafe_16 = tmpData.input3;
|
|
# DEBUG fsafe => fsafe_16
|
|
# DEBUG BEGIN_STMT
|
|
RATE_17 = tmpData.aux1;
|
|
# DEBUG RATE => RATE_17
|
|
# DEBUG BEGIN_STMT
|
|
_1 = tmpData.aux4;
|
|
_2 = _1 << 2;
|
|
_3 = _2 + 191;
|
|
K_18 = _3 >> 7;
|
|
# DEBUG K => K_18
|
|
# DEBUG BEGIN_STMT
|
|
_4 = stepDuration_14 * fsafe_16;
|
|
pcfsEntries[0].sdur = _4;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = RATE_17 * K_18;
|
|
pcfsEntries[0].divc_init = _5;
|
|
# DEBUG BEGIN_STMT
|
|
pcfsEntries[0].divc_rate = RATE_17;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = K_18 + 1;
|
|
_7 = _5 * _6;
|
|
_8 = _7 >> 1;
|
|
_9 = _8 + 999;
|
|
pcfsEntries[0].div_startValue = _9;
|
|
# DEBUG BEGIN_STMT
|
|
_10 = finput_15 * 1000;
|
|
_11 = _10 / fsafe_16;
|
|
_12 = _11 + 4294967295;
|
|
pcfsEntries[0].div_endValue = _12;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PCFS_PLL_PHI0_D ()
|
|
{
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
|
|
<bb 2> [local count: 118111600]:
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 6>; [100.00%]
|
|
|
|
<bb 3> [local count: 955630223]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = tmpData.aux2;
|
|
_2 = tmpData.aux4;
|
|
_3 = _2 + _10;
|
|
if (_1 >= _3)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 477815111]:
|
|
# DEBUG BEGIN_STMT
|
|
_4 = _1 - _3;
|
|
tmpData.aux2 = _4;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = _10 << 1;
|
|
_6 = _2 + _5;
|
|
tmpData.aux4 = _6;
|
|
|
|
<bb 5> [local count: 955630223]:
|
|
# DEBUG BEGIN_STMT
|
|
_7 = tmpData.aux4;
|
|
_8 = _7 >> 1;
|
|
tmpData.aux4 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = _10 >> 2;
|
|
tmpData.aux3 = _9;
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = tmpData.aux3;
|
|
if (_10 != 0)
|
|
goto <bb 3>; [89.00%]
|
|
else
|
|
goto <bb 7>; [11.00%]
|
|
|
|
<bb 7> [local count: 118111601]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PCFS_PLL_PHI0_C ()
|
|
{
|
|
uint32 RATE;
|
|
uint32 fsafe;
|
|
uint32 finput;
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
|
|
<bb 2> [local count: 118111600]:
|
|
# DEBUG BEGIN_STMT
|
|
finput_11 = tmpData.input2;
|
|
# DEBUG finput => finput_11
|
|
# DEBUG BEGIN_STMT
|
|
fsafe_12 = tmpData.input3;
|
|
# DEBUG fsafe => fsafe_12
|
|
# DEBUG BEGIN_STMT
|
|
RATE_13 = tmpData.aux1;
|
|
# DEBUG RATE => RATE_13
|
|
# DEBUG BEGIN_STMT
|
|
_1 = finput_11 * 2048000;
|
|
_2 = fsafe_12 * RATE_13;
|
|
_3 = _1 / _2;
|
|
_4 = 2048000 / RATE_13;
|
|
_5 = _3 - _4;
|
|
_6 = _5 + 256;
|
|
tmpData.aux2 = _6;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.aux3 = 1073741824;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 4>; [100.00%]
|
|
|
|
<bb 3> [local count: 955630223]:
|
|
# DEBUG BEGIN_STMT
|
|
_7 = _8 >> 2;
|
|
tmpData.aux3 = _7;
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = tmpData.aux3;
|
|
if (_6 < _8)
|
|
goto <bb 3>; [89.00%]
|
|
else
|
|
goto <bb 5>; [11.00%]
|
|
|
|
<bb 5> [local count: 118111601]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PCFS_PLL_PHI0_B ()
|
|
{
|
|
uint8 i;
|
|
uint32 RATE;
|
|
uint32 amaxBrut;
|
|
const uint32 pcfsRate[6];
|
|
const uint32 aMax[6];
|
|
unsigned int _1;
|
|
unsigned int _2;
|
|
long unsigned int _3;
|
|
|
|
<bb 2> [local count: 357985524]:
|
|
# DEBUG BEGIN_STMT
|
|
aMax = *.LC0;
|
|
# DEBUG BEGIN_STMT
|
|
pcfsRate = *.LC1;
|
|
# DEBUG BEGIN_STMT
|
|
amaxBrut_11 = tmpData.aux1;
|
|
# DEBUG amaxBrut => amaxBrut_11
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG RATE => 0
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (amaxBrut_11 > 100)
|
|
goto <bb 7>; [50.00%]
|
|
else
|
|
goto <bb 8>; [50.00%]
|
|
|
|
<bb 8> [local count: 178992762]:
|
|
goto <bb 6>; [100.00%]
|
|
|
|
<bb 3> [local count: 894749063]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned int) i_7;
|
|
_2 = _1 + 4294967295;
|
|
_3 = aMax[_2];
|
|
if (_3 < amaxBrut_11)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 447374531]:
|
|
# DEBUG BEGIN_STMT
|
|
RATE_12 = pcfsRate[_2];
|
|
# DEBUG RATE => RATE_12
|
|
|
|
<bb 5> [local count: 894749063]:
|
|
# RATE_4 = PHI <RATE_5(3), RATE_12(4)>
|
|
# DEBUG RATE => RATE_4
|
|
# DEBUG BEGIN_STMT
|
|
i_13 = i_7 + 1;
|
|
# DEBUG i => i_13
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# RATE_5 = PHI <RATE_4(5), 0(8)>
|
|
# i_7 = PHI <i_13(5), 1(8)>
|
|
# DEBUG i => i_7
|
|
# DEBUG RATE => RATE_5
|
|
# DEBUG BEGIN_STMT
|
|
if (i_7 != 6)
|
|
goto <bb 3>; [83.33%]
|
|
else
|
|
goto <bb 7>; [16.67%]
|
|
|
|
<bb 7> [local count: 357985524]:
|
|
# RATE_6 = PHI <RATE_5(6), 1000(2)>
|
|
# DEBUG RATE => RATE_6
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.aux1 = RATE_6;
|
|
aMax ={v} {CLOBBER};
|
|
pcfsRate ={v} {CLOBBER};
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PCFS_PLL_PHI0_A ()
|
|
{
|
|
uint32 amaxBrut;
|
|
uint32 fsafe;
|
|
uint32 finput;
|
|
uint32 stepDuration;
|
|
uint32 maxAllowableIDDchange;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.13_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = pcfsEntries[0].configIndex;
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.13_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#6 => &config_clock.13_2->pcfs[_4]
|
|
# DEBUG pcfsConfig => D#6
|
|
# DEBUG BEGIN_STMT
|
|
maxAllowableIDDchange_15 = MEM[(const struct Clock_Ip_PcfsConfigType *)config_clock.13_2].pcfs[_4].maxAllowableIDDchange;
|
|
# DEBUG maxAllowableIDDchange => maxAllowableIDDchange_15
|
|
# DEBUG BEGIN_STMT
|
|
stepDuration_16 = MEM[(const struct Clock_Ip_PcfsConfigType *)config_clock.13_2].pcfs[_4].stepDuration;
|
|
# DEBUG stepDuration => stepDuration_16
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG maxAllowableIDDchange => 50
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmPcfs_Type *)1076723712B].PCFS_SDUR;
|
|
stepDuration_14 = _5 & 65535;
|
|
# DEBUG stepDuration => stepDuration_14
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# maxAllowableIDDchange_11 = PHI <maxAllowableIDDchange_15(3), 50(4)>
|
|
# stepDuration_12 = PHI <stepDuration_16(3), stepDuration_14(4)>
|
|
# DEBUG stepDuration => stepDuration_12
|
|
# DEBUG maxAllowableIDDchange => maxAllowableIDDchange_11
|
|
# DEBUG BEGIN_STMT
|
|
_6 = bufferFreqs[26];
|
|
finput_17 = _6 / 1000000;
|
|
# DEBUG finput => finput_17
|
|
# DEBUG BEGIN_STMT
|
|
_7 = bufferFreqs[1];
|
|
fsafe_18 = _7 / 1000000;
|
|
# DEBUG fsafe => fsafe_18
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input1 = stepDuration_12;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input2 = finput_17;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input3 = fsafe_18;
|
|
# DEBUG BEGIN_STMT
|
|
_8 = maxAllowableIDDchange_11 * stepDuration_12;
|
|
_9 = _8 * 100000;
|
|
_10 = finput_17 * 2360;
|
|
amaxBrut_22 = _9 / _10;
|
|
# DEBUG amaxBrut => amaxBrut_22
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.aux1 = amaxBrut_22;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS ()
|
|
{
|
|
const struct Clock_Ip_SelectorConfigType * selectorSCS_CLK;
|
|
uint32 i;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.16_1;
|
|
<unnamed type> _2;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.16_4;
|
|
unsigned char _5;
|
|
long unsigned int _6;
|
|
<unnamed type> _7;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
|
|
<bb 2> [local count: 114863532]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG selectorSCS_CLK => 0B
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => 0
|
|
goto <bb 6>; [100.00%]
|
|
|
|
<bb 3> [local count: 1014686025]:
|
|
# DEBUG BEGIN_STMT
|
|
_2 = config_clock.16_4->selectors[i_13].name;
|
|
if (_2 == 12)
|
|
goto <bb 4>; [5.50%]
|
|
else
|
|
goto <bb 5>; [94.50%]
|
|
|
|
<bb 4> [local count: 55807731]:
|
|
# config_clock.16_1 = PHI <config_clock.16_4(3)>
|
|
# i_3 = PHI <i_13(3)>
|
|
# DEBUG BEGIN_STMT
|
|
selectorSCS_CLK_18 = &config_clock.16_1->selectors[i_3];
|
|
# DEBUG selectorSCS_CLK => selectorSCS_CLK_18
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 7>; [100.00%]
|
|
|
|
<bb 5> [local count: 958878293]:
|
|
# DEBUG BEGIN_STMT
|
|
i_17 = i_13 + 1;
|
|
# DEBUG i => i_17
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# i_13 = PHI <0(2), i_17(5)>
|
|
# DEBUG i => i_13
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.16_4 = config_clock;
|
|
_5 = config_clock.16_4->selectorsCount;
|
|
_6 = (long unsigned int) _5;
|
|
if (_6 > i_13)
|
|
goto <bb 3>; [94.50%]
|
|
else
|
|
goto <bb 7>; [5.50%]
|
|
|
|
<bb 7> [local count: 114863532]:
|
|
# selectorSCS_CLK_14 = PHI <selectorSCS_CLK_18(4), 0B(6)>
|
|
# DEBUG selectorSCS_CLK => selectorSCS_CLK_14
|
|
# DEBUG BEGIN_STMT
|
|
if (selectorSCS_CLK_14 != 0B)
|
|
goto <bb 8>; [70.00%]
|
|
else
|
|
goto <bb 12>; [30.00%]
|
|
|
|
<bb 8> [local count: 80404472]:
|
|
# DEBUG BEGIN_STMT
|
|
_7 = selectorSCS_CLK_14->value;
|
|
switch (_7) <default: <L8> [33.33%], case 0: <L6> [33.33%], case 8: <L7> [33.33%]>
|
|
|
|
<bb 9> [local count: 26801491]:
|
|
<L6>:
|
|
CALCULATE_CONFIGURED_CORE_AIPS_SLOW_PLAT_CLKS.part.0 ();
|
|
goto <bb 13>; [100.00%]
|
|
|
|
<bb 10> [local count: 26798811]:
|
|
<L7>:
|
|
# DEBUG BEGIN_STMT
|
|
_9 = bufferFreqs[28];
|
|
configuredCoreClock = _9;
|
|
# DEBUG BEGIN_STMT
|
|
_10 = bufferFreqs[29];
|
|
configuredAipsPlatClock = _10;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = bufferFreqs[30];
|
|
configuredAipsSlowClock = _11;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = bufferFreqs[31];
|
|
configuredHseClock = _12;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [100.00%]
|
|
|
|
<bb 11> [local count: 26798811]:
|
|
<L8>:
|
|
# DEBUG BEGIN_STMT
|
|
configuredCoreClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsPlatClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredHseClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [100.00%]
|
|
|
|
<bb 12> [local count: 34459060]:
|
|
# DEBUG BEGIN_STMT
|
|
configuredCoreClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsPlatClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredAipsSlowClock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
configuredHseClock = 0;
|
|
|
|
<bb 13> [local count: 114855491]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_K ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.17_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.18_10;
|
|
unsigned int _11;
|
|
unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.19_18;
|
|
unsigned int _19;
|
|
unsigned int _20;
|
|
long unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[20];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.17_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_34 = config_clock.17_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_33 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_33
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_26 = PHI <dividerValue_34(3), dividerValue_33(4)>
|
|
# DEBUG dividerValue => dividerValue_26
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_26 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[31];
|
|
_9 = _8 / dividerValue_26;
|
|
bufferFreqs[38] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[38] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.18_10 = config_clock;
|
|
_11 = (unsigned int) _1;
|
|
_12 = _11 + 4294967295;
|
|
dividerValue_38 = config_clock.18_10->dividers[_12].value;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_14 = _13 >> 16;
|
|
_15 = _14 & 63;
|
|
dividerValue_37 = _15 + 1;
|
|
# DEBUG dividerValue => dividerValue_37
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_38(9), dividerValue_37(10)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = bufferFreqs[29];
|
|
_17 = _16 / dividerValue_27;
|
|
bufferFreqs[39] = _17;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[39] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.19_18 = config_clock;
|
|
_19 = (unsigned int) _1;
|
|
_20 = _19 + 4294967295;
|
|
dividerValue_42 = config_clock.19_18->dividers[_20].value;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_21 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_22 = _21 >> 16;
|
|
_23 = _22 & 63;
|
|
dividerValue_41 = _23 + 1;
|
|
# DEBUG dividerValue => dividerValue_41
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_42(15), dividerValue_41(16)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = bufferFreqs[30];
|
|
_25 = _24 / dividerValue_28;
|
|
bufferFreqs[40] = _25;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[40] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_J ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.20_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.21_10;
|
|
unsigned int _11;
|
|
unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.22_18;
|
|
unsigned int _19;
|
|
unsigned int _20;
|
|
long unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[20];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.20_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_34 = config_clock.20_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_33 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_33
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_26 = PHI <dividerValue_34(3), dividerValue_33(4)>
|
|
# DEBUG dividerValue => dividerValue_26
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_26 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[26];
|
|
_9 = _8 / dividerValue_26;
|
|
bufferFreqs[35] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[35] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.21_10 = config_clock;
|
|
_11 = (unsigned int) _1;
|
|
_12 = _11 + 4294967295;
|
|
dividerValue_38 = config_clock.21_10->dividers[_12].value;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_14 = _13 >> 16;
|
|
_15 = _14 & 63;
|
|
dividerValue_37 = _15 + 1;
|
|
# DEBUG dividerValue => dividerValue_37
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_38(9), dividerValue_37(10)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = bufferFreqs[27];
|
|
_17 = _16 / dividerValue_27;
|
|
bufferFreqs[36] = _17;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[36] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.22_18 = config_clock;
|
|
_19 = (unsigned int) _1;
|
|
_20 = _19 + 4294967295;
|
|
dividerValue_42 = config_clock.22_18->dividers[_20].value;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_21 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_22 = _21 >> 16;
|
|
_23 = _22 & 63;
|
|
dividerValue_41 = _23 + 1;
|
|
# DEBUG dividerValue => dividerValue_41
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_42(15), dividerValue_41(16)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = bufferFreqs[28];
|
|
_25 = _24 / dividerValue_28;
|
|
bufferFreqs[37] = _25;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[37] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_I ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.23_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.24_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
unsigned char _19;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.25_20;
|
|
unsigned int _21;
|
|
unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
long unsigned int _27;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[17];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.23_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_36 = config_clock.23_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_36
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[4];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_35 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_36(3), dividerValue_35(4)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[26];
|
|
_9 = _8 / dividerValue_28;
|
|
bufferFreqs[32] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[32] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[18];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.24_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_40 = config_clock.24_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_40
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[5];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 63;
|
|
dividerValue_39 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_40(9), dividerValue_39(10)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[26];
|
|
_18 = _17 / dividerValue_29;
|
|
bufferFreqs[33] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[33] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = freqPointers[19];
|
|
if (_19 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.25_20 = config_clock;
|
|
_21 = (unsigned int) _19;
|
|
_22 = _21 + 4294967295;
|
|
dividerValue_44 = config_clock.25_20->dividers[_22].value;
|
|
# DEBUG dividerValue => dividerValue_44
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_23 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[6];
|
|
_24 = _23 >> 16;
|
|
_25 = _24 & 63;
|
|
dividerValue_43 = _25 + 1;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_30 = PHI <dividerValue_44(15), dividerValue_43(16)>
|
|
# DEBUG dividerValue => dividerValue_30
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_30 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[26];
|
|
_27 = _26 / dividerValue_30;
|
|
bufferFreqs[34] = _27;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[34] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_H ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.26_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.27_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
unsigned char _19;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.28_20;
|
|
unsigned int _21;
|
|
unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
long unsigned int _27;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[14];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.26_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_36 = config_clock.26_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_36
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[1];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_35 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_36(3), dividerValue_35(4)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[26];
|
|
_9 = _8 / dividerValue_28;
|
|
bufferFreqs[29] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[29] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[15];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.27_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_40 = config_clock.27_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_40
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[2];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 63;
|
|
dividerValue_39 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_40(9), dividerValue_39(10)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[26];
|
|
_18 = _17 / dividerValue_29;
|
|
bufferFreqs[30] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[30] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = freqPointers[16];
|
|
if (_19 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.28_20 = config_clock;
|
|
_21 = (unsigned int) _19;
|
|
_22 = _21 + 4294967295;
|
|
dividerValue_44 = config_clock.28_20->dividers[_22].value;
|
|
# DEBUG dividerValue => dividerValue_44
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_23 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[3];
|
|
_24 = _23 >> 16;
|
|
_25 = _24 & 63;
|
|
dividerValue_43 = _25 + 1;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_30 = PHI <dividerValue_44(15), dividerValue_43(16)>
|
|
# DEBUG dividerValue => dividerValue_30
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_30 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[26];
|
|
_27 = _26 / dividerValue_30;
|
|
bufferFreqs[31] = _27;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[31] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_G ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.29_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.30_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
unsigned char _19;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.31_20;
|
|
unsigned int _21;
|
|
unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
long unsigned int _27;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[8];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.29_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_36 = config_clock.29_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_36
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLODIV[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 15;
|
|
dividerValue_35 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_36(3), dividerValue_35(4)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[25];
|
|
_9 = _8 / dividerValue_28;
|
|
bufferFreqs[26] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[26] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[9];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.30_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_40 = config_clock.30_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_40
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLODIV[1];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 15;
|
|
dividerValue_39 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_40(9), dividerValue_39(10)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[25];
|
|
_18 = _17 / dividerValue_29;
|
|
bufferFreqs[27] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[27] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = freqPointers[13];
|
|
if (_19 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.31_20 = config_clock;
|
|
_21 = (unsigned int) _19;
|
|
_22 = _21 + 4294967295;
|
|
dividerValue_44 = config_clock.31_20->dividers[_22].value;
|
|
# DEBUG dividerValue => dividerValue_44
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_23 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[0];
|
|
_24 = _23 >> 16;
|
|
_25 = _24 & 63;
|
|
dividerValue_43 = _25 + 1;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_30 = PHI <dividerValue_44(15), dividerValue_43(16)>
|
|
# DEBUG dividerValue => dividerValue_30
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_30 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[26];
|
|
_27 = _26 / dividerValue_30;
|
|
bufferFreqs[28] = _27;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[28] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_F ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.32_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.33_10;
|
|
unsigned int _11;
|
|
unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
unsigned char _18;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.34_19;
|
|
unsigned int _20;
|
|
unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[20];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.32_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_35 = config_clock.32_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_34 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_35(3), dividerValue_34(4)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[6];
|
|
_9 = _8 / dividerValue_27;
|
|
bufferFreqs[23] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[23] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.33_10 = config_clock;
|
|
_11 = (unsigned int) _1;
|
|
_12 = _11 + 4294967295;
|
|
dividerValue_39 = config_clock.33_10->dividers[_12].value;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_14 = _13 >> 16;
|
|
_15 = _14 & 63;
|
|
dividerValue_38 = _15 + 1;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_39(9), dividerValue_38(10)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = bufferFreqs[7];
|
|
_17 = _16 / dividerValue_28;
|
|
bufferFreqs[24] = _17;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[24] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_18 = freqPointers[7];
|
|
if (_18 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.34_19 = config_clock;
|
|
_20 = (unsigned int) _18;
|
|
_21 = _20 + 4294967295;
|
|
dividerValue_43 = config_clock.34_19->dividers[_21].value;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_22 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLDV;
|
|
_23 = _22 >> 25;
|
|
dividerValue_42 = _23 & 63;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_43(15), dividerValue_42(16)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = bufferFreqs[5];
|
|
_25 = _24 / dividerValue_29;
|
|
bufferFreqs[25] = _25;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[5];
|
|
bufferFreqs[25] = _26;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_E ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.35_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.36_10;
|
|
unsigned int _11;
|
|
unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.37_18;
|
|
unsigned int _19;
|
|
unsigned int _20;
|
|
long unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[20];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.35_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_34 = config_clock.35_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_33 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_33
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_26 = PHI <dividerValue_34(3), dividerValue_33(4)>
|
|
# DEBUG dividerValue => dividerValue_26
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_26 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[11];
|
|
_9 = _8 / dividerValue_26;
|
|
bufferFreqs[20] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[20] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.36_10 = config_clock;
|
|
_11 = (unsigned int) _1;
|
|
_12 = _11 + 4294967295;
|
|
dividerValue_38 = config_clock.36_10->dividers[_12].value;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_14 = _13 >> 16;
|
|
_15 = _14 & 63;
|
|
dividerValue_37 = _15 + 1;
|
|
# DEBUG dividerValue => dividerValue_37
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_38(9), dividerValue_37(10)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = bufferFreqs[9];
|
|
_17 = _16 / dividerValue_27;
|
|
bufferFreqs[21] = _17;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[21] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.37_18 = config_clock;
|
|
_19 = (unsigned int) _1;
|
|
_20 = _19 + 4294967295;
|
|
dividerValue_42 = config_clock.37_18->dividers[_20].value;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_21 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_22 = _21 >> 16;
|
|
_23 = _22 & 63;
|
|
dividerValue_41 = _23 + 1;
|
|
# DEBUG dividerValue => dividerValue_41
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_42(15), dividerValue_41(16)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = bufferFreqs[10];
|
|
_25 = _24 / dividerValue_28;
|
|
bufferFreqs[22] = _25;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[22] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_D ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.38_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.39_10;
|
|
unsigned int _11;
|
|
unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.40_18;
|
|
unsigned int _19;
|
|
unsigned int _20;
|
|
long unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[20];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.38_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_34 = config_clock.38_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_33 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_33
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_26 = PHI <dividerValue_34(3), dividerValue_33(4)>
|
|
# DEBUG dividerValue => dividerValue_26
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_26 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[3];
|
|
_9 = _8 / dividerValue_26;
|
|
bufferFreqs[17] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[17] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.39_10 = config_clock;
|
|
_11 = (unsigned int) _1;
|
|
_12 = _11 + 4294967295;
|
|
dividerValue_38 = config_clock.39_10->dividers[_12].value;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_14 = _13 >> 16;
|
|
_15 = _14 & 63;
|
|
dividerValue_37 = _15 + 1;
|
|
# DEBUG dividerValue => dividerValue_37
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_38(9), dividerValue_37(10)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = bufferFreqs[4];
|
|
_17 = _16 / dividerValue_27;
|
|
bufferFreqs[18] = _17;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[18] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_1 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.40_18 = config_clock;
|
|
_19 = (unsigned int) _1;
|
|
_20 = _19 + 4294967295;
|
|
dividerValue_42 = config_clock.40_18->dividers[_20].value;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_21 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_22 = _21 >> 16;
|
|
_23 = _22 & 63;
|
|
dividerValue_41 = _23 + 1;
|
|
# DEBUG dividerValue => dividerValue_41
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_42(15), dividerValue_41(16)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = bufferFreqs[8];
|
|
_25 = _24 / dividerValue_28;
|
|
bufferFreqs[19] = _25;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[19] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_C ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.41_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.42_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.43_19;
|
|
unsigned int _20;
|
|
unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[19];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.41_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_35 = config_clock.41_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[6];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_34 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_34
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_27 = PHI <dividerValue_35(3), dividerValue_34(4)>
|
|
# DEBUG dividerValue => dividerValue_27
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_27 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[1];
|
|
_9 = _8 / dividerValue_27;
|
|
bufferFreqs[14] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[14] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[20];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.42_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_39 = config_clock.42_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 63;
|
|
dividerValue_38 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_38
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_39(9), dividerValue_38(10)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[1];
|
|
_18 = _17 / dividerValue_28;
|
|
bufferFreqs[15] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[15] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (_10 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.43_19 = config_clock;
|
|
_20 = (unsigned int) _10;
|
|
_21 = _20 + 4294967295;
|
|
dividerValue_43 = config_clock.43_19->dividers[_21].value;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_22 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].divider[0];
|
|
_23 = _22 >> 16;
|
|
_24 = _23 & 63;
|
|
dividerValue_42 = _24 + 1;
|
|
# DEBUG dividerValue => dividerValue_42
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_43(15), dividerValue_42(16)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_25 = bufferFreqs[2];
|
|
_26 = _25 / dividerValue_29;
|
|
bufferFreqs[16] = _26;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[16] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_B ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.44_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.45_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
unsigned char _19;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.46_20;
|
|
unsigned int _21;
|
|
unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
long unsigned int _27;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[16];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.44_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_36 = config_clock.44_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_36
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[3];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_35 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_36(3), dividerValue_35(4)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[1];
|
|
_9 = _8 / dividerValue_28;
|
|
bufferFreqs[11] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[11] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[17];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.45_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_40 = config_clock.45_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_40
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[4];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 63;
|
|
dividerValue_39 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_40(9), dividerValue_39(10)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[1];
|
|
_18 = _17 / dividerValue_29;
|
|
bufferFreqs[12] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[12] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = freqPointers[18];
|
|
if (_19 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.46_20 = config_clock;
|
|
_21 = (unsigned int) _19;
|
|
_22 = _21 + 4294967295;
|
|
dividerValue_44 = config_clock.46_20->dividers[_22].value;
|
|
# DEBUG dividerValue => dividerValue_44
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_23 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[5];
|
|
_24 = _23 >> 16;
|
|
_25 = _24 & 63;
|
|
dividerValue_43 = _25 + 1;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_30 = PHI <dividerValue_44(15), dividerValue_43(16)>
|
|
# DEBUG dividerValue => dividerValue_30
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_30 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[1];
|
|
_27 = _26 / dividerValue_30;
|
|
bufferFreqs[13] = _27;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[13] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IntegerDividers_A ()
|
|
{
|
|
uint32 dividerValue;
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.47_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.48_11;
|
|
unsigned int _12;
|
|
unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
unsigned char _19;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.49_20;
|
|
unsigned int _21;
|
|
unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
long unsigned int _27;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[13];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.47_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
dividerValue_36 = config_clock.47_2->dividers[_4].value;
|
|
# DEBUG dividerValue => dividerValue_36
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[0];
|
|
_6 = _5 >> 16;
|
|
_7 = _6 & 63;
|
|
dividerValue_35 = _7 + 1;
|
|
# DEBUG dividerValue => dividerValue_35
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# dividerValue_28 = PHI <dividerValue_36(3), dividerValue_35(4)>
|
|
# DEBUG dividerValue => dividerValue_28
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_28 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = bufferFreqs[1];
|
|
_9 = _8 / dividerValue_28;
|
|
bufferFreqs[8] = _9;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[8] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_10 = freqPointers[14];
|
|
if (_10 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.48_11 = config_clock;
|
|
_12 = (unsigned int) _10;
|
|
_13 = _12 + 4294967295;
|
|
dividerValue_40 = config_clock.48_11->dividers[_13].value;
|
|
# DEBUG dividerValue => dividerValue_40
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[1];
|
|
_15 = _14 >> 16;
|
|
_16 = _15 & 63;
|
|
dividerValue_39 = _16 + 1;
|
|
# DEBUG dividerValue => dividerValue_39
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# dividerValue_29 = PHI <dividerValue_40(9), dividerValue_39(10)>
|
|
# DEBUG dividerValue => dividerValue_29
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_29 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 = bufferFreqs[1];
|
|
_18 = _17 / dividerValue_29;
|
|
bufferFreqs[9] = _18;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[9] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = freqPointers[15];
|
|
if (_19 != 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.49_20 = config_clock;
|
|
_21 = (unsigned int) _19;
|
|
_22 = _21 + 4294967295;
|
|
dividerValue_44 = config_clock.49_20->dividers[_22].value;
|
|
# DEBUG dividerValue => dividerValue_44
|
|
goto <bb 17>; [100.00%]
|
|
|
|
<bb 16> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_23 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].divider[2];
|
|
_24 = _23 >> 16;
|
|
_25 = _24 & 63;
|
|
dividerValue_43 = _25 + 1;
|
|
# DEBUG dividerValue => dividerValue_43
|
|
|
|
<bb 17> [local count: 1073741824]:
|
|
# dividerValue_30 = PHI <dividerValue_44(15), dividerValue_43(16)>
|
|
# DEBUG dividerValue => dividerValue_30
|
|
# DEBUG BEGIN_STMT
|
|
if (dividerValue_30 != 0)
|
|
goto <bb 18>; [50.00%]
|
|
else
|
|
goto <bb 19>; [50.00%]
|
|
|
|
<bb 18> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_26 = bufferFreqs[1];
|
|
_27 = _26 / dividerValue_30;
|
|
bufferFreqs[10] = _27;
|
|
goto <bb 20>; [100.00%]
|
|
|
|
<bb 19> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[10] = 0;
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PLL_C ()
|
|
{
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = tmpData.output;
|
|
_2 = tmpData.input1;
|
|
_3 = tmpData.input2;
|
|
_4 = _2 / _3;
|
|
_5 = tmpData.aux2;
|
|
_6 = _4 * _5;
|
|
_7 = _1 + _6;
|
|
# DEBUG BEGIN_STMT
|
|
_8 = tmpData.aux4;
|
|
_9 = tmpData.input4;
|
|
_10 = _8 * _9;
|
|
_11 = _7 + _10;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = tmpData.aux5;
|
|
_13 = _9 * _12;
|
|
_14 = tmpData.aux3;
|
|
_15 = _13 / _14;
|
|
_16 = _11 + _15;
|
|
tmpData.output = _16;
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[5] = _16;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PLL_B ()
|
|
{
|
|
long unsigned int _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = tmpData.input2;
|
|
_2 = _1 << 14;
|
|
_3 = _1 << 11;
|
|
_4 = _2 + _3;
|
|
tmpData.aux3 = _4;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = tmpData.input1;
|
|
_6 = _5 / _4;
|
|
tmpData.aux4 = _6;
|
|
# DEBUG BEGIN_STMT
|
|
_7 = _4 * _6;
|
|
_8 = _5 - _7;
|
|
tmpData.aux5 = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = tmpData.aux1;
|
|
_10 = _5 * _9;
|
|
tmpData.output = _10;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
PLL_A ()
|
|
{
|
|
long unsigned int _1;
|
|
unsigned char _2;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.50_3;
|
|
unsigned int _4;
|
|
unsigned int _5;
|
|
unsigned char _6;
|
|
long unsigned int _7;
|
|
unsigned char _8;
|
|
long unsigned int _9;
|
|
short unsigned int _10;
|
|
long unsigned int _11;
|
|
long unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
long unsigned int _15;
|
|
long unsigned int _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
long unsigned int _20;
|
|
long unsigned int _21;
|
|
long unsigned int _22;
|
|
long unsigned int _23;
|
|
long unsigned int _24;
|
|
long unsigned int _25;
|
|
long unsigned int _26;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = bufferFreqs[3];
|
|
tmpData.input1 = _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = freqPointers[6];
|
|
if (_2 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.50_3 = config_clock;
|
|
_4 = (unsigned int) _2;
|
|
_5 = _4 + 4294967295;
|
|
# DEBUG D#5 => &config_clock.50_3->plls[_5]
|
|
# DEBUG pllConfig => D#5
|
|
# DEBUG BEGIN_STMT
|
|
_6 = MEM[(const struct Clock_Ip_PllConfigType *)config_clock.50_3].plls[_5].predivider;
|
|
_7 = (long unsigned int) _6;
|
|
tmpData.input2 = _7;
|
|
# DEBUG BEGIN_STMT
|
|
_8 = MEM[(const struct Clock_Ip_PllConfigType *)config_clock.50_3].plls[_5].mulFactorDiv;
|
|
_9 = (long unsigned int) _8;
|
|
tmpData.input3 = _9;
|
|
# DEBUG BEGIN_STMT
|
|
_10 = MEM[(const struct Clock_Ip_PllConfigType *)config_clock.50_3].plls[_5].numeratorFracLoopDiv;
|
|
_11 = (long unsigned int) _10;
|
|
tmpData.input4 = _11;
|
|
# DEBUG BEGIN_STMT
|
|
tmpData.input5 = 0;
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_12 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLDV;
|
|
_13 = _12 >> 12;
|
|
_14 = _13 & 7;
|
|
tmpData.input2 = _14;
|
|
# DEBUG BEGIN_STMT
|
|
_15 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLDV;
|
|
_16 = _15 & 255;
|
|
tmpData.input3 = _16;
|
|
# DEBUG BEGIN_STMT
|
|
_17 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLFD;
|
|
_18 = _17 & 32767;
|
|
tmpData.input4 = _18;
|
|
# DEBUG BEGIN_STMT
|
|
_19 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLDV;
|
|
_20 = _19 >> 25;
|
|
_21 = _20 & 63;
|
|
tmpData.input5 = _21;
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_22 = tmpData.input3;
|
|
_23 = tmpData.input2;
|
|
_24 = _22 / _23;
|
|
tmpData.aux1 = _24;
|
|
# DEBUG BEGIN_STMT
|
|
_25 = _23 * _24;
|
|
_26 = _22 - _25;
|
|
tmpData.aux2 = _26;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
IRCOSCS_XOSCS_SERDES_EXTERNAL_CLOCKS ()
|
|
{
|
|
unsigned char _1;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.51_2;
|
|
unsigned int _3;
|
|
unsigned int _4;
|
|
long unsigned int _5;
|
|
unsigned char _6;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.52_7;
|
|
unsigned int _8;
|
|
unsigned int _9;
|
|
long unsigned int _10;
|
|
unsigned char _11;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.53_12;
|
|
unsigned int _13;
|
|
unsigned int _14;
|
|
long unsigned int _15;
|
|
unsigned char _16;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.54_17;
|
|
unsigned int _18;
|
|
unsigned int _19;
|
|
long unsigned int _20;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[4];
|
|
if (_1 != 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.51_2 = config_clock;
|
|
_3 = (unsigned int) _1;
|
|
_4 = _3 + 4294967295;
|
|
# DEBUG D#1 => &config_clock.51_2->xoscs[_4]
|
|
# DEBUG xoscConfig => D#1
|
|
# DEBUG BEGIN_STMT
|
|
_5 = MEM[(const struct Clock_Ip_XoscConfigType *)config_clock.51_2].xoscs[_4].freq;
|
|
bufferFreqs[3] = _5;
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[3] = 16000000;
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_6 = freqPointers[5];
|
|
if (_6 != 0)
|
|
goto <bb 6>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 6> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.52_7 = config_clock;
|
|
_8 = (unsigned int) _6;
|
|
_9 = _8 + 4294967295;
|
|
# DEBUG D#2 => &config_clock.52_7->xoscs[_9]
|
|
# DEBUG xoscConfig => D#2
|
|
# DEBUG BEGIN_STMT
|
|
_10 = MEM[(const struct Clock_Ip_XoscConfigType *)config_clock.52_7].xoscs[_9].freq;
|
|
bufferFreqs[4] = _10;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[4] = 32768;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[2] = 32000;
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[1] = 48000000;
|
|
# DEBUG BEGIN_STMT
|
|
freqPointers[0] = 1;
|
|
# DEBUG BEGIN_STMT
|
|
freqPointers[2] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = freqPointers[10];
|
|
if (_11 != 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.53_12 = config_clock;
|
|
_13 = (unsigned int) _11;
|
|
_14 = _13 + 4294967295;
|
|
# DEBUG D#3 => &config_clock.53_12->extClks[_14]
|
|
# DEBUG extClkConfig => D#3
|
|
# DEBUG BEGIN_STMT
|
|
_15 = MEM[(const struct Clock_Ip_ExtClkConfigType *)config_clock.53_12].extClks[_14].value;
|
|
bufferFreqs[6] = _15;
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 10> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[6] = 0;
|
|
|
|
<bb 11> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = freqPointers[11];
|
|
if (_16 != 0)
|
|
goto <bb 12>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 12> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.54_17 = config_clock;
|
|
_18 = (unsigned int) _16;
|
|
_19 = _18 + 4294967295;
|
|
# DEBUG D#4 => &config_clock.54_17->extClks[_19]
|
|
# DEBUG extClkConfig => D#4
|
|
# DEBUG BEGIN_STMT
|
|
_20 = MEM[(const struct Clock_Ip_ExtClkConfigType *)config_clock.54_17].extClks[_19].value;
|
|
bufferFreqs[7] = _20;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
bufferFreqs[7] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
freqPointers[10] = 6;
|
|
# DEBUG BEGIN_STMT
|
|
freqPointers[11] = 7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
NOT_UNDER_MCU_CONTROL_B ()
|
|
{
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
signed int _5;
|
|
unsigned char _6;
|
|
long unsigned int _7;
|
|
long unsigned int _8;
|
|
long unsigned int _9;
|
|
signed int _10;
|
|
unsigned char _11;
|
|
long unsigned int _12;
|
|
long unsigned int _13;
|
|
long unsigned int _14;
|
|
<unnamed type> _15;
|
|
unsigned char _16;
|
|
long unsigned int _17;
|
|
long unsigned int _18;
|
|
long unsigned int _19;
|
|
<unnamed type> _20;
|
|
clock_element_state_t iftmp.55_21;
|
|
clock_element_state_t iftmp.56_22;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[8];
|
|
if (_1 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 8>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} MEM[(struct MC_ME_Type *)1076740096B].PRTN1_COFB1_STAT;
|
|
_3 = _2 & 16777216;
|
|
if (_3 != 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 7>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLODIV[0];
|
|
_5 = (signed int) _4;
|
|
if (_5 >= 0)
|
|
goto <bb 6>; [59.00%]
|
|
else
|
|
goto <bb 5>; [41.00%]
|
|
|
|
<bb 5> [local count: 110058537]:
|
|
|
|
<bb 6> [local count: 268435456]:
|
|
# iftmp.55_21 = PHI <0(4), 255(5)>
|
|
clkState[8] = iftmp.55_21;
|
|
goto <bb 8>; [100.00%]
|
|
|
|
<bb 7> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[8] = 0;
|
|
|
|
<bb 8> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_6 = freqPointers[9];
|
|
if (_6 == 0)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 14>; [50.00%]
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_7 ={v} MEM[(struct MC_ME_Type *)1076740096B].PRTN1_COFB1_STAT;
|
|
_8 = _7 & 16777216;
|
|
if (_8 != 0)
|
|
goto <bb 10>; [50.00%]
|
|
else
|
|
goto <bb 13>; [50.00%]
|
|
|
|
<bb 10> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
_9 ={v} MEM[(volatile struct PLL_Type *)1076756480B].PLLODIV[1];
|
|
_10 = (signed int) _9;
|
|
if (_10 >= 0)
|
|
goto <bb 12>; [59.00%]
|
|
else
|
|
goto <bb 11>; [41.00%]
|
|
|
|
<bb 11> [local count: 110058537]:
|
|
|
|
<bb 12> [local count: 268435456]:
|
|
# iftmp.56_22 = PHI <0(10), 255(11)>
|
|
clkState[9] = iftmp.56_22;
|
|
goto <bb 14>; [100.00%]
|
|
|
|
<bb 13> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[9] = 0;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[10] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
clkState[11] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = freqPointers[12];
|
|
if (_11 == 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 16>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_12 ={v} MEM[(volatile struct cgmMux_Type *)1076724480B].CSS;
|
|
_13 = _12 >> 24;
|
|
_14 = _13 & 63;
|
|
_15 = selectorEntryIndex[_14];
|
|
clkState[12] = _15;
|
|
|
|
<bb 16> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_16 = freqPointers[20];
|
|
if (_16 == 0)
|
|
goto <bb 17>; [50.00%]
|
|
else
|
|
goto <bb 18>; [50.00%]
|
|
|
|
<bb 17> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_17 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].CSS;
|
|
_18 = _17 >> 24;
|
|
_19 = _18 & 63;
|
|
_20 = selectorEntryIndex[_19];
|
|
clkState[20] = _20;
|
|
|
|
<bb 18> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
NOT_UNDER_MCU_CONTROL_A ()
|
|
{
|
|
unsigned char _1;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
unsigned char _5;
|
|
long unsigned int _6;
|
|
signed int _7;
|
|
unsigned char _8;
|
|
long unsigned int _9;
|
|
long unsigned int _10;
|
|
unsigned char _11;
|
|
long unsigned int _12;
|
|
signed int _13;
|
|
unsigned char _14;
|
|
clock_element_state_t iftmp.57_15;
|
|
clock_element_state_t iftmp.58_16;
|
|
clock_element_state_t iftmp.59_17;
|
|
clock_element_state_t iftmp.60_18;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[0] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = freqPointers[1];
|
|
if (_1 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 6>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} MEM[(struct FIRC_Type *)1076690944B].STDBY_ENABLE;
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 5>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
|
|
<bb 5> [local count: 536870913]:
|
|
# iftmp.57_15 = PHI <0(3), 255(4)>
|
|
clkState[1] = iftmp.57_15;
|
|
|
|
<bb 6> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 = freqPointers[4];
|
|
if (_5 == 0)
|
|
goto <bb 7>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 7> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_6 ={v} MEM[(volatile struct ExtOSC_Type *)1076707328B].STAT;
|
|
_7 = (signed int) _6;
|
|
if (_7 >= 0)
|
|
goto <bb 9>; [59.00%]
|
|
else
|
|
goto <bb 8>; [41.00%]
|
|
|
|
<bb 8> [local count: 220117074]:
|
|
|
|
<bb 9> [local count: 536870913]:
|
|
# iftmp.58_16 = PHI <0(7), 255(8)>
|
|
clkState[4] = iftmp.58_16;
|
|
|
|
<bb 10> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = freqPointers[3];
|
|
if (_8 == 0)
|
|
goto <bb 11>; [50.00%]
|
|
else
|
|
goto <bb 14>; [50.00%]
|
|
|
|
<bb 11> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_9 ={v} MEM[(struct SIRC_Type *)1076658176B].MISCELLANEOUS_IN;
|
|
_10 = _9 & 256;
|
|
if (_10 == 0)
|
|
goto <bb 13>; [50.00%]
|
|
else
|
|
goto <bb 12>; [50.00%]
|
|
|
|
<bb 12> [local count: 268435456]:
|
|
|
|
<bb 13> [local count: 536870913]:
|
|
# iftmp.59_17 = PHI <0(11), 255(12)>
|
|
clkState[3] = iftmp.59_17;
|
|
|
|
<bb 14> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
clkState[2] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
_11 = freqPointers[5];
|
|
if (_11 == 0)
|
|
goto <bb 15>; [50.00%]
|
|
else
|
|
goto <bb 18>; [50.00%]
|
|
|
|
<bb 15> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_12 ={v} MEM[(struct SXOSC_Type *)1076674560B].SXOSC_STAT;
|
|
_13 = (signed int) _12;
|
|
if (_13 >= 0)
|
|
goto <bb 17>; [59.00%]
|
|
else
|
|
goto <bb 16>; [41.00%]
|
|
|
|
<bb 16> [local count: 220117074]:
|
|
|
|
<bb 17> [local count: 536870913]:
|
|
# iftmp.60_18 = PHI <0(15), 255(16)>
|
|
clkState[5] = iftmp.60_18;
|
|
|
|
<bb 18> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_14 = freqPointers[6];
|
|
if (_14 == 0)
|
|
goto <bb 19>; [50.00%]
|
|
else
|
|
goto <bb 20>; [50.00%]
|
|
|
|
<bb 19> [local count: 536870912]:
|
|
NOT_UNDER_MCU_CONTROL_A.part.0 ();
|
|
|
|
<bb 20> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CONFIG_ELEMENTS_MAPPINGS_02 ()
|
|
{
|
|
uint8 j;
|
|
uint8 i;
|
|
int _1;
|
|
<unnamed type> _2;
|
|
int _3;
|
|
unsigned char _4;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.65_5;
|
|
unsigned char _6;
|
|
int _7;
|
|
<unnamed type> _8;
|
|
int _9;
|
|
unsigned char _10;
|
|
const struct Clock_Ip_ClockConfigType * config_clock.65_11;
|
|
unsigned char _12;
|
|
int _13;
|
|
<unnamed type> _14;
|
|
int _15;
|
|
unsigned char _16;
|
|
unsigned char _17;
|
|
<unnamed type> _19;
|
|
int _20;
|
|
<unnamed type> _21;
|
|
unsigned char _22;
|
|
unsigned char _23;
|
|
int _24;
|
|
<unnamed type> _25;
|
|
int _26;
|
|
<unnamed type> _27;
|
|
unsigned char _28;
|
|
unsigned char _29;
|
|
|
|
<bb 2> [local count: 7299031]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => 0
|
|
goto <bb 6>; [100.00%]
|
|
|
|
<bb 3> [local count: 59055797]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) i_30;
|
|
_2 = config_clock.65_5->selectors[_1].name;
|
|
if (_2 <= 20)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 29527898]:
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) _2;
|
|
_4 = i_30 + 1;
|
|
freqPointers[_3] = _4;
|
|
|
|
<bb 5> [local count: 59055797]:
|
|
# DEBUG BEGIN_STMT
|
|
i_60 = i_30 + 1;
|
|
# DEBUG i => i_60
|
|
|
|
<bb 6> [local count: 66354828]:
|
|
# i_30 = PHI <0(2), i_60(5)>
|
|
# DEBUG i => i_30
|
|
# DEBUG BEGIN_STMT
|
|
config_clock.65_5 = config_clock;
|
|
_6 = config_clock.65_5->selectorsCount;
|
|
if (_6 > i_30)
|
|
goto <bb 3>; [89.00%]
|
|
else
|
|
goto <bb 7>; [11.00%]
|
|
|
|
<bb 7> [local count: 7299031]:
|
|
# config_clock.65_11 = PHI <config_clock.65_5(6)>
|
|
goto <bb 11>; [100.00%]
|
|
|
|
<bb 8> [local count: 59055797]:
|
|
# DEBUG BEGIN_STMT
|
|
_7 = (int) i_31;
|
|
_8 = config_clock.65_11->dividers[_7].name;
|
|
if (_8 <= 20)
|
|
goto <bb 9>; [50.00%]
|
|
else
|
|
goto <bb 10>; [50.00%]
|
|
|
|
<bb 9> [local count: 29527899]:
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) _8;
|
|
_10 = i_31 + 1;
|
|
freqPointers[_9] = _10;
|
|
|
|
<bb 10> [local count: 59055797]:
|
|
# DEBUG BEGIN_STMT
|
|
i_58 = i_31 + 1;
|
|
# DEBUG i => i_58
|
|
|
|
<bb 11> [local count: 66354828]:
|
|
# i_31 = PHI <i_58(10), 0(7)>
|
|
# DEBUG i => i_31
|
|
# DEBUG BEGIN_STMT
|
|
_12 = config_clock.65_11->dividersCount;
|
|
if (_12 > i_31)
|
|
goto <bb 8>; [89.00%]
|
|
else
|
|
goto <bb 34>; [11.00%]
|
|
|
|
<bb 34> [local count: 7299031]:
|
|
goto <bb 15>; [100.00%]
|
|
|
|
<bb 12> [local count: 59055798]:
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) i_32;
|
|
_14 = config_clock.65_11->fracDivs[_13].name;
|
|
if (_14 <= 20)
|
|
goto <bb 13>; [50.00%]
|
|
else
|
|
goto <bb 14>; [50.00%]
|
|
|
|
<bb 13> [local count: 29527899]:
|
|
# DEBUG BEGIN_STMT
|
|
_15 = (int) _14;
|
|
_16 = i_32 + 1;
|
|
freqPointers[_15] = _16;
|
|
|
|
<bb 14> [local count: 59055798]:
|
|
# DEBUG BEGIN_STMT
|
|
i_56 = i_32 + 1;
|
|
# DEBUG i => i_56
|
|
|
|
<bb 15> [local count: 66354829]:
|
|
# i_32 = PHI <i_56(14), 0(34)>
|
|
# DEBUG i => i_32
|
|
# DEBUG BEGIN_STMT
|
|
_17 = config_clock.65_11->fracDivsCount;
|
|
if (_17 > i_32)
|
|
goto <bb 12>; [89.00%]
|
|
else
|
|
goto <bb 32>; [11.00%]
|
|
|
|
<bb 32> [local count: 7299031]:
|
|
goto <bb 21>; [100.00%]
|
|
|
|
<bb 16> [local count: 1014686024]:
|
|
# DEBUG BEGIN_STMT
|
|
_19 = pcfsEntries[0].name;
|
|
_20 = (int) i_33;
|
|
_21 = config_clock.65_11->pcfs[_20].name;
|
|
if (_19 == _21)
|
|
goto <bb 17>; [67.00%]
|
|
else
|
|
goto <bb 35>; [33.00%]
|
|
|
|
<bb 35> [local count: 334846388]:
|
|
goto <bb 29>; [100.00%]
|
|
|
|
<bb 17> [local count: 679839636]:
|
|
# DEBUG BEGIN_STMT
|
|
_22 = i_33 + 1;
|
|
pcfsEntries[0].configIndex = _22;
|
|
|
|
<bb 19> [local count: 738895437]:
|
|
# j_43 = PHI <1(17), 0(33)>
|
|
|
|
<bb 29> [local count: 1073741824]:
|
|
# j_35 = PHI <j_43(19), 1(35)>
|
|
# DEBUG j => j_35
|
|
# DEBUG BEGIN_STMT
|
|
if (j_35 == 0)
|
|
goto <bb 16>; [94.50%]
|
|
else
|
|
goto <bb 20>; [5.50%]
|
|
|
|
<bb 20> [local count: 59055800]:
|
|
# DEBUG BEGIN_STMT
|
|
i_53 = i_33 + 1;
|
|
# DEBUG i => i_53
|
|
|
|
<bb 21> [local count: 66354831]:
|
|
# i_33 = PHI <i_53(20), 0(32)>
|
|
# DEBUG i => i_33
|
|
# DEBUG BEGIN_STMT
|
|
_23 = config_clock.65_11->pcfsCount;
|
|
if (_23 > i_33)
|
|
goto <bb 33>; [89.00%]
|
|
else
|
|
goto <bb 30>; [11.00%]
|
|
|
|
<bb 33> [local count: 59055800]:
|
|
goto <bb 19>; [100.00%]
|
|
|
|
<bb 30> [local count: 7299031]:
|
|
goto <bb 27>; [100.00%]
|
|
|
|
<bb 22> [local count: 236223206]:
|
|
# DEBUG BEGIN_STMT
|
|
_24 = (int) j_36;
|
|
_25 = cmuEntries[_24].name;
|
|
_26 = (int) i_34;
|
|
_27 = config_clock.65_11->cmus[_26].name;
|
|
if (_25 == _27)
|
|
goto <bb 23>; [34.00%]
|
|
else
|
|
goto <bb 24>; [66.00%]
|
|
|
|
<bb 23> [local count: 80315890]:
|
|
# DEBUG BEGIN_STMT
|
|
_28 = i_34 + 1;
|
|
cmuEntries[_24].configIndex = _28;
|
|
|
|
<bb 24> [local count: 236223206]:
|
|
# DEBUG BEGIN_STMT
|
|
j_52 = j_36 + 1;
|
|
# DEBUG j => j_52
|
|
|
|
<bb 25> [local count: 295279007]:
|
|
# j_36 = PHI <j_52(24), 0(31)>
|
|
# DEBUG j => j_36
|
|
# DEBUG BEGIN_STMT
|
|
if (j_36 != 4)
|
|
goto <bb 22>; [80.00%]
|
|
else
|
|
goto <bb 26>; [20.00%]
|
|
|
|
<bb 26> [local count: 59055801]:
|
|
# DEBUG BEGIN_STMT
|
|
i_50 = i_34 + 1;
|
|
# DEBUG i => i_50
|
|
|
|
<bb 27> [local count: 66354833]:
|
|
# i_34 = PHI <i_50(26), 0(30)>
|
|
# DEBUG i => i_34
|
|
# DEBUG BEGIN_STMT
|
|
_29 = config_clock.65_11->cmusCount;
|
|
if (_29 > i_34)
|
|
goto <bb 31>; [89.00%]
|
|
else
|
|
goto <bb 28>; [11.00%]
|
|
|
|
<bb 31> [local count: 59055801]:
|
|
goto <bb 25>; [100.00%]
|
|
|
|
<bb 28> [local count: 7299032]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CONFIG_ELEMENTS_MAPPINGS_01 ()
|
|
{
|
|
uint8 i;
|
|
int _1;
|
|
|
|
<bb 2> [local count: 46707770]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG i => 0
|
|
goto <bb 4>; [100.00%]
|
|
|
|
<bb 3> [local count: 1027034056]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) i_3;
|
|
freqPointers[_1] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
i_9 = i_3 + 1;
|
|
# DEBUG i => i_9
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
# i_3 = PHI <0(2), i_9(3)>
|
|
# DEBUG i => i_3
|
|
# DEBUG BEGIN_STMT
|
|
if (i_3 != 22)
|
|
goto <bb 3>; [95.65%]
|
|
else
|
|
goto <bb 5>; [4.35%]
|
|
|
|
<bb 5> [local count: 46707769]:
|
|
# i_4 = PHI <0(4)>
|
|
CONFIG_ELEMENTS_MAPPINGS_01.part.0 ();
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UpdateFrequencies (power_modes_t powerMode)
|
|
{
|
|
uint8 pllEn;
|
|
static const clock_element_state_t convertValueToClockState[256] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 255};
|
|
static const uint8 bufferFreqEntriesCLKOUT_RUN_CLK[3][13] = {"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x0f#\x10\x11\x12$\x13\x14\x15\x16\x17\x18", "\x00\x0f#\x10\x11\x12$%&\'(\x17\x18"};
|
|
static const Clock_Ip_NameType selectorEntriesCLKOUT_RUN_CLK[13] = {21, 0, 8, 2, 4, 5, 9, 13, 16, 14, 15, 10, 11};
|
|
static const uint8 bufferFreqEntriesQSPI_MEM_CLK[3] = "\x00\x0e\"";
|
|
static const uint8 bufferFreqEntriesLBIST_CLK[3] = "\x00\r!";
|
|
static const uint8 bufferFreqEntriesDCM_CLK[3] = "\x00\f ";
|
|
static const uint8 bufferFreqEntriesHSE_CLK[3] = "\x00\v\x1f";
|
|
static const uint8 bufferFreqEntriesAIPS_SLOW_CLK[3] = "\x00\n\x1e";
|
|
static const uint8 bufferFreqEntriesAIPS_PLAT_CLK[3] = "\x00\t\x1d";
|
|
static const uint8 bufferFreqEntriesCORE_CLK[3] = "\x00\b\x1c";
|
|
static const uint8 bufferFreqEntriesSCS_CLK[3] = "\x00\x01\x1a";
|
|
static const Clock_Ip_NameType selectorEntriesSCS_CLK[3] = {21, 0, 8};
|
|
<unnamed type> _1;
|
|
unsigned char _2;
|
|
<unnamed type> _3;
|
|
unsigned char _4;
|
|
<unnamed type> _5;
|
|
unsigned char _6;
|
|
<unnamed type> _7;
|
|
unsigned char _8;
|
|
unsigned char _9;
|
|
<unnamed type> _10;
|
|
unsigned char _11;
|
|
int _12;
|
|
<unnamed type> _13;
|
|
<unnamed type> _14;
|
|
unsigned char _15;
|
|
int _16;
|
|
<unnamed type> _17;
|
|
unsigned char _18;
|
|
unsigned char _19;
|
|
<unnamed type> _20;
|
|
int _21;
|
|
<unnamed type> _22;
|
|
int _23;
|
|
<unnamed type> _24;
|
|
unsigned char _25;
|
|
unsigned char _26;
|
|
unsigned char _27;
|
|
unsigned char _28;
|
|
unsigned char _29;
|
|
unsigned char _30;
|
|
unsigned char _31;
|
|
unsigned char _32;
|
|
unsigned char _33;
|
|
unsigned char _34;
|
|
unsigned char _35;
|
|
unsigned char _36;
|
|
unsigned char _37;
|
|
unsigned char _38;
|
|
unsigned char _39;
|
|
unsigned char _40;
|
|
long unsigned int _41;
|
|
long unsigned int _42;
|
|
long unsigned int _43;
|
|
<unnamed type> _44;
|
|
int _45;
|
|
<unnamed type> _46;
|
|
int _47;
|
|
<unnamed type> _48;
|
|
unsigned char _49;
|
|
unsigned char _50;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = clkState[1];
|
|
_2 = _1 & 1;
|
|
freqPointers[1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = clkState[3];
|
|
_4 = _3 & 2;
|
|
freqPointers[3] = _4;
|
|
# DEBUG BEGIN_STMT
|
|
pllEn_54 = clkState[6];
|
|
# DEBUG pllEn => pllEn_54
|
|
# DEBUG BEGIN_STMT
|
|
_5 = clkState[4];
|
|
_6 = _5 & 3;
|
|
freqPointers[4] = _6;
|
|
# DEBUG BEGIN_STMT
|
|
_7 = clkState[5];
|
|
_8 = _7 & 4;
|
|
freqPointers[5] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
_9 = pllEn_54 & 5;
|
|
freqPointers[6] = _9;
|
|
# DEBUG BEGIN_STMT
|
|
_10 = clkState[8];
|
|
_11 = _10 & pllEn_54;
|
|
_12 = (int) _11;
|
|
_13 = convertValueToClockState[_12];
|
|
clkState[8] = _13;
|
|
# DEBUG BEGIN_STMT
|
|
_14 = clkState[9];
|
|
_15 = _14 & pllEn_54;
|
|
_16 = (int) _15;
|
|
_17 = convertValueToClockState[_16];
|
|
clkState[9] = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = _13 & 26;
|
|
freqPointers[8] = _18;
|
|
# DEBUG BEGIN_STMT
|
|
_19 = _17 & 27;
|
|
freqPointers[9] = _19;
|
|
# DEBUG BEGIN_STMT
|
|
_20 = clkState[12];
|
|
_21 = (int) _20;
|
|
_22 = selectorEntriesSCS_CLK[_21];
|
|
_23 = (int) _22;
|
|
_24 = clkState[_23];
|
|
_25 = bufferFreqEntriesSCS_CLK[_21];
|
|
_26 = _24 & _25;
|
|
freqPointers[12] = _26;
|
|
# DEBUG BEGIN_STMT
|
|
_27 = bufferFreqEntriesCORE_CLK[_21];
|
|
_28 = _24 & _27;
|
|
freqPointers[13] = _28;
|
|
# DEBUG BEGIN_STMT
|
|
_29 = bufferFreqEntriesAIPS_PLAT_CLK[_21];
|
|
_30 = _24 & _29;
|
|
freqPointers[14] = _30;
|
|
# DEBUG BEGIN_STMT
|
|
_31 = bufferFreqEntriesAIPS_SLOW_CLK[_21];
|
|
_32 = _24 & _31;
|
|
freqPointers[15] = _32;
|
|
# DEBUG BEGIN_STMT
|
|
_33 = bufferFreqEntriesHSE_CLK[_21];
|
|
_34 = _24 & _33;
|
|
freqPointers[16] = _34;
|
|
# DEBUG BEGIN_STMT
|
|
_35 = bufferFreqEntriesDCM_CLK[_21];
|
|
_36 = _24 & _35;
|
|
freqPointers[17] = _36;
|
|
# DEBUG BEGIN_STMT
|
|
_37 = bufferFreqEntriesLBIST_CLK[_21];
|
|
_38 = _24 & _37;
|
|
freqPointers[18] = _38;
|
|
# DEBUG BEGIN_STMT
|
|
_39 = bufferFreqEntriesQSPI_MEM_CLK[_21];
|
|
_40 = _24 & _39;
|
|
freqPointers[19] = _40;
|
|
# DEBUG BEGIN_STMT
|
|
_41 ={v} MEM[(volatile struct cgmMux_Type *)1076724864B].CSS;
|
|
_42 = _41 >> 24;
|
|
_43 = _42 & 63;
|
|
_44 = selectorEntryIndex[_43];
|
|
clkState[20] = _44;
|
|
# DEBUG BEGIN_STMT
|
|
_45 = (int) _44;
|
|
_46 = selectorEntriesCLKOUT_RUN_CLK[_45];
|
|
_47 = (int) _46;
|
|
_48 = clkState[_47];
|
|
_49 = bufferFreqEntriesCLKOUT_RUN_CLK[_21][_45];
|
|
_50 = _48 & _49;
|
|
freqPointers[20] = _50;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
GetProducerClockFreq (Clock_Ip_NameType clockName)
|
|
{
|
|
int _1;
|
|
unsigned char _2;
|
|
int _3;
|
|
uint32 _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) clockName_4(D);
|
|
_2 = freqPointers[_1];
|
|
_3 = (int) _2;
|
|
_6 = bufferFreqs[_3];
|
|
return _6;
|
|
|
|
}
|
|
|
|
|
|
SpecificPlatformInitClock (const struct Clock_Ip_ClockConfigType * config)
|
|
{
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
config_clock = config_2(D);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SpecificPeripheralClockInitialization (const struct Clock_IP_SpecificPeriphConfigType * config)
|
|
{
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
GetClockState (Clock_Ip_NameType name)
|
|
{
|
|
clock_element_state_t retValue;
|
|
int _1;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (name_3(D) <= 20)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) name_3(D);
|
|
retValue_6 = clkState[_1];
|
|
# DEBUG retValue => retValue_6
|
|
goto <bb 5>; [100.00%]
|
|
|
|
<bb 4> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
retValue_5 = clkState[21];
|
|
# DEBUG retValue => retValue_5
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# retValue_2 = PHI <retValue_6(3), retValue_5(4)>
|
|
# DEBUG retValue => retValue_2
|
|
# DEBUG BEGIN_STMT
|
|
return retValue_2;
|
|
|
|
}
|
|
|
|
|
|
UpdateClockState (Clock_Ip_NameType name, clock_element_state_t state)
|
|
{
|
|
int _1;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
if (name_3(D) <= 20)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 4>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) name_3(D);
|
|
clkState[_1] = state_5(D);
|
|
|
|
<bb 4> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|