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717 lines
24 KiB
C
717 lines
24 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral :
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file Clock_Ip_Divider.c
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* @version 0.9.0
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*
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* @brief CLOCK driver implementations.
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* @details CLOCK driver implementations.
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*
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* @addtogroup CLOCK_DRIVER Clock Ip Driver
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* @{
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*/
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/**
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* @page misra_violations MISRA-C:2012 violations
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*
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* @section Clock_Ip_Divider_c_REF_1
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* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor
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* directives or comments. AUTOSAR imposes the specification of the sections in which certain parts
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* of the driver must be placed.
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*
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* @section Clock_Ip_Divider_c_REF_2
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* Violates MISRA 2012 Advisory Rule 4.8, This file includes the definition
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* of types but does not use it. Header is common for all files
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*
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*/
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#include "Clock_Ip_Private.h"
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/*==================================================================================================
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SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define CLOCK_IP_DIVIDER_VENDOR_ID_C 43
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#define CLOCK_IP_DIVIDER_AR_RELEASE_MAJOR_VERSION_C 4
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#define CLOCK_IP_DIVIDER_AR_RELEASE_MINOR_VERSION_C 4
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#define CLOCK_IP_DIVIDER_AR_RELEASE_REVISION_VERSION_C 0
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#define CLOCK_IP_DIVIDER_SW_MAJOR_VERSION_C 0
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#define CLOCK_IP_DIVIDER_SW_MINOR_VERSION_C 9
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#define CLOCK_IP_DIVIDER_SW_PATCH_VERSION_C 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same vendor */
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#if (CLOCK_IP_DIVIDER_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
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#error "Clock_Ip_Divider.c and Clock_Ip_Private.h have different vendor ids"
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#endif
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/* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same Autosar version */
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#if ((CLOCK_IP_DIVIDER_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
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(CLOCK_IP_DIVIDER_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
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(CLOCK_IP_DIVIDER_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
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)
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#error "AutoSar Version Numbers of Clock_Ip_Divider.c and Clock_Ip_Private.h are different"
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#endif
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/* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same Software version */
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#if ((CLOCK_IP_DIVIDER_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
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(CLOCK_IP_DIVIDER_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
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(CLOCK_IP_DIVIDER_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
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)
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#error "Software Version Numbers of Clock_Ip_Divider.c and Clock_Ip_Private.h are different"
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#endif
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/* Clock start section code */
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#define MCU_START_SEC_CODE
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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static void Callback_DividerEmpty(Clock_Ip_DividerConfigType const* config);
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#ifdef CGM_X_DE_DIV_STAT_WITHOUT_PHASE
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static void SetCgmXDeDivStatWithoutPhase(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef CGM_X_DE_DIV_WITHOUT_PHASE
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static void SetCgmXDeDivWithoutPhase(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef CGM_X_DE_DIV_STAT_WITH_PHASE
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static void SetCgmXDeDivStatWithPhase(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef PLLDIG_PLL0DIV_DE_DIV_OUTPUT
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static void SetPlldigPll0divDeDivOutput(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef PLL_PLL0DIV_DE_DIV_OUTPUT
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static void SetPllPll0divDeDivOutput(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef PLL_PLLDV_ODIV2_OUTPUT
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static void SetPllPlldvOdiv2Output(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SCG_ASYNC_DIV1
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static void SetScgAsyncDiv1(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SCG_ASYNC_DIV2
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static void SetScgAsyncDiv2(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SCG_DIVCORE
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static void SetScgDivcore(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SCG_DIVBUS
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static void SetScgDivbus(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SCG_DIVSLOW
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static void SetScgDivslow(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef PCC_PCD_DIV_MUL
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static void SetPccPcdDivMul(Clock_Ip_DividerConfigType const* config);
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#endif
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#ifdef SIM_TRACE_DIV_MUL
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static void SetSimTraceDivMul(Clock_Ip_DividerConfigType const* config);
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#endif
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/* Clock stop section code */
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#define MCU_STOP_SEC_CODE
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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/* Clock start constant section data */
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#define MCU_START_SEC_CONST_UNSPECIFIED
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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const dividerCallback dividerCallbacks[DIVIDER_CALLBACKS_COUNT] =
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{
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{
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Callback_DividerEmpty, /* Set */
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},
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#ifdef CGM_X_DE_DIV_STAT_WITHOUT_PHASE
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{
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SetCgmXDeDivStatWithoutPhase, /* Set */
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},
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#endif
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#ifdef CGM_X_DE_DIV_WITHOUT_PHASE
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{
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SetCgmXDeDivWithoutPhase, /* Set */
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},
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#endif
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#ifdef CGM_X_DE_DIV_STAT_WITH_PHASE
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{
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SetCgmXDeDivStatWithPhase, /* Set */
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},
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#endif
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#ifdef PLLDIG_PLL0DIV_DE_DIV_OUTPUT
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{
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SetPlldigPll0divDeDivOutput, /* Set */
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},
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#endif
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#ifdef PLL_PLL0DIV_DE_DIV_OUTPUT
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{
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SetPllPll0divDeDivOutput, /* Set */
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},
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#endif
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#ifdef PLL_PLLDV_ODIV2_OUTPUT
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{
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SetPllPlldvOdiv2Output, /* Set */
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},
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#endif
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#ifdef SCG_ASYNC_DIV1
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{
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SetScgAsyncDiv1, /* Set */
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},
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#endif
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#ifdef SCG_ASYNC_DIV2
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{
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SetScgAsyncDiv2, /* Set */
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},
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#endif
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#ifdef SCG_DIVCORE
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{
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SetScgDivcore, /* Set */
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},
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#endif
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#ifdef SCG_DIVBUS
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{
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SetScgDivbus, /* Set */
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},
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#endif
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#ifdef SCG_DIVSLOW
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{
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SetScgDivslow, /* Set */
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},
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#endif
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#ifdef PCC_PCD_DIV_MUL
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{
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SetPccPcdDivMul, /* Set */
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},
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#endif
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#ifdef SIM_TRACE_DIV_MUL
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{
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SetSimTraceDivMul, /* Set */
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},
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#endif
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};
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/* Clock stop constant section data */
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#define MCU_STOP_SEC_CONST_UNSPECIFIED
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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#define MCU_START_SEC_CODE
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/* Clock start section code */
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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static void Callback_DividerEmpty(Clock_Ip_DividerConfigType const* config)
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{
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(void)config;
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/* No implementation */
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}
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#ifdef CGM_X_DE_DIV_STAT_WITHOUT_PHASE
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static void SetCgmXDeDivStatWithoutPhase(Clock_Ip_DividerConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 selectorIndex = clockFeatures[config->name][SELECTOR_INDEX];
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uint32 dividerIndex = clockFeatures[config->name][DIVIDER_INDEX];
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#if defined(MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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uint32 triggerFeat = clockFeatures[config->name][TRIGGER_FEATURE];
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#endif
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uint32 regValue;
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 DividerStatus;
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boolean immediateTriggerIsUpdated = TRUE;
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/* Program divider value */
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if (config->value != 0U) {
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regValue = cgm[instance][selectorIndex]->divider[dividerIndex];
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regValue &= ~MC_CGM_MUX_DC_DIV_MASK;
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regValue |= MC_CGM_MUX_DC_DIV(config->value-1U);
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cgm[instance][selectorIndex]->divider[dividerIndex] = regValue;
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}
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#if defined(MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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if (triggerFeat == TRIGGER)
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{
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/* Common update is triggered. */
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if ((cgm[instance][selectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK) == MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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{
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immediateTriggerIsUpdated = FALSE;
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}
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}
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#endif
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/* Immediate update is triggered. */
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if (TRUE == immediateTriggerIsUpdated)
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{
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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/* Wait for acknowledge to be cleared. */
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do
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{
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DividerStatus = (cgm[instance][selectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK);
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while ((DividerStatus == MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING) && (FALSE == TimeoutOccurred));
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}
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if (FALSE == TimeoutOccurred)
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{
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/* Enable or Disable the Clock Divider */
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if (config->value != 0U)
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{
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/* Enable divider */
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cgm[instance][selectorIndex]->divider[dividerIndex] |= MC_CGM_MUX_DC_DE_MASK;
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if (DISABLED_CLOCK == GetClockState(config->name))
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{
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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else
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{
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cgm[instance][selectorIndex]->divider[dividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK;
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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}
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else
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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}
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#endif
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#ifdef CGM_X_DE_DIV_WITHOUT_PHASE
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static void SetCgmXDeDivWithoutPhase(Clock_Ip_DividerConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 selectorIndex = clockFeatures[config->name][SELECTOR_INDEX];
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uint32 dividerIndex = clockFeatures[config->name][DIVIDER_INDEX];
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uint32 regValue;
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/* Program divider value */
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if (config->value != 0U) {
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regValue = cgm[instance][selectorIndex]->divider[dividerIndex];
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regValue &= ~MC_CGM_MUX_DC_DIV_MASK;
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regValue |= MC_CGM_MUX_DC_DIV(config->value-1U);
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cgm[instance][selectorIndex]->divider[dividerIndex] = regValue;
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}
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/* Enable or Disable the Clock Divider */
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if (config->value != 0U)
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{
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/* Enable divider */
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cgm[instance][selectorIndex]->divider[dividerIndex] |= MC_CGM_MUX_DC_DE_MASK;
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if (DISABLED_CLOCK == GetClockState(config->name))
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{
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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else
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{
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cgm[instance][selectorIndex]->divider[dividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK;
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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}
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#endif
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#ifdef CGM_X_DE_DIV_STAT_WITH_PHASE
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static void SetCgmXDeDivStatWithPhase(Clock_Ip_DividerConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 selectorIndex = clockFeatures[config->name][SELECTOR_INDEX];
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uint32 dividerIndex = clockFeatures[config->name][DIVIDER_INDEX];
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#if defined(MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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uint32 triggerFeat = clockFeatures[config->name][TRIGGER_FEATURE];
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#endif
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uint32 regValue;
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 DividerStatus;
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boolean immediateTriggerIsUpdated = TRUE;
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/* Program divider value */
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if (config->value != 0U) {
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regValue = cgm[instance][selectorIndex]->divider[dividerIndex];
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regValue &= ~MC_CGM_MUX_DC_DIV_MASK;
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regValue |= MC_CGM_MUX_DC_DIV(config->value-1U);
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cgm[instance][selectorIndex]->divider[dividerIndex] = regValue;
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}
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#if defined(MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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if (triggerFeat == TRIGGER)
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{
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/* Common update is triggered. */
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if ((cgm[instance][selectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK) == MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE)
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{
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immediateTriggerIsUpdated = FALSE;
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}
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}
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#endif
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/* Immediate update is triggered. */
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if (TRUE == immediateTriggerIsUpdated)
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{
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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/* Wait for acknowledge to be cleared. */
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do
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{
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DividerStatus = (cgm[instance][selectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK);
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while ((DividerStatus == MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING) && (FALSE == TimeoutOccurred));
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}
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if (FALSE == TimeoutOccurred)
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{
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/* Update phase value */
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/* Disable clock to update phase */
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cgm[instance][selectorIndex]->divider[dividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK;
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UpdateClockState(config->name, DISABLED_CLOCK);
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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/* Wait for the divider update to complete. */
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do
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{
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DividerStatus = (cgm[instance][selectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK);
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while ((DividerStatus == MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING) && (FALSE == TimeoutOccurred));
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if (FALSE == TimeoutOccurred)
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{
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/* We should now wait for at least one division cycle as per the existing programmed DIV value. */
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/* However, a register write sequence operation will take MUCH longer than one division cycle. */
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/* Therefore, there is no need to perform an explicit wait. */
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regValue = cgm[instance][selectorIndex]->divider[dividerIndex];
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regValue &= ~MC_CGM_MUX_DC_PHASE_MASK;
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regValue |= MC_CGM_MUX_DC_PHASE(config->options[0U]);
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cgm[instance][selectorIndex]->divider[dividerIndex] = regValue;
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}
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else
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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/* Enable Clock Divider */
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if (config->value != 0U)
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{
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cgm[instance][selectorIndex]->divider[dividerIndex] |= MC_CGM_MUX_DC_DE_MASK;
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if (DISABLED_CLOCK == GetClockState(config->name))
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{
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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}
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else
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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}
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#endif
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#ifdef PLLDIG_PLL0DIV_DE_DIV_OUTPUT
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static void SetPlldigPll0divDeDivOutput(Clock_Ip_DividerConfigType const* config)
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{
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 dividerIndex = clockFeatures[config->name][DIVIDER_INDEX];
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uint32 regValue;
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/* Disable divider */
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pll[instance]->PLLODIV[dividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK;
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/* Check if divider is enabled */
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if (config->value != 0U)
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{
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regValue = pll[instance]->PLLODIV[dividerIndex];
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regValue |= PLLDIG_PLLODIV_DE_MASK;
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regValue &= ~PLLDIG_PLLODIV_DIV_MASK;
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regValue |= PLLDIG_PLLODIV_DIV(config->value - 1U);
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pll[instance]->PLLODIV[dividerIndex] = regValue;
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if (DISABLED_CLOCK == GetClockState(config->name))
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{
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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else
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{
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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}
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#endif
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#ifdef PLL_PLL0DIV_DE_DIV_OUTPUT
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static void SetPllPll0divDeDivOutput(Clock_Ip_DividerConfigType const* config)
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{
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 dividerIndex = clockFeatures[config->name][DIVIDER_INDEX];
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uint32 regValue;
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/* Check clock status for PLL device */
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if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U)
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{
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/* Enable clock for PLL device */
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MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ56(1U); /* REQ56: Frequency Modulated Phase-Locked Loop */
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MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
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MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
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MC_ME->CTL_KEY = 0x5AF0; /* Enter key */
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MC_ME->CTL_KEY = 0xA50F; /* Enter inverted key */
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/* Wait until PLL clock is running */
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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do
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{
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while (((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U) && (FALSE == TimeoutOccurred));
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/* timeout notification */
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if (TRUE == TimeoutOccurred)
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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}
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/* Disable divider */
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pll[instance]->PLLODIV[dividerIndex] &= ~PLL_PLLODIV_DE_MASK;
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/* Check if divider is enabled */
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if (config->value != 0U)
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{
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regValue = pll[instance]->PLLODIV[dividerIndex];
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regValue |= PLL_PLLODIV_DE_MASK;
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regValue &= ~PLL_PLLODIV_DIV_MASK;
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regValue |= PLL_PLLODIV_DIV(config->value - 1U);
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pll[instance]->PLLODIV[dividerIndex] = regValue;
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if (DISABLED_CLOCK == GetClockState(config->name))
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{
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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}
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else
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{
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UpdateClockState(config->name, DISABLED_CLOCK);
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}
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}
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#endif
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#ifdef PLL_PLLDV_ODIV2_OUTPUT
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static void SetPllPlldvOdiv2Output(Clock_Ip_DividerConfigType const* config)
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{
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boolean TimeoutOccurred = FALSE;
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uint32 StartTime;
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uint32 ElapsedTime;
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uint32 TimeoutTicks;
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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uint32 regValue, dividerValue;
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/* Check clock status for PLL device */
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if ((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U)
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{
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/* Enable clock for PLL device */
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MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ56(1U); /* REQ56: Frequency Modulated Phase-Locked Loop */
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MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
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MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
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MC_ME->CTL_KEY = 0x5AF0; /* Enter key */
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MC_ME->CTL_KEY = 0xA50F; /* Enter inverted key */
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/* Wait until PLL clock is running */
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ClockStartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_TIMEOUT_VALUE_US);
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do
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{
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TimeoutOccurred = ClockTimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
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}
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while(((MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK) == 0U) && (!TimeoutOccurred));
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/* timeout notification */
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if (TimeoutOccurred)
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{
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/* Report timeout error */
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ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, config->name);
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}
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}
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dividerValue = (config->value != 0U) ? config->value : 1U;
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regValue = pll[instance]->PLLDV;
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regValue &= ~PLL_PLLDV_ODIV2_MASK;
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regValue |= PLL_PLLDV_ODIV2(dividerValue);
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pll[instance]->PLLDV = regValue;
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UpdateClockState(config->name, ENABLED_CLOCK);
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}
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#endif
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#ifdef SCG_ASYNC_DIV1
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static void SetScgAsyncDiv1(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32 regValue;
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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regValue = scgPeriphAsyncDivs[instance].ASYNC_DIV;
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regValue &= SCG_SIRCDIV_SIRCDIV1_MASK;
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regValue |= ((config->value-1U) << SCG_SIRCDIV_SIRCDIV1_SHIFT);
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scgPeriphAsyncDivs[instance].ASYNC_DIV = regValue;
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}
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#endif
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#ifdef SCG_ASYNC_DIV2
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static void SetScgAsyncDiv2(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32 regValue;
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uint32 instance = clockFeatures[config->name][CLOCK_MODULE_INSTANCE];
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regValue = scgPeriphAsyncDivs[instance].ASYNC_DIV;
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regValue &= SCG_SIRCDIV_SIRCDIV2_MASK;
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regValue |= ((config->value-1U) << SCG_SIRCDIV_SIRCDIV2_SHIFT);
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scgPeriphAsyncDivs[instance].ASYNC_DIV = regValue;
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}
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#endif
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#ifdef SCG_DIVCORE
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static void SetScgDivcore(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32_t regValue;
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uint32_t powerModeIndex = clockFeatures[config->name][POWER_MODE_INDEX];
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regValue = scgCCRs[powerModeIndex]->CCR;
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regValue &= SCG_RCCR_DIVCORE_MASK;
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regValue |= ((config->value - 1U) << SCG_RCCR_DIVCORE_SHIFT);
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scgCCRs[powerModeIndex]->CCR = regValue;
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}
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#endif
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#ifdef SCG_DIVBUS
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static void SetScgDivbus(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32_t regValue;
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uint32_t powerModeIndex = clockFeatures[config->name][POWER_MODE_INDEX];
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regValue = scgCCRs[powerModeIndex]->CCR;
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regValue &= SCG_RCCR_DIVBUS_MASK;
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regValue |= ((config->value - 1U) << SCG_RCCR_DIVBUS_SHIFT);
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scgCCRs[powerModeIndex]->CCR = regValue;
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}
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#endif
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#ifdef SCG_DIVSLOW
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static void SetScgDivslow(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32_t regValue;
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uint32_t powerModeIndex = clockFeatures[config->name][POWER_MODE_INDEX];
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regValue = scgCCRs[powerModeIndex]->CCR;
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regValue &= SCG_RCCR_DIVSLOW_MASK;
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regValue |= ((config->value - 1U) << SCG_RCCR_DIVSLOW_SHIFT);
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scgCCRs[powerModeIndex]->CCR = regValue;
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}
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#endif
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#ifdef PCC_PCD_DIV_MUL
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static void SetPccPcdDivMul(Clock_Ip_DividerConfigType const* config)
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{
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status_t result = STATUS_SUCCESS;
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uint32_t regValue;
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regValue = PCC->PCCn[clockFeatures[config->name][PCC_INDEX]];
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regValue |= PCC_PCCn_PCD(config->value); /* Divider */
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regValue |= PCC_PCCn_FRAC(config->optons[0U]); /* Multiplier */
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PCC->PCCn[clockFeatures[config->name][SELECTOR_INDEX]] = regValue;
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}
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#endif
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#ifdef SIM_TRACE_DIV_MUL
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static void SetSimTraceDivMul(Clock_Ip_DividerConfigType const* config)
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{
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SIM->CLKDIV4 |= SIM_CLKDIV4_TRACEDIV(config->value) | /* Divider */
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SIM_CLKDIV4_TRACEFRAC(config->options[0U]); /* Multiplier */
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}
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#endif
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/* Clock stop section code */
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#define MCU_STOP_SEC_CODE
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/**
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* @violates @ref Clock_Ip_Divider_c_REF_1 #include directives should only be preceded by preprocessor
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* directives or comments.
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*/
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#include "Mcu_MemMap.h"
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/*! @}*/
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/*******************************************************************************
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* EOF
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******************************************************************************/
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