mirror of
https://github.com/Dev-KATECH/ADM.git
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116 lines
5.6 KiB
C
116 lines
5.6 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral : SIUL2
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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#ifndef SIUL2_DIO_IP_CFG_H
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#define SIUL2_DIO_IP_CFG_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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#include "S32K344_SIUL2.h"
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define SIUL2_DIO_IP_VENDOR_ID_CFG_H 43
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#define SIUL2_DIO_IP_AR_RELEASE_MAJOR_VERSION_CFG_H 4
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#define SIUL2_DIO_IP_AR_RELEASE_MINOR_VERSION_CFG_H 4
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#define SIUL2_DIO_IP_AR_RELEASE_REVISION_VERSION_CFG_H 0
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#define SIUL2_DIO_IP_SW_MAJOR_VERSION_CFG_H 0
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#define SIUL2_DIO_IP_SW_MINOR_VERSION_CFG_H 9
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#define SIUL2_DIO_IP_SW_PATCH_VERSION_CFG_H 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/*==================================================================================================
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* CONSTANTS
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==================================================================================================*/
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/*==================================================================================================
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* DEFINES AND MACROS
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==================================================================================================*/
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/* Pre-processor switch to enable/disable development error detection for Dio Ip API */
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#define SIUL2_DIO_IP_DEV_ERROR_DETECT (STD_OFF)
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/* Pre-processor switch to enable/disable VirtWrapper support */
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#define DIO_VIRTWRAPPER_SUPPORT (STD_OFF)
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/* GPIO - Peripheral instance base addresses */
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/** Peripheral PTA base address */
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#define PTA_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO0)))
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#define PTA_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO1)))
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/** Peripheral PTB base address */
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#define PTB_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO2)))
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#define PTB_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO3)))
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/** Peripheral PTC base address */
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#define PTC_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO4)))
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#define PTC_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO5)))
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/** Peripheral PTD base address */
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#define PTD_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO6)))
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#define PTD_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO7)))
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/** Peripheral PTE base address */
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#define PTE_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO8)))
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#define PTE_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO9)))
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/** Peripheral PTF base address */
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#define PTF_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO10)))
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#define PTF_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO11)))
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/** Peripheral PTG base address */
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#define PTG_L_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO12)))
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#define PTG_H_HALF ((Siul2_Dio_Ip_GpioType *)(&(SIUL2->PGPDO13)))
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/*==================================================================================================
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* ENUMS
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==================================================================================================*/
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/*==================================================================================================
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* STRUCTURES AND OTHER TYPEDEFS
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL VARIABLE DECLARATIONS
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==================================================================================================*/
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/*==================================================================================================
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* FUNCTION PROTOTYPES
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==================================================================================================*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* SIUL2_DIO_IP_CFG_H */
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/** @} */
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