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ADM/GW/RTD/include/FlexCAN_Ip_HwAccess.h
S2-CHICKEN 77297108b6 VCU C code first commit
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/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral : FLEXCAN
* Dependencies :
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
/**
* @file FlexCAN_Ip_HwAccess.h
*
* @brief FlexCAN HardWare Access Header File
*
* @addtogroup FlexCAN
* @{
*/
#ifndef FLEXCAN_FLEXCAN_IP_HWACCESS_H_
#define FLEXCAN_FLEXCAN_IP_HWACCESS_H_
/*==================================================================================================
* INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include <stdint.h>
#include <stddef.h>
#include "Devassert.h"
#include "FlexCAN_Ip.h"
#include "OsIf.h"
/*==================================================================================================
* SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define FLEXCAN_IP_HWACCESS_VENDOR_ID_H 43
#define FLEXCAN_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION_H 4
#define FLEXCAN_IP_HWACCESS_AR_RELEASE_MINOR_VERSION_H 4
#define FLEXCAN_IP_HWACCESS_AR_RELEASE_REVISION_VERSION_H 0
#define FLEXCAN_IP_HWACCESS_SW_MAJOR_VERSION_H 0
#define FLEXCAN_IP_HWACCESS_SW_MINOR_VERSION_H 9
#define FLEXCAN_IP_HWACCESS_SW_PATCH_VERSION_H 0
/*==================================================================================================
* FILE VERSION CHECKS
==================================================================================================*/
/* Check if current file and FlexCAN_Ip header file are of the same vendor */
#if (FLEXCAN_IP_HWACCESS_VENDOR_ID_H != FLEXCAN_IP_VENDOR_ID_H)
#error "FlexCAN_Ip_HwAccess.h and FlexCAN_Ip.h have different vendor ids"
#endif
/* Check if current file and FlexCAN_Ip header file are of the same Autosar version */
#if ((FLEXCAN_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION_H != FLEXCAN_IP_AR_RELEASE_MAJOR_VERSION_H) || \
(FLEXCAN_IP_HWACCESS_AR_RELEASE_MINOR_VERSION_H != FLEXCAN_IP_AR_RELEASE_MINOR_VERSION_H) || \
(FLEXCAN_IP_HWACCESS_AR_RELEASE_REVISION_VERSION_H != FLEXCAN_IP_AR_RELEASE_REVISION_VERSION_H))
#error "AutoSar Version Numbers of FlexCAN_Ip_HwAccess.h and FlexCAN_Ip.h are different"
#endif
/* Check if current file and FlexCAN_Ip header file are of the same Software version */
#if ((FLEXCAN_IP_HWACCESS_SW_MAJOR_VERSION_H != FLEXCAN_IP_SW_MAJOR_VERSION_H) || \
(FLEXCAN_IP_HWACCESS_SW_MINOR_VERSION_H != FLEXCAN_IP_SW_MINOR_VERSION_H) || \
(FLEXCAN_IP_HWACCESS_SW_PATCH_VERSION_H != FLEXCAN_IP_SW_PATCH_VERSION_H))
#error "Software Version Numbers of FlexCAN_Ip_HwAccess.h and FlexCAN_Ip.h are different"
#endif
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if current file and Devassert header file are of the same version */
/* Check if current file and osif header file are of the same version */
#endif
/*==================================================================================================
* CONSTANTS
==================================================================================================*/
/*==================================================================================================
* DEFINES AND MACROS
==================================================================================================*/
/* @brief Frames available in Rx FIFO flag shift */
#define CAN_LEGACY_RXFIFO_FRAME_AVAILABLE (5U)
/* @brief Rx FIFO warning flag shift */
#define CAN_LEGACY_RXFIFO_WARNING (6U)
/* @brief Rx FIFO overflow flag shift */
#define CAN_LEGACY_RXFIFO_OVERFLOW (7U)
/* @brief Frames available in Enhanced Rx FIFO flag shift */
#define CAN_ENHANCED_RXFIFO_FRAME_AVAILABLE (28U)
/* @brief Enhanced Rx FIFO Watermark Indication flag shift */
#define CAN_ENHANCED_RXFIFO_WATERMARK (29U)
/* @brief Enhanced Rx FIFO Overflow flag shift */
#define CAN_ENHANCED_RXFIFO_OVERFLOW (30U)
/* @brief Enhanced Rx FIFO Underflow flag shift */
#define CAN_ENHANCED_RXFIFO_UNDERFLOW (31U)
/*! @brief FlexCAN Embedded RAM address offset */
#define FEATURE_CAN_RAM_OFFSET (0x00000080u)
#if (STD_ON == FEATURE_CAN_HAS_EXPANDABLE_MEMORY)
/*! @brief FlexCAN Expandable Embedded RAM address offset */
#define FEATURE_CAN_EXP_RAM_OFFSET (0x00001000u)
#endif /* (STD_ON == FEATURE_CAN_HAS_EXPANDABLE_MEMORY) */
/*! @brief FlexCAN Enhanced Fifo Embedded RAM address offset */
#define FEATURE_CAN_ENHANCED_FIFO_RAM_OFFSET (0x00002000u)
#define FLEXCAN_ALL_INT (0x3B0006U) /*!< Masks for wakeup, error, bus off*/
#if (FEATURE_CAN_BUSOFF_ERROR_INTERRUPT_UNIFIED == STD_OFF)
#define BUS_OFF_INT (0xB0004U) /*!< Masks for busOff, Tx/Rx Warning */
#define ERROR_INT (0x300002U) /*!< Masks for ErrorOvr, ErrorFast, Error */
#endif
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT_WIDTH 18
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD_WIDTH 11
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO_WIDTH 3
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP_WIDTH 16
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC_WIDTH 4
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_RTR_WIDTH 1
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_IDE_WIDTH 1
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_SRR_WIDTH 1
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE_WIDTH 4
#define CAN_CS_IDHIT_MASK 0xFF800000u
#define CAN_CS_IDHIT_SHIFT 23
#define CAN_CS_IDHIT_WIDTH 9
#define CAN_MB_EDL_MASK 0x80000000u
#define CAN_MB_BRS_MASK 0x40000000u
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT (31U) /*!< FlexCAN RX FIFO ID filter*/
/*! format A&B RTR mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT (30U) /*!< FlexCAN RX FIFO ID filter*/
/*! format A&B IDE mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT (15U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B RTR-2 mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT (14U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B IDE-2 mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU) /*!< FlexCAN RX FIFO ID filter*/
/*! format A extended mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U) /*!< FlexCAN RX FIFO ID filter*/
/*! format A extended shift.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U) /*!< FlexCAN RX FIFO ID filter*/
/*! format A standard mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U) /*!< FlexCAN RX FIFO ID filter*/
/*! format A standard shift.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x1FFF8000U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B extended mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK1 (0x3FFFU) /*!< FlexCAN RX FIFO ID filter*/
/*! format B extended mask1.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B extended shift 1.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B extended shift 2.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x7FFU) /*!< FlexCAN RX FIFO ID filter*/
/*! format B standard mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B standard shift1.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B standard shift2.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_CMP_SHIFT (15U) /*!< FlexCAN RX FIFO ID filter*/
/*! format B extended compare shift.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_EXT_MASK (0x1FE00000U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_STD_MASK (0x7F8U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C mask.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C shift1.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C shift2.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C shift3.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C shift4.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_EXT_CMP_SHIFT (21U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C extended compare shift.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_STD_CMP_SHIFT (3U) /*!< FlexCAN RX FIFO ID filter*/
/*! format C standard compare shift.*/
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU) /*!< FlexCAN RX FIFO ID filter*/
#if (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON)
#define CAN_ENHANCED_IDHIT_MASK 0x7Fu
#define CAN_ENHANCED_IDHIT_SHIFT 0
#define CAN_ENHANCED_IDHIT_WIDTH 7
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_FSCH_SHIFT (30U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard & Extended FSCH shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_STD_RTR2_SHIFT (27U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard RTR-2 shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_STD_RTR1_SHIFT (11U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard RTR-1 shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_EXT_RTR_SHIFT (29U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Extended RTR shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_STD_SHIFT2 (16U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard ID-2 shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_STD_SHIFT1 (0U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard ID-1 shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_STD_MASK (0x7FFU) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Standard ID mask.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_EXT_SHIFT (0U) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Extended ID shift.*/
#define FLEXCAN_ENHANCED_RX_FIFO_ID_FILTER_EXT_MASK (0x1FFFFFFFU) /*!< FlexCAN Enhanced RX FIFO ID filter*/
/*! Mask for enable\disable all enhanced interrupts */
#define FLEXCAN_ENHACED_RX_FIFO_ALL_INTERRUPT_MASK (FLEXCAN_ERFIER_ERFUFWIE_MASK | FLEXCAN_ERFIER_ERFOVFIE_MASK | \
FLEXCAN_ERFIER_ERFWMIIE_MASK | FLEXCAN_ERFIER_ERFDAIE_MASK)
#endif /* (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_On) */
/* This are for little endians cores and supporting rev32 asm instuction */
#define FlexcanSwapBytesInWordIndex(index) (((index) & ~3U) + (3U - ((index) & 3U)))
#define FlexcanSwapBytesInWord(a, b) REV_BYTES_32(a, b)
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
/*==================================================================================================
* ENUMS
==================================================================================================*/
/*! @brief FlexCAN message buffer CODE for Rx buffers*/
enum
{
FLEXCAN_RX_INACTIVE = 0x0, /*!< MB is not active.*/
FLEXCAN_RX_FULL = 0x2, /*!< MB is full.*/
FLEXCAN_RX_EMPTY = 0x4, /*!< MB is active and empty.*/
FLEXCAN_RX_OVERRUN = 0x6, /*!< MB is overwritten into a full buffer.*/
FLEXCAN_RX_BUSY = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
/*! The CPU must not access the MB.*/
FLEXCAN_RX_RANSWER = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/
/*! and transmit a Response Frame in return.*/
FLEXCAN_RX_NOT_USED = 0xF /*!< Not used*/
};
/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/
enum
{
FLEXCAN_TX_INACTIVE = 0x08, /*!< MB is not active.*/
FLEXCAN_TX_ABORT = 0x09, /*!< MB is aborted.*/
FLEXCAN_TX_DATA = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/
FLEXCAN_TX_REMOTE = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/
FLEXCAN_TX_TANSWER = 0x0E, /*!< MB is a TX Response Request Frame from.*/
/*! an incoming Remote Request Frame.*/
FLEXCAN_TX_NOT_USED = 0xF /*!< Not used*/
};
/*! @brief FlexCAN error interrupt types
*/
typedef enum
{
FLEXCAN_INT_RX_WARNING = FLEXCAN_CTRL1_RWRNMSK_MASK, /*!< RX warning interrupt*/
FLEXCAN_INT_TX_WARNING = FLEXCAN_CTRL1_TWRNMSK_MASK, /*!< TX warning interrupt*/
FLEXCAN_INT_ERR = FLEXCAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt*/
FLEXCAN_INT_ERR_FAST, /*!< Error Fast interrupt*/
FLEXCAN_INT_BUSOFF = FLEXCAN_CTRL1_BOFFMSK_MASK, /*!< Bus off interrupt*/
} flexcan_int_type_t;
/*==================================================================================================
* STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/
/*! @brief FlexCAN Message Buffer code and status for transmit and receive
*/
typedef struct
{
uint32 code; /*!< MB code for TX or RX buffers.*/
/*! Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */
Flexcan_Ip_MsgBuffIdType msgIdType; /*!< Type of message ID (standard or extended)*/
uint32 dataLen; /*!< Length of Data in Bytes*/
boolean fd_enable;
uint8 fd_padding;
boolean enable_brs; /* Enable bit rate switch*/
} Flexcan_Ip_MsbuffCodeStatusType;
/*==================================================================================================
* GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/
/*==================================================================================================
* FUNCTION PROTOTYPES
==================================================================================================*/
#define CAN_START_SEC_CODE
#include "Can_MemMap.h"
void FLEXCAN_ClearMsgBuffIntCmd(FLEXCAN_Type * pBase,
uint8 u8Instance,
uint32 mb_idx,
boolean bIsIntActive);
void FlexCAN_SetErrIntCmd(FLEXCAN_Type * base,
flexcan_int_type_t errType,
boolean enable);
/*!
* @brief Calculate the Individual\Global Mask as format ID type in FIFO Mode.
*
* @param id_type A standard ID or an extended ID
* @param formatType Filter Table Format
* @param mask Mask ID aligned LSB
* @return Mask calculated according to format type
*
*/
uint32 FlexCAN_GetRxFifoMask(Flexcan_Ip_MsgBuffIdType id_type,
Flexcan_Ip_RxFifoIdElementFormatType formatType,
uint32 mask);
#if (FEATURE_CAN_BUSOFF_ERROR_INTERRUPT_UNIFIED == STD_OFF)
/*!
* @brief Clears all other interrupts in ERRSTAT register (Error).
*
* @param base The FlexCAN base address
*/
void FlexCAN_ClearErrIntStatusFlag(FLEXCAN_Type * base);
/*!
* @brief Clears BusOff interrupts in ESR register
*
* @param base The FlexCAN base address
*/
void FlexCAN_ClearBusOffIntStatusFlag(FLEXCAN_Type * base);
#endif /* (FEATURE_CAN_BUSOFF_ERROR_INTERRUPT_UNIFIED == STD_OFF) */
/*!
* @brief Get error interrupts in ESR register
*
* @param u8Instance The FlexCAN instance
*/
boolean FlexCAN_GetErrStatusFlag(uint8 u8Instance);
/*!
* @brief Get BusOff interrupts in ESR register
*
* @param u8Instance The FlexCAN instance
*/
boolean FlexCAN_GetBusOffStatusFlag(uint8 u8Instance);
/*!
* @brief Writes the abort code into the CODE field of the requested Tx message buffer.
*
* @param base The FlexCAN base address
* @param msgBuffIdx The requested Tx message buffer
*/
void FlexCAN_AbortTxMsgBuff(const FLEXCAN_Type * base,
uint32 msgBuffIdx);
Flexcan_Ip_StatusType FlexCAN_EnterFreezeMode(FLEXCAN_Type * base);
/*!
* @brief Sets the FlexCAN Rx FIFO fields.
*
* @param base The FlexCAN base address
* @param idFormat The format of the Rx FIFO ID Filter Table Elements
* @param idFilterTable The ID filter table elements which contain RTR bit,
* IDE bit, and RX message ID.
*/
void FlexCAN_SetRxFifoFilter(FLEXCAN_Type * base,
Flexcan_Ip_RxFifoIdElementFormatType idFormat,
const Flexcan_Ip_IdTableType * idFilterTable);
/*!
* @brief Gets the FlexCAN Rx FIFO data.
*
* @param base The FlexCAN base address
* @param rxFifo The FlexCAN receive FIFO data
*/
void FlexCAN_ReadRxFifo(const FLEXCAN_Type * base,
Flexcan_Ip_MsgBuffType * rxFifo);
/*!
* @brief Un freezes the FlexCAN module.
*
* @param base The FlexCAN base address
* @return FLEXCAN_STATUS_SUCCESS successfully exit from freeze
* FLEXCAN_STATUS_TIMEOUT fail to exit from freeze
*/
Flexcan_Ip_StatusType FlexCAN_ExitFreezeMode(FLEXCAN_Type * base);
Flexcan_Ip_StatusType FlexCAN_Disable(FLEXCAN_Type * base);
Flexcan_Ip_StatusType FlexCAN_Enable(FLEXCAN_Type * base);
/*!
* @brief Locks the FlexCAN Rx message buffer.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
*
*/
void FlexCAN_LockRxMsgBuff(const FLEXCAN_Type * base,
uint32 msgBuffIdx);
/*!
* @brief Enables/Disables the FlexCAN Message Buffer interrupt.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @param enable choose enable or disable
* @return FLEXCAN_STATUS_SUCCESS if successful;
* FLEXCAN_STATUS_CAN_BUFF_OUT_OF_RANGE if the index of the
* message buffer is invalid
*/
Flexcan_Ip_StatusType FlexCAN_SetMsgBuffIntCmd(FLEXCAN_Type * base,
uint8 u8Instance,
uint32 msgBuffIdx,
boolean enable,
boolean bIsIntActive);
/*!
* @brief Disable all interrupts.
*
* @param pBase The FlexCAN base address
*/
void FlexCAN_DisableInterrupts(FLEXCAN_Type * pBase);
/*!
* @brief Enable all interrupts configured.
*
* @param pBase The FlexCAN base address
* @param u8Instance A FlexCAN instance number
*/
void FlexCAN_EnableInterrupts(FLEXCAN_Type * pBase, uint8 u8Instance);
/*!
* @brief Sets the FlexCAN message buffer fields for transmitting.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @param cs CODE/status values (TX)
* @param msgId ID of the message to transmit
* @param msgData Bytes of the FlexCAN message
* @param isRemote Will set RTR remote Flag
* @return FLEXCAN_STATUS_SUCCESS if successful;
* FLEXCAN_STATUS_CAN_BUFF_OUT_OF_RANGE if the index of the
* message buffer is invalid
*/
void FlexCAN_SetTxMsgBuff(const FLEXCAN_Type * base,
uint32 msgBuffIdx,
const Flexcan_Ip_MsbuffCodeStatusType * cs,
uint32 msgId,
const uint8 * msgData,
const boolean isRemote);
/*!
* @brief Enables the Rx FIFO.
*
* @param base The FlexCAN base address
* @param numOfFilters The number of Rx FIFO filters
* @return The status of the operation
* @retval FLEXCAN_STATUS_SUCCESS RxFIFO was successfully enabled
* @retval FLEXCAN_STATUS_ERROR RxFIFO could not be enabled (e.g. the FD feature
* was enabled, and these two features are not compatible)
*/
Flexcan_Ip_StatusType FlexCAN_EnableRxFifo(FLEXCAN_Type * base,
uint32 numOfFilters);
/*!
* @brief Sets the maximum number of Message Buffers.
*
* @param base The FlexCAN base address
* @param maxMsgBuffNum Maximum number of message buffers
* @return FLEXCAN_STATUS_SUCCESS if successful;
* FLEXCAN_STATUS_BUFF_OUT_OF_RANGE if the index of the
* message buffer is invalid
*/
Flexcan_Ip_StatusType FlexCAN_SetMaxMsgBuffNum(FLEXCAN_Type * base,
uint32 maxMsgBuffNum);
/*!
* @brief Sets the FlexCAN message buffer fields for receiving.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @param cs CODE/status values (RX)
* @param msgId ID of the message to receive
* @return FLEXCAN_STATUS_SUCCESS if successful;
* FLEXCAN_STATUS_BUFF_OUT_OF_RANGE if the index of the
* message buffer is invalid
*/
void FlexCAN_SetRxMsgBuff(const FLEXCAN_Type * base,
uint32 msgBuffIdx,
const Flexcan_Ip_MsbuffCodeStatusType * cs,
uint32 msgId);
/*!
* @brief Gets the message buffer timestamp value.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @return value of timestamp for selected message buffer.
*/
uint32 FlexCAN_GetMsgBuffTimestamp(const FLEXCAN_Type * base, uint32 msgBuffIdx);
/*!
* @brief Gets the FlexCAN message buffer fields.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @param msgBuff The fields of the message buffer
*/
void FlexCAN_GetMsgBuff(const FLEXCAN_Type * base,
uint32 msgBuffIdx,
Flexcan_Ip_MsgBuffType * msgBuff);
#if (FEATURE_CAN_HAS_FD == STD_ON)
/*!
* @brief Sets the payload size of the MBs.
*
* @param base The FlexCAN base address
* @param payloadSize The payload size
*/
void FlexCAN_SetPayloadSize(FLEXCAN_Type * base,
const Flexcan_Ip_PayloadSizeType * payloadSize);
/*!
* @brief Check If mb index is out of range or not.
*
* @param pBase The FlexCAN base address
* @param u8MbIndex MB index
* @param bIsLegacyFifoEn Legacy fifo enabled or not
* @param u32MaxMbNum Max mb number
*/
boolean FlexCAN_IsMbOutOfRange
(
const FLEXCAN_Type * pBase,
uint8 u8MbIndex,
boolean bIsLegacyFifoEn,
uint32 u32MaxMbNum
);
/*!
* @brief Sets the FlexCAN RX FIFO global mask.
*
* @param[in] base The FlexCAN base address
* @param[in] Mask Sets mask
*/
static inline void FlexCAN_SetRxFifoGlobalMask(FLEXCAN_Type * base,
uint32 Mask)
{
(base->RXFGMASK) = Mask;
}
/*!
* @brief Enables/Disables the Transceiver Delay Compensation feature and sets
* the Transceiver Delay Compensation Offset (offset value to be added to the
* measured transceiver's loop delay in order to define the position of the
* delayed comparison point when bit rate switching is active).
*
* @param base The FlexCAN base address
* @param enable Enable/Disable Transceiver Delay Compensation
* @param offset Transceiver Delay Compensation Offset
*/
static inline void FlexCAN_SetTDCOffset(FLEXCAN_Type * base,
boolean enable,
uint8 offset)
{
uint32 tmp;
tmp = base->FDCTRL;
tmp &= ~(FLEXCAN_FDCTRL_TDCEN_MASK | FLEXCAN_FDCTRL_TDCOFF_MASK);
if (enable)
{
tmp = tmp | FLEXCAN_FDCTRL_TDCEN_MASK;
tmp = tmp | FLEXCAN_FDCTRL_TDCOFF(offset);
}
base->FDCTRL = tmp;
}
/*!
* @brief Enables/Disables the Transceiver Delay Compensation feature and sets
* the Transceiver Delay Compensation Offset (offset value to be added to the
* measured transceiver's loop delay in order to define the position of the
* delayed comparison point when bit rate switching is active).
*
* @param base The FlexCAN base address
* @param enable Enable/Disable Transceiver Delay Compensation
* @param offset Transceiver Delay Compensation Offset
*/
static inline void FlexCAN_SetEnhancedTDCOffset(FLEXCAN_Type * base,
boolean enable,
uint8 offset)
{
uint32 tmp;
tmp = base->ETDC;
tmp &= ~(FLEXCAN_ETDC_ETDCEN_MASK | FLEXCAN_ETDC_ETDCOFF_MASK);
if (enable)
{
tmp = tmp | FLEXCAN_ETDC_ETDCEN_MASK;
tmp = tmp | FLEXCAN_ETDC_ETDCOFF(offset);
}
base->ETDC = tmp;
}
#endif /* FEATURE_CAN_HAS_FD */
/*!
* @brief Gets the payload size of the Ramblock.
*
* @param base The FlexCAN base address
* @return The payload size in bytes
*/
uint8 FlexCAN_GetPayloadSize(const FLEXCAN_Type * base, uint8 mbdsrIdx);
/*!
* @brief Gets the payload size of the MBs.
*
* @param base The FlexCAN base address
* @return The payload size in bytes
*/
uint8 FlexCAN_GetMbPayloadSize(const FLEXCAN_Type * base, uint32 maxMsgBuffNum);
/*!
* @brief Initializes the FlexCAN controller.
*
* @param base The FlexCAN base address
*/
Flexcan_Ip_StatusType FlexCAN_Init(FLEXCAN_Type * base);
/*!
* @brief Checks if the FlexCAN is enabled.
*
* @param base The FlexCAN base address
* @return TRUE if enabled; FALSE if disabled
*/
static inline boolean FlexCAN_IsEnabled(const FLEXCAN_Type * pBase)
{
return (((pBase->MCR & FLEXCAN_MCR_MDIS_MASK) >> FLEXCAN_MCR_MDIS_SHIFT) != 0U) ? FALSE : TRUE;
}
#if (FEATURE_CAN_HAS_MEM_ERR_DET == STD_ON)
/*!
* @brief Disable Error Detection and Correction of Memory Errors.
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_DisableMemErrorDetection(FLEXCAN_Type * base)
{
/* Enable write of MECR register */
base->CTRL2 |= FLEXCAN_CTRL2_ECRWRE(1);
/* Enable write of MECR */
base->MECR = FLEXCAN_MECR_ECRWRDIS(0);
/* Disable Error Detection and Correction mechanism,
* that will set CAN in Freez Mode in case of trigger */
base->MECR = FLEXCAN_MECR_NCEFAFRZ(0);
/* Disable memory error correction */
base->MECR |= FLEXCAN_MECR_ECCDIS(1);
/* Disable write of MECR */
base->CTRL2 |= FLEXCAN_CTRL2_ECRWRE(0);
}
#endif /* FEATURE_CAN_HAS_MEM_ERR_DET */
/*!
* @brief Enables/Disables Flexible Data rate (if supported).
*
* @param base The FlexCAN base address
* @param enable TRUE to enable; FALSE to disable
*/
static inline void FlexCAN_SetFDEnabled(FLEXCAN_Type * base,
boolean enableFD,
boolean enableBRS)
{
base->MCR = (base->MCR & ~FLEXCAN_MCR_FDEN_MASK) | FLEXCAN_MCR_FDEN(enableFD ? 1UL : 0UL);
/* Enable BitRate Switch support from BRS_TX_MB field or ignore it */
base->FDCTRL = (base->FDCTRL & ~FLEXCAN_FDCTRL_FDRATE_MASK) | FLEXCAN_FDCTRL_FDRATE(enableBRS ? 1UL : 0UL);
/* Disable Transmission Delay Compensation by default */
base->FDCTRL &= ~(FLEXCAN_FDCTRL_TDCEN_MASK | FLEXCAN_FDCTRL_TDCOFF_MASK);
}
/*!
* @brief Enables/Disables Listen Only Mode.
*
* @param base The FlexCAN base address
* @param enable TRUE to enable; FALSE to disable
*/
static inline void FlexCAN_SetListenOnlyMode(FLEXCAN_Type * base,
boolean enableListenOnly)
{
base->CTRL1 = (base->CTRL1 & ~FLEXCAN_CTRL1_LOM_MASK) | FLEXCAN_CTRL1_LOM(enableListenOnly ? 1UL : 0UL);
}
#if (FEATURE_CAN_HAS_DMA_ENABLE == STD_ON)
/*!
* @brief Clears the FIFO
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_ClearFIFO(FLEXCAN_Type * base)
{
base->IFLAG1 = FLEXCAN_IFLAG1_BUF0I_MASK;
}
/*!
* @brief Enables/Disables the DMA support for RxFIFO.
*
* @param base The FlexCAN base address
* @param enable Enable/Disable DMA support
*/
static inline void FlexCAN_SetRxFifoDMA(FLEXCAN_Type * base,
boolean enable)
{
base->MCR = (base->MCR & ~FLEXCAN_MCR_DMA_MASK) | FLEXCAN_MCR_DMA(enable ? 1UL : 0UL);
}
#if (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON)
/*!
* @brief Resets Enhanced Rx FIFO engine and state.
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_ClearEnhancedRxFifoEngine(FLEXCAN_Type * base)
{
base->ERFSR = base->ERFSR | FLEXCAN_ERFSR_ERFCLR_MASK;
}
/*!
* @brief Clears the Enhanced Rx FIFO
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_ClearEnhancedFIFO(FLEXCAN_Type * base)
{
base->ERFSR = FLEXCAN_ERFSR_ERFCLR_MASK;
}
/*!
* @brief Configure the number of words to transfer for each Enhanced Rx FIFO data element in DMA mode.
*
* @param base The FlexCAN base address
* @param numOfWords The number of words to transfer
*/
static inline void FlexCAN_ConfigEnhancedRxFifoDMA(FLEXCAN_Type * base,
uint32 numOfWords)
{
base->ERFCR = (base->ERFCR & (~FLEXCAN_ERFCR_DMALW_MASK)) | (((numOfWords - 1u) << FLEXCAN_ERFCR_DMALW_SHIFT) & FLEXCAN_ERFCR_DMALW_MASK);
}
/*!
* @brief Gets the number of bytes to transfer for each Enhanced Rx FIFO data element using DMA
*
* @param base The FlexCAN base address
* @return the number of bytes to transfer for each Enhanced Rx FIFO data element using DMA
*/
static inline uint32 FlexCAN_GetNumOfByteToTransfer(FLEXCAN_Type * base)
{
/* The number of bytes to transfer for each Enhanced Rx FIFO data element using DMA */
return (uint32)((((base->ERFCR & FLEXCAN_ERFCR_DMALW_MASK) >> FLEXCAN_ERFCR_DMALW_SHIFT) + 1U) * 4U);
}
#endif /* FEATURE_CAN_HAS_ENHANCED_RX_FIFO */
#endif /* if FEATURE_CAN_HAS_DMA_ENABLE */
/*!
* @brief Get The Max no of MBs allowed on CAN instance.
*
* @param base The FlexCAN base address
* @return The Max No of MBs on the CAN instance;
*/
uint32 FlexCAN_GetMaxMbNum(const FLEXCAN_Type * base);
/*!
* @brief Unlocks the FlexCAN Rx message buffer.
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_UnlockRxMsgBuff(const FLEXCAN_Type * base)
{
/* Unlock the mailbox by reading the free running timer */
(void)base->TIMER;
}
/*!
* @brief Clears the interrupt flag of the message buffers.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
*/
static inline void FlexCAN_ClearMsgBuffIntStatusFlag(FLEXCAN_Type * base,
uint32 msgBuffIdx)
{
uint32 flag = ((uint32)1U << (msgBuffIdx % 32U));
/* Clear the corresponding message buffer interrupt flag*/
if (msgBuffIdx < 32U)
{
(base->IFLAG1) = (flag);
}
#if FEATURE_CAN_MAX_MB_NUM > 32U
else if (msgBuffIdx < 64U)
{
(base->IFLAG2) = (flag);
}
#if FEATURE_CAN_MAX_MB_NUM <= 64U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif
#endif /* if FEATURE_CAN_MAX_MB_NUM > 32U */
#if FEATURE_CAN_MAX_MB_NUM > 64U
else if (msgBuffIdx < 96U)
{
(base->IFLAG3) = (flag);
}
#if FEATURE_CAN_MAX_MB_NUM <= 96U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif
#endif /* if FEATURE_CAN_MAX_MB_NUM > 64U */
#if FEATURE_CAN_MAX_MB_NUM > 96U
else
{
(base->IFLAG4) = (flag);
}
#endif
}
/*!
* @brief Get the interrupt flag of the message buffers.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @return flag The value of interrupt flag of the message buffer.
*/
static inline uint8 FlexCAN_GetBuffStatusFlag(const FLEXCAN_Type * base,
uint32 msgBuffIdx)
{
uint32 flag = 0U;
if (msgBuffIdx < 32U)
{
flag = ((base->IFLAG1 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM > 32U
else if (msgBuffIdx < 64U)
{
flag = ((base->IFLAG2 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM <= 64U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif /* FEATURE_CAN_MAX_MB_NUM <= 64U */
#endif /* FEATURE_CAN_MAX_MB_NUM > 32U */
#if FEATURE_CAN_MAX_MB_NUM > 64U
else if (msgBuffIdx < 96U)
{
flag = ((base->IFLAG3 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM <= 96U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif /* FEATURE_CAN_MAX_MB_NUM <= 96U */
#endif /* FEATURE_CAN_MAX_MB_NUM > 64U */
#if FEATURE_CAN_MAX_MB_NUM > 96U
else
{
flag = ((base->IFLAG4 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#endif
return (uint8)flag;
}
/*!
* @brief Get the interrupt Imask of the message buffers.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @return Imask The value of interrupt Imask of the message buffer.
*/
static inline uint8 FlexCAN_GetBuffStatusImask(const FLEXCAN_Type * base,
uint32 msgBuffIdx)
{
uint32 u32Imask = 0U;
if (msgBuffIdx < 32U)
{
u32Imask = ((base->IMASK1 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM > 32U
else if (msgBuffIdx < 64U)
{
u32Imask = ((base->IMASK2 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM <= 64U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif /* FEATURE_CAN_MAX_MB_NUM <= 64U */
#endif /* FEATURE_CAN_MAX_MB_NUM > 32U */
#if FEATURE_CAN_MAX_MB_NUM > 64U
else if (msgBuffIdx < 96U)
{
u32Imask = ((base->IMASK3 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#if FEATURE_CAN_MAX_MB_NUM <= 96U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif /* FEATURE_CAN_MAX_MB_NUM <= 96U */
#endif /* FEATURE_CAN_MAX_MB_NUM > 64U */
#if FEATURE_CAN_MAX_MB_NUM > 96U
else
{
u32Imask = ((base->IMASK4 & ((uint32)1U << (msgBuffIdx % 32U))) >> (msgBuffIdx % 32U));
}
#endif
return (uint8)u32Imask;
}
#if (FEATURE_CAN_HAS_FD == STD_ON)
/*!
* @brief Sets the FlexCAN time segments for setting up bit rate for FD BRS.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_SetFDTimeSegments(FLEXCAN_Type * base,
const Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
/* Set FlexCAN time segments*/
(base->FDCBT) = ((base->FDCBT) & ~((FLEXCAN_FDCBT_FPROPSEG_MASK | FLEXCAN_FDCBT_FPSEG2_MASK |
FLEXCAN_FDCBT_FPSEG1_MASK | FLEXCAN_FDCBT_FPRESDIV_MASK) |
FLEXCAN_FDCBT_FRJW_MASK));
(base->FDCBT) = ((base->FDCBT) | (FLEXCAN_FDCBT_FPROPSEG(timeSeg->propSeg) |
FLEXCAN_FDCBT_FPSEG2(timeSeg->phaseSeg2) |
FLEXCAN_FDCBT_FPSEG1(timeSeg->phaseSeg1) |
FLEXCAN_FDCBT_FPRESDIV(timeSeg->preDivider) |
FLEXCAN_FDCBT_FRJW(timeSeg->rJumpwidth)));
}
#endif /* FEATURE_CAN_HAS_FD */
/*!
* @brief Sets the FlexCAN time segments for setting up bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_SetTimeSegments(FLEXCAN_Type * base,
const Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
(base->CTRL1) = ((base->CTRL1) & ~((FLEXCAN_CTRL1_PROPSEG_MASK | FLEXCAN_CTRL1_PSEG2_MASK |
FLEXCAN_CTRL1_PSEG1_MASK | FLEXCAN_CTRL1_PRESDIV_MASK) |
FLEXCAN_CTRL1_RJW_MASK));
(base->CTRL1) = ((base->CTRL1) | (FLEXCAN_CTRL1_PROPSEG(timeSeg->propSeg) |
FLEXCAN_CTRL1_PSEG2(timeSeg->phaseSeg2) |
FLEXCAN_CTRL1_PSEG1(timeSeg->phaseSeg1) |
FLEXCAN_CTRL1_PRESDIV(timeSeg->preDivider) |
FLEXCAN_CTRL1_RJW(timeSeg->rJumpwidth)));
}
/*!
* @brief Sets the FlexCAN extended time segments for setting up bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_SetExtendedTimeSegments(FLEXCAN_Type * base,
const Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
/* If extended bit time definitions are enabled, use CBT register */
(base->CBT) = ((base->CBT) & ~((FLEXCAN_CBT_EPROPSEG_MASK | FLEXCAN_CBT_EPSEG2_MASK |
FLEXCAN_CBT_EPSEG1_MASK | FLEXCAN_CBT_EPRESDIV_MASK) |
FLEXCAN_CBT_ERJW_MASK));
(base->CBT) = ((base->CBT) | (FLEXCAN_CBT_EPROPSEG(timeSeg->propSeg) |
FLEXCAN_CBT_EPSEG2(timeSeg->phaseSeg2) |
FLEXCAN_CBT_EPSEG1(timeSeg->phaseSeg1) |
FLEXCAN_CBT_EPRESDIV(timeSeg->preDivider) |
FLEXCAN_CBT_ERJW(timeSeg->rJumpwidth)));
}
/*!
* @brief Sets the FlexCAN Enhanced time segments for setting up nominal bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_SetEnhancedNominalTimeSegments(FLEXCAN_Type * base,
const Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
(base->ENCBT) = ((base->ENCBT) & ~(FLEXCAN_ENCBT_NTSEG1_MASK | FLEXCAN_ENCBT_NTSEG2_MASK | FLEXCAN_ENCBT_NRJW_MASK));
(base->ENCBT) = ((base->ENCBT) |(FLEXCAN_ENCBT_NTSEG1(timeSeg->phaseSeg1 + timeSeg->propSeg + 1U) |
FLEXCAN_ENCBT_NTSEG2(timeSeg->phaseSeg2) |
FLEXCAN_ENCBT_NRJW(timeSeg->rJumpwidth)));
(base->EPRS) = (base->EPRS & ~FLEXCAN_EPRS_ENPRESDIV_MASK);
(base->EPRS) |= FLEXCAN_EPRS_ENPRESDIV(timeSeg->preDivider);
}
/*!
* @brief Get the FlexCAN Enhanced time segments for nominal bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_GetEnhancedNominalTimeSegments(const FLEXCAN_Type * base,
Flexcan_Ip_TimeSegmentType * timeSeg)
{
timeSeg->propSeg = 0;
timeSeg->preDivider = ((base->EPRS & FLEXCAN_EPRS_ENPRESDIV_MASK) >> FLEXCAN_EPRS_ENPRESDIV_SHIFT);
timeSeg->phaseSeg1 = ((base->ENCBT & FLEXCAN_ENCBT_NTSEG1_MASK) >> FLEXCAN_ENCBT_NTSEG1_SHIFT);
timeSeg->phaseSeg2 = ((base->ENCBT & FLEXCAN_ENCBT_NTSEG2_MASK) >> FLEXCAN_ENCBT_NTSEG2_SHIFT);
timeSeg->rJumpwidth = ((base->ENCBT & FLEXCAN_ENCBT_NRJW_MASK) >> FLEXCAN_ENCBT_NRJW_SHIFT);
}
/*!
* @brief Sets the FlexCAN Enhanced time segments for setting up data bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments, which need to be set for the bit rate.
*/
static inline void FlexCAN_SetEnhancedDataTimeSegments(FLEXCAN_Type * base,
const Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
(base->EDCBT) = ((base->EDCBT) & ~(FLEXCAN_EDCBT_DTSEG1_MASK | FLEXCAN_EDCBT_DTSEG2_MASK | FLEXCAN_EDCBT_DRJW_MASK));
(base->EDCBT) = ((base->EDCBT) | (FLEXCAN_EDCBT_DTSEG1(timeSeg->phaseSeg1 + timeSeg->propSeg) |
FLEXCAN_EDCBT_DTSEG2(timeSeg->phaseSeg2) |
FLEXCAN_EDCBT_DRJW(timeSeg->rJumpwidth)));
(base->EPRS) = (base->EPRS & ~FLEXCAN_EPRS_EDPRESDIV_MASK);
(base->EPRS) |= FLEXCAN_EPRS_EDPRESDIV(timeSeg->preDivider);
}
static inline void FlexCAN_GetEnhancedDataTimeSegments(const FLEXCAN_Type * base,
Flexcan_Ip_TimeSegmentType * timeSeg)
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
DevAssert(timeSeg != NULL_PTR);
#endif
timeSeg->propSeg = 0U;
timeSeg->phaseSeg1 = ((base->EDCBT & FLEXCAN_EDCBT_DTSEG1_MASK) >> FLEXCAN_EDCBT_DTSEG1_SHIFT);
timeSeg->phaseSeg2 = ((base->EDCBT & FLEXCAN_EDCBT_DTSEG2_MASK) >> FLEXCAN_EDCBT_DTSEG2_SHIFT);
timeSeg->rJumpwidth = ((base->EDCBT & FLEXCAN_EDCBT_DRJW_MASK) >> FLEXCAN_EDCBT_DRJW_SHIFT);
timeSeg->preDivider = ((base->EPRS & FLEXCAN_EPRS_EDPRESDIV_MASK) >> FLEXCAN_EPRS_EDPRESDIV_SHIFT);
}
/*!
* @brief Gets the FlexCAN extended time segments used for setting up bit rate.
*
* @param[in] base The FlexCAN base address
* @param[out] timeSeg FlexCAN time segments read for bit rate
*/
static inline void FlexCAN_GetExtendedTimeSegments(const FLEXCAN_Type * base,
Flexcan_Ip_TimeSegmentType * timeSeg)
{
timeSeg->preDivider = ((base->CBT) & FLEXCAN_CBT_EPRESDIV_MASK) >> FLEXCAN_CBT_EPRESDIV_SHIFT;
timeSeg->propSeg = ((base->CBT) & FLEXCAN_CBT_EPROPSEG_MASK) >> FLEXCAN_CBT_EPROPSEG_SHIFT;
timeSeg->phaseSeg1 = ((base->CBT) & FLEXCAN_CBT_EPSEG1_MASK) >> FLEXCAN_CBT_EPSEG1_SHIFT;
timeSeg->phaseSeg2 = ((base->CBT) & FLEXCAN_CBT_EPSEG2_MASK) >> FLEXCAN_CBT_EPSEG2_SHIFT;
timeSeg->rJumpwidth = ((base->CBT) & FLEXCAN_CBT_ERJW_MASK) >> FLEXCAN_CBT_ERJW_SHIFT;
}
/*!
* @brief Gets the FlexCAN time segments to calculate the bit rate.
*
* @param[in] base The FlexCAN base address
* @param[out] timeSeg FlexCAN time segments read for bit rate
*/
static inline void FlexCAN_GetTimeSegments(const FLEXCAN_Type * base,
Flexcan_Ip_TimeSegmentType * timeSeg)
{
timeSeg->preDivider = ((base->CTRL1) & FLEXCAN_CTRL1_PRESDIV_MASK) >> FLEXCAN_CTRL1_PRESDIV_SHIFT;
timeSeg->propSeg = ((base->CTRL1) & FLEXCAN_CTRL1_PROPSEG_MASK) >> FLEXCAN_CTRL1_PROPSEG_SHIFT;
timeSeg->phaseSeg1 = ((base->CTRL1) & FLEXCAN_CTRL1_PSEG1_MASK) >> FLEXCAN_CTRL1_PSEG1_SHIFT;
timeSeg->phaseSeg2 = ((base->CTRL1) & FLEXCAN_CTRL1_PSEG2_MASK) >> FLEXCAN_CTRL1_PSEG2_SHIFT;
timeSeg->rJumpwidth = ((base->CTRL1) & FLEXCAN_CTRL1_RJW_MASK) >> FLEXCAN_CTRL1_RJW_SHIFT;
}
#if (FEATURE_CAN_HAS_FD == STD_ON)
/*!
* @brief Gets the FlexCAN time segments for FD BRS to calculate the bit rate.
*
* @param base The FlexCAN base address
* @param timeSeg FlexCAN time segments read for bit rate
*/
static inline void FlexCAN_GetFDTimeSegments(const FLEXCAN_Type * base,
Flexcan_Ip_TimeSegmentType * timeSeg)
{
timeSeg->preDivider = ((base->FDCBT) & FLEXCAN_FDCBT_FPRESDIV_MASK) >> FLEXCAN_FDCBT_FPRESDIV_SHIFT;
timeSeg->propSeg = ((base->FDCBT) & FLEXCAN_FDCBT_FPROPSEG_MASK) >> FLEXCAN_FDCBT_FPROPSEG_SHIFT;
timeSeg->phaseSeg1 = ((base->FDCBT) & FLEXCAN_FDCBT_FPSEG1_MASK) >> FLEXCAN_FDCBT_FPSEG1_SHIFT;
timeSeg->phaseSeg2 = ((base->FDCBT) & FLEXCAN_FDCBT_FPSEG2_MASK) >> FLEXCAN_FDCBT_FPSEG2_SHIFT;
timeSeg->rJumpwidth = ((base->FDCBT) & FLEXCAN_FDCBT_FRJW_MASK) >> FLEXCAN_FDCBT_FRJW_SHIFT;
}
#endif /* if FEATURE_CAN_HAS_FD */
/*!
* @brief Checks if the Extended Time Segment are enabled.
*
* @param base The FlexCAN base address
* @return TRUE if enabled; FALSE if disabled
*/
static inline boolean FlexCAN_IsExCbtEnabled(const FLEXCAN_Type * pBase)
{
return (((pBase->CBT & FLEXCAN_CBT_BTF_MASK) >> FLEXCAN_CBT_BTF_SHIFT) == 0U) ? FALSE : TRUE;
}
/*!
* @brief Checks if the Enhanced Time Segment are enabled.
*
* @param base The FlexCAN base address
* @return TRUE if enabled; FALSE if disabled
*/
static inline boolean FlexCAN_IsEnhCbtEnabled(const FLEXCAN_Type * pBase)
{
return (((pBase->CTRL2 & FLEXCAN_CTRL2_BTE_MASK) >> FLEXCAN_CTRL2_BTE_SHIFT) == 0U) ? FALSE : TRUE;
}
/*!
* @brief Set the Extended Time Segment are enabled or disabled.
*
* @param base The FlexCAN base address
* @param enableCBT Enable/Disable use of Extent Time Segments
*/
static inline void FlexCAN_EnableExtCbt(FLEXCAN_Type * base,
boolean enableCBT)
{ /* Enable the use of extended bit time definitions */
base->CBT = (base->CBT & ~FLEXCAN_CBT_BTF_MASK) | FLEXCAN_CBT_BTF(enableCBT ? 1UL : 0UL);
}
/*!
* @brief Set the Enhanced Time Segment are enabled or disabled.
*
* @param base The FlexCAN base address
* @param enableCBT Enable/Disable use of Enhanced Time Segments
*/
static inline void FlexCAN_EnhCbtEnable(FLEXCAN_Type * base,
boolean enableCBT)
{ /* Enable the use of extended bit time definitions */
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_BTE_MASK) | FLEXCAN_CTRL2_BTE(enableCBT ? 1UL : 0UL);
}
/*!
* @brief Set operation mode.
*
* @param base The FlexCAN base address
* @param mode Set an operation mode
*/
void FlexCAN_SetOperationMode(FLEXCAN_Type * base,
Flexcan_Ip_ModesType mode);
/*!
* @brief Enables/Disables the Self Reception feature.
*
* If enabled, FlexCAN is allowed to receive frames transmitted by itself.
*
* @param base The FlexCAN base address
* @param enable Enable/Disable Self Reception
*/
static inline void FlexCAN_SetSelfReception(FLEXCAN_Type * base,
boolean enable)
{
base->MCR = (base->MCR & ~FLEXCAN_MCR_SRXDIS_MASK) | FLEXCAN_MCR_SRXDIS(enable ? 0UL : 1UL);
}
/*!
* @brief Checks if the Flexible Data rate feature is enabled.
*
* @param base The FlexCAN base address
* @return TRUE if enabled; FALSE if disabled
*/
static inline boolean FlexCAN_IsFDEnabled(const FLEXCAN_Type * base)
{
return ((base->MCR & FLEXCAN_MCR_FDEN_MASK) >> FLEXCAN_MCR_FDEN_SHIFT) != 0U;
}
/*!
* @brief Checks if the listen only mode is enabled.
*
* @param base The FlexCAN base address
* @return TRUE if enabled; FALSE if disabled
*/
static inline boolean FlexCAN_IsListenOnlyModeEnabled(const FLEXCAN_Type * base)
{
return (((base->CTRL1 & (FLEXCAN_CTRL1_LOM_MASK)) != 0U) ? TRUE : FALSE);
}
/*!
* @brief Return last Message Buffer Occupied By RxFIFO
*
* @param x Number of Configured RxFIFO Filters
* @return number of last MB occupied by RxFIFO
*/
static inline uint32 RxFifoOcuppiedLastMsgBuff(uint32 x)
{
return 5U + ((((x) + 1U) * 8U) / 4U);
}
/*!
* @brief Computes the maximum payload size (in bytes), given a DLC
*
* @param dlcValue DLC code from the MB memory.
* @return payload size (in bytes)
*/
uint8 FlexCAN_ComputePayloadSize(uint8 dlcValue);
/*!
* @brief Sets the FlexCAN message buffer fields for transmitting.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @return Pointer to the beginning of the MBs space address
*/
volatile uint32 * FlexCAN_GetMsgBuffRegion(const FLEXCAN_Type * base,
uint32 msgBuffIdx);
/*!
* @brief Enables/Disables FD frame compatible with ISO-FD Frame ISO 11898-1 (2003)
*
* The CAN FD protocol has been improved to increase the failure detection capability that was in the original CAN FD protocol,
* which is also called non-ISO CAN FD, by CAN in Automation (CiA). A three-bit stuff counter and a parity bit have been introduced
* in the improved CAN FD protocol, now called ISO CAN FD. The CRC calculation has also been modified. All these improvements
* make the ISO CAN FD protocol incompatible with the non-FD CAN FD protocol.
*
* @param base The FlexCAN base address
* @param enable Enable/Disable ISO FD Compatible mode.
*/
#if (FEATURE_CAN_SWITCHINGISOMODE == STD_ON)
static inline void FlexCAN_SetIsoCan(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_ISOCANFDEN_MASK) | FLEXCAN_CTRL2_ISOCANFDEN(enable ? 1UL : 0UL);
}
#endif
static inline void FlexCAN_SetEntireFrameArbitrationFieldComparison(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_EACEN_MASK) | FLEXCAN_CTRL2_EACEN(enable ? 1UL : 0UL);
}
#if (FEATURE_CAN_PROTOCOLEXCEPTION == STD_ON)
static inline void FlexCAN_SetProtocolException(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_PREXCEN_MASK) | FLEXCAN_CTRL2_PREXCEN(enable ? 1UL : 0UL);
}
#endif
static inline void FlexCAN_SetBusOffAutorecovery(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL1 = (base->CTRL1 & ~FLEXCAN_CTRL1_BOFFREC_MASK) | FLEXCAN_CTRL1_BOFFREC(enable ? 0UL : 1UL);
}
#if (FEATURE_CAN_EDGEFILTER == STD_ON)
static inline void FlexCAN_SetEdgeFilter(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_EDFLTDIS_MASK) | FLEXCAN_CTRL2_EDFLTDIS(enable ? 0UL : 1UL);
}
#endif
static inline void FlexCAN_CanBitSampling(FLEXCAN_Type * base,
boolean enable)
{
base->CTRL1 = (base->CTRL1 & ~FLEXCAN_CTRL1_SMP_MASK) | FLEXCAN_CTRL1_SMP(enable ? 1UL : 0UL);
}
/*!
* @brief Gets the individual FlexCAN MB interrupt flag.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer
* @return the individual Message Buffer interrupt flag (0 and 1 are the flag value)
*/
static inline uint8 FlexCAN_GetMsgBuffIntStatusFlag(const FLEXCAN_Type * base,
uint32 msgBuffIdx)
{
/* TODO: This need to be protected multithread access*/
uint8 flag = 0;
uint32 mask;
if (msgBuffIdx < 32U)
{
mask = base->IMASK1 & FLEXCAN_IMASK1_BUF31TO0M_MASK;
flag = (uint8)(((base->IFLAG1 & mask) >> (msgBuffIdx % 32U)) & 1U);
}
#if FEATURE_CAN_MAX_MB_NUM > 32U
else if (msgBuffIdx < 64U)
{
mask = base->IMASK2 & FLEXCAN_IMASK2_BUF63TO32M_MASK;
flag = (uint8)(((base->IFLAG2 & mask) >> (msgBuffIdx % 32U)) & 1U);
}
#if FEATURE_CAN_MAX_MB_NUM <= 64U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif
#endif /* if FEATURE_CAN_MAX_MB_NUM > 32U */
#if FEATURE_CAN_MAX_MB_NUM > 64U
else if (msgBuffIdx < 96U)
{
mask = base->IMASK3 & FLEXCAN_IMASK3_BUF95TO64M_MASK;
flag = (uint8)(((base->IFLAG3 & mask) >> (msgBuffIdx % 32U)) & 1U);
}
#if FEATURE_CAN_MAX_MB_NUM <= 96U
else
{
/* Required Rule 15.7, no 'else' at end of 'if ... else if' chain */
}
#endif
#endif /* if FEATURE_CAN_MAX_MB_NUM > 64U */
#if FEATURE_CAN_MAX_MB_NUM > 96U
else
{
mask = base->IMASK4 & FLEXCAN_IMASK4_BUF127TO96M_MASK;
flag = (uint8)(((base->IFLAG4 & mask) >> (msgBuffIdx % 32U)) & 1U);
}
#endif
return flag;
}
/*!
* @brief Return Rx FIFO Id Format.
*
* @param base The FlexCAN base address
* @return RxFifo Id Format
*/
static inline Flexcan_Ip_RxFifoIdElementFormatType FlexCAN_GetRxFifoIdFormat(const FLEXCAN_Type * base)
{
Flexcan_Ip_RxFifoIdElementFormatType id_type = FLEXCAN_RX_FIFO_ID_FORMAT_A;
switch ((base->MCR & FLEXCAN_MCR_IDAM_MASK) >> FLEXCAN_MCR_IDAM_SHIFT)
{
case 0U:
id_type = FLEXCAN_RX_FIFO_ID_FORMAT_A;
break;
case 1U:
id_type = FLEXCAN_RX_FIFO_ID_FORMAT_B;
break;
case 2U:
id_type = FLEXCAN_RX_FIFO_ID_FORMAT_C;
break;
case 3U:
id_type = FLEXCAN_RX_FIFO_ID_FORMAT_D;
break;
default:
{
#if (FLEXCAN_DEV_ERROR_DETECT == STD_ON)
/* This case should never be reached */
DevAssert(FALSE);
#endif
break;
}
}
return id_type;
}
/*!
* @brief Get the no of Rx FIFO ID Filter Table Elements Affected by Rx Individual Masks
*
* @param base The FlexCAN base address
* @return the max no of elements affected by Rx Individual Mask register RXMIR in RxFIFO Mode
*/
static inline uint8 FlexCAN_GetNoOfIndividualMBsRxFIFO(const FLEXCAN_Type * base)
{
/* Get the number of RX FIFO Filters*/
uint8 ret = (uint8)(((base->CTRL2) & FLEXCAN_CTRL2_RFFN_MASK) >> FLEXCAN_CTRL2_RFFN_SHIFT);
/* Max filters configured by individual mask are (7 + RFFN * 2) depends on the FIFO size,
* max allowed value is 31 RXIMR */
ret = (uint8)(7u + ((uint32)ret << 1u));
return ret;
}
/*!
* @brief Sets the FlexCAN Rx Message Buffer global mask.
*
* @param base The FlexCAN base address
* @param Mask Mask Value
*/
static inline void FlexCAN_SetRxMsgBuffGlobalMask(FLEXCAN_Type * base,
uint32 Mask)
{
(base->RXMGMASK) = Mask;
}
/*!
* @brief Sets the FlexCAN Rx individual mask for ID filtering in the Rx Message Buffers and the Rx FIFO.
*
* @param base The FlexCAN base address
* @param msgBuffIdx Index of the message buffer/filter
* @param mask Individual mask
*/
static inline void FlexCAN_SetRxIndividualMask(FLEXCAN_Type * base,
uint32 msgBuffIdx,
uint32 mask)
{
base->RXIMR[msgBuffIdx] = mask;
}
/*!
* @brief Check if controller is in freeze mode or not.
*
* @param base The FlexCAN base address
* @return TRUE if controller is in freeze mode
* FALSE if controller is not in freeze mode
*/
static inline boolean FlexCAN_IsFreezeMode(const FLEXCAN_Type * base)
{
return (((base->MCR & (FLEXCAN_MCR_FRZACK_MASK)) != 0U )? TRUE : FALSE);
}
static inline void FlexCAN_SetTxArbitrationStartDelay(FLEXCAN_Type * base, uint8 tasd)
{
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_TASD_MASK) | FLEXCAN_CTRL2_TASD(tasd);
}
/*!
* @brief Sets the Rx masking type.
*
* @param base The FlexCAN base address
* @param type The FlexCAN Rx mask type
*/
static inline void FlexCAN_SetRxMaskType(FLEXCAN_Type * base,
Flexcan_Ip_RxMaskType type)
{
/* Set RX masking type (RX global mask or RX individual mask)*/
if (type == FLEXCAN_RX_MASK_GLOBAL)
{
/* Enable Global RX masking */
base->MCR = (base->MCR & ~FLEXCAN_MCR_IRMQ_MASK) | FLEXCAN_MCR_IRMQ(0U);
}
else
{
/* Enable Individual Rx Masking and Queue */
base->MCR = (base->MCR & ~FLEXCAN_MCR_IRMQ_MASK) | FLEXCAN_MCR_IRMQ(1U);
}
}
#if (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON)
/*!
* @brief Checks if Enhanced Rx FIFO is enabled.
*
* @param base The FlexCAN base address
* @return EnhancedRxFifo status (true = enabled / false = disabled)
*/
static inline boolean FlexCAN_IsEnhancedRxFifoEnabled(const FLEXCAN_Type * base)
{
return ((((base->ERFCR & FLEXCAN_ERFCR_ERFEN_MASK) >> FLEXCAN_ERFCR_ERFEN_SHIFT) != 0U) ? ((boolean)TRUE): ((boolean)FALSE) );
}
/*FUNCTION**********************************************************************
*
* Function Name : FLEXCAN_SetEnhancedRxFifoIntAll
* Description : Enable/Disable All(Underflow, Overflow, Watermark and frame available)
* interrupts for Enhanced Rx FIFO.
*
*END**************************************************************************/
static inline void FlexCAN_SetEnhancedRxFifoIntAll(FLEXCAN_Type * base,
boolean enable)
{
if (enable == TRUE)
{
(base->ERFIER) = ((base->ERFIER) | (uint32)(FLEXCAN_ENHACED_RX_FIFO_ALL_INTERRUPT_MASK));
}
else
{
(base->ERFIER) = ((base->ERFIER) & (uint32)~(FLEXCAN_ENHACED_RX_FIFO_ALL_INTERRUPT_MASK));
}
}
/*!
* @brief Gets the individual FlexCAN Enhanced Rx FIFO flag.
*
* @param base The FlexCAN base address
* @param intFlag Index of the Enhanced Rx FIFO flag
* @return the individual Enhanced Rx FIFO flag (0 and 1 are the flag value)
*/
static inline uint8 FlexCAN_GetEnhancedRxFIFOStatusFlag(const FLEXCAN_Type * base,
uint32 intFlag)
{
return (uint8)((base->ERFSR & ((uint32)1U << ((uint8)intFlag & (uint8)0x1F))) >> ((uint8)intFlag & (uint8)0x1F));
}
/*!
* @brief Clears the interrupt flag of the Enhanced Rx FIFO.
*
* @param base The FlexCAN base address
* @param intFlag Index of the Enhanced Rx FIFO interrupt flag
*/
static inline void FlexCAN_ClearEnhancedRxFifoIntStatusFlag(FLEXCAN_Type * base,
uint32 intFlag)
{
(base->ERFSR) = (uint32)1U << intFlag;
}
/*!
* @brief Gets the individual FlexCAN Enhanced Rx FIFO interrupt flag.
*
* @param base The FlexCAN base address
* @param intFlag Index of the Enhanced Rx FIFO interrupt flag
* @return the individual Enhanced Rx FIFO interrupt flag (0 and 1 are the flag value)
*/
static inline uint8 FlexCAN_GetEnhancedRxFIFOIntStatusFlag(const FLEXCAN_Type * base,
uint32 intFlag)
{
return (uint8)((base->ERFIER & ((uint32)1U << ((uint8)intFlag & (uint8)0x1F))) >> ((uint8)intFlag & (uint8)0x1F));
}
/*!
* @brief Checks if FlexCAN has Enhanced Rx FIFO.
*
* @param base The FlexCAN base address
* @return EnhancedRxFifo status (TRUE = available / FALSE = unavailable)
*/
boolean FlexCAN_IsEnhancedRxFifoAvailable(const FLEXCAN_Type * base);
Flexcan_Ip_StatusType FlexCAN_EnableEnhancedRxFifo(FLEXCAN_Type * base,
uint32 numOfStdIDFilters,
uint32 numOfExtIDFilters,
uint32 numOfWatermark);
void FlexCAN_SetEnhancedRxFifoFilter(FLEXCAN_Type * base, const Flexcan_Ip_EnhancedIdTableType * idFilterTable);
#if (FEATURE_CAN_HAS_DMA_ENABLE == STD_ON)
/*!
* @brief Clear Enhance fifo data.
*
* @param base The FlexCAN base address
* @return void
*/
void FlexCAN_ClearOutputEnhanceFIFO(FLEXCAN_Type * base);
#endif /* (FEATURE_CAN_HAS_DMA_ENABLE == STD_ON) */
void FlexCAN_ReadEnhancedRxFifo(const FLEXCAN_Type * base, Flexcan_Ip_MsgBuffType * rxFifo);
#endif /* (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON) */
#if (FEATURE_CAN_HAS_DMA_ENABLE == STD_ON)
/*!
* @brief Clear Legacy fifo data.
*
* @param base The FlexCAN base address
* @return void
*/
void FlexCAN_ClearOutputLegacyFIFO(FLEXCAN_Type * base);
#endif /* FEATURE_CAN_HAS_DMA_ENABLE */
#if (FEATURE_CAN_HAS_HR_TIMER == STD_ON)
/*!
* @brief Checks if High Resolution Time Stamp is enabled.
*
* @param base The FlexCAN base address
* @return HRTimeStamp status (true = enabled / false = disabled)
*/
static inline boolean FLEXCAN_IsHRTimeStampEnabled(const FLEXCAN_Type * base)
{
return (((base->CTRL2 & FLEXCAN_CTRL2_TSTAMPCAP_MASK) >> FLEXCAN_CTRL2_TSTAMPCAP_SHIFT) != 0U ? TRUE : FALSE);
}
void FlexCAN_ConfigTimestamp(FLEXCAN_Type * base, Flexcan_Ip_TimeStampConfigType * config);
static inline void FlexCAN_ConfigTimestampModule(Flexcan_Ip_TimeStampConfigType * config)
{
TIMESTAMP_REG = CAN_TIMESTAMP_SEL(config->hrSrc)|CAN_TIMESTAMP_EN_MASK;
}
#endif /*(FEATURE_CAN_HAS_HR_TIMER == STD_ON) */
/*!
* @brief configure controller depending on options.
*
* @param pBase The FlexCAN base address.
* @param u32Options Controller Options.
*/
void FlexCAN_ConfigCtrlOptions(FLEXCAN_Type * pBase, uint32 u32Options);
/*!
* @brief Will set Flexcan Peripheral Register to default val.
*
* @param base The FlexCAN base address
*/
static inline void FlexCAN_SetRegDefaultVal(FLEXCAN_Type * base)
{
#if (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON)
if ((boolean)TRUE == FlexCAN_IsEnhancedRxFifoAvailable(base))
{
base->ERFSR = FLEXCAN_ERFSR_DEFAULT_VALUE_U32;
base->ERFIER = FLEXCAN_ERFIER_DEFAULT_VALUE_U32;
base->ERFCR = FLEXCAN_ERFCR_DEFAULT_VALUE_U32;
}
#endif /* (FEATURE_CAN_HAS_ENHANCED_RX_FIFO == STD_ON) */
#if (FEATURE_CAN_HAS_FD == STD_ON)
base->FDCBT = FLEXCAN_FDCBT_DEFAULT_VALUE_U32;
base->FDCTRL = FLEXCAN_FDCTRL_DEFAULT_VALUE_U32;
#endif /* (FEATURE_CAN_HAS_FD == STD_ON) */
#if (FEATURE_CAN_HAS_MEM_ERR_DET == STD_ON)
base->ERRSR = FLEXCAN_ERRSR_DEFAULT_VALUE_U32;
base->ERRIPPR = FLEXCAN_ERRIPPR_DEFAULT_VALUE_U32;
base->ERRIDPR = FLEXCAN_ERRIDPR_DEFAULT_VALUE_U32;
base->ERRIAR = FLEXCAN_ERRIAR_DEFAULT_VALUE_U32;
/* Enable write of MECR register */
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_ECRWRE_MASK) | FLEXCAN_CTRL2_ECRWRE(1);
/* Enable write of MECR */
base->MECR = (base->MECR & ~FLEXCAN_MECR_ECRWRDIS_MASK) | FLEXCAN_MECR_ECRWRDIS(0);
/* set Default value */
base->MECR = FLEXCAN_MECR_DEFAULT_VALUE_U32;
/* disable write of MECR */
base->MECR = (base->MECR & ~FLEXCAN_MECR_ECRWRDIS_MASK) | FLEXCAN_MECR_ECRWRDIS(1);
/* Disable write of MECR */
base->CTRL2 = (base->CTRL2 & ~FLEXCAN_CTRL2_ECRWRE_MASK) | FLEXCAN_CTRL2_ECRWRE(0);
#endif /* (FEATURE_CAN_HAS_MEM_ERR_DET == STD_ON) */
#if (FEATURE_CAN_MAX_MB_NUM > 96U)
if (FlexCAN_GetMaxMbNum(base) > 96U)
{
base->IFLAG4 = FLEXCAN_IFLAG_DEFAULT_VALUE_U32;
base->IMASK4 = FLEXCAN_IMASK_DEFAULT_VALUE_U32;
}
#endif /* (FEATURE_CAN_MAX_MB_NUM > 96U) */
#if (FEATURE_CAN_MAX_MB_NUM > 64U)
if (FlexCAN_GetMaxMbNum(base) > 64U)
{
base->IFLAG3 = FLEXCAN_IFLAG_DEFAULT_VALUE_U32;
base->IMASK3 = FLEXCAN_IMASK_DEFAULT_VALUE_U32;
}
#endif /* (FEATURE_CAN_MAX_MB_NUM > 64U) */
#if (FEATURE_CAN_MAX_MB_NUM > 32U)
if (FlexCAN_GetMaxMbNum(base) > 32U)
{
base->IFLAG2 = FLEXCAN_IFLAG_DEFAULT_VALUE_U32;
base->IMASK2 = FLEXCAN_IMASK_DEFAULT_VALUE_U32;
}
#endif /* (FEATURE_CAN_MAX_MB_NUM > 32U) */
base->IFLAG1 = FLEXCAN_IFLAG_DEFAULT_VALUE_U32;
base->IMASK1 = FLEXCAN_IMASK_DEFAULT_VALUE_U32;
base->CBT = FLEXCAN_CBT_DEFAULT_VALUE_U32;
base->CTRL2 = FLEXCAN_CTRL2_DEFAULT_VALUE_U32;
base->ESR1 = FLEXCAN_ESR1_DEFAULT_VALUE_U32;
base->ECR = FLEXCAN_ECR_DEFAULT_VALUE_U32;
base->TIMER = FLEXCAN_TIMER_DEFAULT_VALUE_U32;
base->CTRL1 = FLEXCAN_CTRL1_DEFAULT_VALUE_U32;
base->EPRS = FLEXCAN_EPRS_DEFAULT_VALUE_U32;
base->ENCBT = FLEXCAN_ENCBT_DEFAULT_VALUE_U32;
base->EDCBT = FLEXCAN_EDCBT_DEFAULT_VALUE_U32;
base->ETDC = FLEXCAN_ETDC_DEFAULT_VALUE_U32;
base->MCR = FLEXCAN_MCR_DEFAULT_VALUE_U32;
}
#define CAN_STOP_SEC_CODE
#include "Can_MemMap.h"
#endif /* FLEXCAN_FLEXCAN_IP_HWACCESS_H_ */
/** @} */
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