mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 01:43:59 +09:00
7493 lines
238 KiB
Plaintext
7493 lines
238 KiB
Plaintext
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Marking local functions:
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Marking externally visible functions: setupCanTJA1153 debug_printf UART0_get_cmd get_line put_char get_char register_bus_off_callback Gvar_init UART9_RX_Callback UART1_RX_Callback UART13_RX_Callback UART10_RX_Callback UART2_RX_Callback UART0_RX_Callback Uart_Init board_init Pit_Callback tmr_delay Adc_Read_ch Adc2EndOfChainNoti Adc1EndOfChainNoti Adc0EndOfChainNoti ADC_Read Adc_Init led_onoff Digital_Read Digital_Write DIN_TEST can_transmit_txring can_send_txring can_tx_check clear_tx_ring clear_tx_buf ECU3_Data_Init Can_Init_ECU3 can_main_ECU3 get_can_data CAN5_ErrCallback CAN5_Callback CAN4_ErrCallback CAN4_Callback CAN3_ErrCallback CAN3_Callback CAN2_ErrCallback CAN2_Callback CAN1_ErrCallback CAN1_Callback CAN0_ErrCallback CAN0_Callback i2c_delay sda_out sda_in i2c_test i2c1_init i2c0_init Lin_tx_test Lin2callback Lin1callback Lin_init SPI_test SPI_init Set_PWM_Duty pwm_init
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Marking externally visible variables: trans_ret init_ret passed FlexCAN_Config_500k rx_info tx_info can5_rxData can4_rxData can3_rxData can2_rxData can1_rxData can0_rxData isSend txBuff txBuff_lin timeOut numberOfBytes rxBuffer_spi txBuffer_spi txBuffer rxBufferSlave hscan_test_buf canfd_test_buf vcan_send_miss_message din_test adc_test1
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Reclaiming functions:
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Reclaiming variables:
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Clearing address taken flags:
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Symbol table:
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FlexCAN_Ip_SendBlocking/285 (FlexCAN_Ip_SendBlocking) @09b757e0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: setupCanTJA1153/132 setupCanTJA1153/132 setupCanTJA1153/132 setupCanTJA1153/132 setupCanTJA1153/132
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Calls:
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strlen/284 (strlen) @09b75e00
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: debug_printf/131
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Calls:
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__builtin_va_end/283 (__builtin_va_end) @09b75d20
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: debug_printf/131
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Calls:
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vsprintf/282 (vsprintf) @09b75c40
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: debug_printf/131
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Calls:
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__builtin_va_start/281 (__builtin_va_start) @09b75b60
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: debug_printf/131
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Calls:
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strcmp/280 (strcmp) @09b759a0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: UART0_get_cmd/130
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Calls:
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Lpuart_Uart_Ip_SyncSend/279 (Lpuart_Uart_Ip_SyncSend) @09b75620
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: put_char/128
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Calls:
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Lpuart_Uart_Ip_SetRxBuffer/278 (Lpuart_Uart_Ip_SetRxBuffer) @09b6f700
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: UART9_RX_Callback/124 UART1_RX_Callback/123 UART13_RX_Callback/122 UART10_RX_Callback/121 UART2_RX_Callback/120 UART0_RX_Callback/119
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Calls:
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Lpuart_Uart_Ip_AsyncReceive/277 (Lpuart_Uart_Ip_AsyncReceive) @09b6f540
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Uart_Init/118 Uart_Init/118 Uart_Init/118 Uart_Init/118
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Calls:
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Lpuart_Uart_Ip_pHwConfigPB_13_BOARD_INITPERIPHERALS/276 (Lpuart_Uart_Ip_pHwConfigPB_13_BOARD_INITPERIPHERALS) @09b6c5a0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Varpool flags: read-only
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Lpuart_Uart_Ip_pHwConfigPB_10_BOARD_INITPERIPHERALS/275 (Lpuart_Uart_Ip_pHwConfigPB_10_BOARD_INITPERIPHERALS) @09b6c510
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Varpool flags: read-only
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Lpuart_Uart_Ip_pHwConfigPB_2_BOARD_INITPERIPHERALS/274 (Lpuart_Uart_Ip_pHwConfigPB_2_BOARD_INITPERIPHERALS) @09b6c480
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Varpool flags: read-only
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Lpuart_Uart_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS/273 (Lpuart_Uart_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS) @09b6c3f0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Varpool flags: read-only
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Lpuart_Uart_Ip_Init/272 (Lpuart_Uart_Ip_Init) @09b6f380
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Uart_Init/118 Uart_Init/118 Uart_Init/118 Uart_Init/118
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Calls:
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LPUART_UART_IP_13_IRQHandler/271 (LPUART_UART_IP_13_IRQHandler) @09b6f2a0
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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LPUART_UART_IP_10_IRQHandler/270 (LPUART_UART_IP_10_IRQHandler) @09b6f1c0
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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LPUART_UART_IP_2_IRQHandler/269 (LPUART_UART_IP_2_IRQHandler) @09b6f0e0
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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LPUART_UART_IP_0_IRQHandler/268 (LPUART_UART_IP_0_IRQHandler) @09b6f000
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Uart_Init/118 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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task_500us/267 (task_500us) @09b66d20
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Pit_Callback/116
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Calls:
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uds_timer_interrupt/266 (uds_timer_interrupt) @09b66b60
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Pit_Callback/116
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Calls:
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t.15143/265 (t) @09b67e58
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Type: variable definition analyzed
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Visibility: prevailing_def_ironly
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References:
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Referring: Pit_Callback/116 (read)Pit_Callback/116 (write)Pit_Callback/116 (write)
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Availability: available
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Varpool flags: initialized
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Adc_Sar_Ip_StartConversion/264 (Adc_Sar_Ip_StartConversion) @09b668c0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Adc_Read_ch/114
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Calls:
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Adc_Sar_Ip_GetConvData/263 (Adc_Sar_Ip_GetConvData) @09b66540
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Adc2EndOfChainNoti/113 Adc2EndOfChainNoti/113 Adc2EndOfChainNoti/113 Adc1EndOfChainNoti/112 Adc1EndOfChainNoti/112 Adc0EndOfChainNoti/111
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Calls:
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Adc_Sar_Ip_EnableNotifications/262 (Adc_Sar_Ip_EnableNotifications) @09b661c0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Adc_Init/109 Adc_Init/109 Adc_Init/109
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Calls:
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Adc_Sar_Ip_DoCalibration/261 (Adc_Sar_Ip_DoCalibration) @09b660e0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Adc_Init/109 Adc_Init/109 Adc_Init/109
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Calls:
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Adc_Sar_2_Isr/260 (Adc_Sar_2_Isr) @09b4c700
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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Adc_Sar_1_Isr/259 (Adc_Sar_1_Isr) @09b4c620
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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Adc_Sar_0_Isr/258 (Adc_Sar_0_Isr) @09b4c540
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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AdcHwUnit_2_BOARD_INITPERIPHERALS/257 (AdcHwUnit_2_BOARD_INITPERIPHERALS) @09b62bd0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Varpool flags: read-only
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AdcHwUnit_1_BOARD_INITPERIPHERALS/256 (AdcHwUnit_1_BOARD_INITPERIPHERALS) @09b62af8
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Varpool flags: read-only
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AdcHwUnit_0_BOARD_INITPERIPHERALS/255 (AdcHwUnit_0_BOARD_INITPERIPHERALS) @09b62a20
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Adc_Init/109 (addr)
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Availability: not_available
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Varpool flags: read-only
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Adc_Sar_Ip_Init/254 (Adc_Sar_Ip_Init) @09b4c000
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Adc_Init/109 Adc_Init/109 Adc_Init/109
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Calls:
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Siul2_Dio_Ip_ReadPin/253 (Siul2_Dio_Ip_ReadPin) @09b4c9a0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: Digital_Read/107 Digital_Read/107 Digital_Read/107 Digital_Read/107 Digital_Read/107 Digital_Read/107 Digital_Read/107 Digital_Read/107 DIN_TEST/105
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Calls:
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FlexCAN_Ip_Send/252 (FlexCAN_Ip_Send) @09b4c7e0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: can_transmit_txring/104
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Calls:
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ECU3/251 (ECU3) @09b3aa20
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 (write)ECU3_Data_Init/99 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Availability: not_available
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Varpool flags:
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g_messageObjectConf_ECU3_5ch_RX/250 (g_messageObjectConf_ECU3_5ch_RX) @09b3a870
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Can_Init_ECU3/98 (read)
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Availability: not_available
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Varpool flags: read-only
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FlexCAN_Config5/249 (FlexCAN_Config5) @09b3a7e0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Can_Init_ECU3/98 (addr)
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Availability: not_available
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Varpool flags: read-only
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FlexCAN_State5/248 (FlexCAN_State5) @09b3a6c0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)
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Availability: not_available
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Varpool flags:
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CAN5_ORED_0_31_MB_IRQHandler/247 (CAN5_ORED_0_31_MB_IRQHandler) @09b38ee0
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Can_Init_ECU3/98 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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CAN5_ORED_IRQHandler/246 (CAN5_ORED_IRQHandler) @09b38e00
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Type: function
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Visibility: external public
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Address is taken.
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References:
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Referring: Can_Init_ECU3/98 (addr)
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Availability: not_available
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Function flags: optimize_size
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Called by:
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Calls:
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g_messageObjectConf_ECU3_4ch_RX/245 (g_messageObjectConf_ECU3_4ch_RX) @09b3a3f0
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Can_Init_ECU3/98 (read)
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Availability: not_available
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Varpool flags: read-only
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FlexCAN_Config4/244 (FlexCAN_Config4) @09b3a360
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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Visibility: external public
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References:
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Referring: Can_Init_ECU3/98 (addr)
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Availability: not_available
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Varpool flags: read-only
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FlexCAN_State4/243 (FlexCAN_State4) @09b3a240
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Type: variable
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Body removed by symtab_remove_unreachable_nodes
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|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
CAN4_ORED_0_31_MB_IRQHandler/242 (CAN4_ORED_0_31_MB_IRQHandler) @09b38d20
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
CAN4_ORED_IRQHandler/241 (CAN4_ORED_IRQHandler) @09b38c40
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
g_messageObjectConf_ECU3_3ch_RX/240 (g_messageObjectConf_ECU3_3ch_RX) @09b36f30
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (read)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_Config3/239 (FlexCAN_Config3) @09b36ea0
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_State3/238 (FlexCAN_State3) @09b36e58
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
CAN3_ORED_0_31_MB_IRQHandler/237 (CAN3_ORED_0_31_MB_IRQHandler) @09b38b60
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
CAN3_ORED_IRQHandler/236 (CAN3_ORED_IRQHandler) @09b38a80
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
g_messageObjectConf_ECU3_2ch_RX/235 (g_messageObjectConf_ECU3_2ch_RX) @09b36b88
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (read)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_Config2/234 (FlexCAN_Config2) @09b36af8
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_State2/233 (FlexCAN_State2) @09b36ab0
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
CAN2_ORED_0_31_MB_IRQHandler/232 (CAN2_ORED_0_31_MB_IRQHandler) @09b389a0
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
CAN2_ORED_IRQHandler/231 (CAN2_ORED_IRQHandler) @09b388c0
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
g_messageObjectConf_ECU3_1ch_RX/230 (g_messageObjectConf_ECU3_1ch_RX) @09b367e0
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (read)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_Config1/229 (FlexCAN_Config1) @09b36750
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_State1/228 (FlexCAN_State1) @09b36708
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
CAN1_ORED_0_31_MB_IRQHandler/227 (CAN1_ORED_0_31_MB_IRQHandler) @09b387e0
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
CAN1_ORED_IRQHandler/226 (CAN1_ORED_IRQHandler) @09b38700
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
FlexCAN_Ip_ConfigRxMb/225 (FlexCAN_Ip_ConfigRxMb) @09b38540
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98
|
|
Calls:
|
|
FlexCAN_Ip_SetStartMode_Privileged/224 (FlexCAN_Ip_SetStartMode_Privileged) @09b38460
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98
|
|
Calls:
|
|
FlexCAN_Ip_SetRxIndividualMask_Privileged/223 (FlexCAN_Ip_SetRxIndividualMask_Privileged) @09b38380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98
|
|
Calls:
|
|
FlexCAN_Ip_SetRxMaskType_Privileged/222 (FlexCAN_Ip_SetRxMaskType_Privileged) @09b382a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98
|
|
Calls:
|
|
FlexCAN_Config0/221 (FlexCAN_Config0) @09b362d0
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
FlexCAN_State0/220 (FlexCAN_State0) @09b36288
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
FlexCAN_Ip_Init_Privileged/219 (FlexCAN_Ip_Init_Privileged) @09b381c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98
|
|
Calls:
|
|
Siul2_Dio_Ip_WritePin/218 (Siul2_Dio_Ip_WritePin) @09b380e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: setupCanTJA1153/132 setupCanTJA1153/132 led_onoff/108 led_onoff/108 Digital_Write/106 Digital_Write/106 Digital_Write/106 Digital_Write/106 Digital_Write/106 Digital_Write/106 Digital_Write/106 Digital_Write/106 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98
|
|
Calls:
|
|
CAN0_ORED_0_31_MB_IRQHandler/217 (CAN0_ORED_0_31_MB_IRQHandler) @09b38000
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
CAN0_ORED_IRQHandler/216 (CAN0_ORED_IRQHandler) @09b2dd20
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
Receive_RWS_VCU_stat_Signal_CH5_0x072/215 (Receive_RWS_VCU_stat_Signal_CH5_0x072) @09b2dc40
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWS_VCU_Rack_AngleFbk_CH5_0x073/214 (Receive_RWS_VCU_Rack_AngleFbk_CH5_0x073) @09b2db60
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWS_VCU_stat_Signal_CH4_0x072/213 (Receive_RWS_VCU_stat_Signal_CH4_0x072) @09b2da80
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWS_VCU_Rack_AngleFbk_CH4_0x073/212 (Receive_RWS_VCU_Rack_AngleFbk_CH4_0x073) @09b2d9a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_UdsResponse_CH3_0x799/211 (Receive_RCU_UdsResponse_CH3_0x799) @09b2d8c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_Status_CH3_0x093/210 (Receive_RCU_Status_CH3_0x093) @09b2d7e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_WheelStatus_CH3_0x08D/209 (Receive_RCU_WheelStatus_CH3_0x08D) @09b2d700
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_TireSlipStatus_CH3_0x097/208 (Receive_RCU_TireSlipStatus_CH3_0x097) @09b2d620
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status3_CH3_0x0AA/207 (Receive_RWA_Status3_CH3_0x0AA) @09b2d540
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status2_CH3_0x073/206 (Receive_RWA_Status2_CH3_0x073) @09b2d460
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status1_CH3_0x072/205 (Receive_RWA_Status1_CH3_0x072) @09b2d380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_PressureStatus_CH3_0x0A1/204 (Receive_RCU_PressureStatus_CH3_0x0A1) @09b2d2a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_BrakeStatus2_CH3_0x0C9/203 (Receive_RCU_BrakeStatus2_CH3_0x0C9) @09b2d1c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RCU_BrakeStatus1_CH3_0x09B/202 (Receive_RCU_BrakeStatus1_CH3_0x09B) @09b2d0e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status3_CH2_0x0AA/201 (Receive_RWA_Status3_CH2_0x0AA) @09b2d000
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status2_CH2_0x073/200 (Receive_RWA_Status2_CH2_0x073) @09b2cee0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RWA_Status1_CH2_0x072/199 (Receive_RWA_Status1_CH2_0x072) @09b2ce00
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_WheelStatus_CH2_0x08C/198 (Receive_IDB_WheelStatus_CH2_0x08C) @09b2cd20
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_UdsResponse_CH2_0x798/197 (Receive_IDB_UdsResponse_CH2_0x798) @09b2cc40
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_TireSlipStatus_CH2_0x096/196 (Receive_IDB_TireSlipStatus_CH2_0x096) @09b2cb60
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_Status_CH2_0x092/195 (Receive_IDB_Status_CH2_0x092) @09b2ca80
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_RegenTcsRequest_CH2_0x082/194 (Receive_IDB_RegenTcsRequest_CH2_0x082) @09b2c9a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_PressureStatus_CH2_0x0A0/193 (Receive_IDB_PressureStatus_CH2_0x0A0) @09b2c8c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_BrakeStatus2_CH2_0x0C8/192 (Receive_IDB_BrakeStatus2_CH2_0x0C8) @09b2c7e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IDB_BrakeStatus1_CH2_0x09A/191 (Receive_IDB_BrakeStatus1_CH2_0x09A) @09b2c700
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_ACU_BCM_Signal_1_CH1_0x150/190 (Receive_ACU_BCM_Signal_1_CH1_0x150) @09b2c620
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
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Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_ACU_VCU_Signal3_CH1_0x093/189 (Receive_ACU_VCU_Signal3_CH1_0x093) @09b2c540
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
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Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_ACU_VCU_Signal2_CH1_0x092/188 (Receive_ACU_VCU_Signal2_CH1_0x092) @09b2c460
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
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Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_ACU_VCU_Signal1_CH1_0x091/187 (Receive_ACU_VCU_Signal1_CH1_0x091) @09b2c380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_EPAM_VCU_CH0_0x221/186 (Receive_EPAM_VCU_CH0_0x221) @09b2c2a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RC_VCU_BCM_Signal_1_CH0_0x155/185 (Receive_RC_VCU_BCM_Signal_1_CH0_0x155) @09b2c1c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IMU_TX1_CH0_0x17C/184 (Receive_IMU_TX1_CH0_0x17C) @09b2c0e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IMU_TX1_CH0_0x178/183 (Receive_IMU_TX1_CH0_0x178) @09b2c000
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IMU_TX1_CH0_0x174/182 (Receive_IMU_TX1_CH0_0x174) @09b179a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RC_VCU_Signal2_CH0_0x041/181 (Receive_RC_VCU_Signal2_CH0_0x041) @09b178c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_RC_VCU_Signal1_CH0_0x040/180 (Receive_RC_VCU_Signal1_CH0_0x040) @09b177e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
GV_CH0_0x301_CNT/179 (GV_CH0_0x301_CNT) @09b278b8
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: can_main_ECU3/97 (read)can_main_ECU3/97 (write)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
Receive_MCU_VCU_Signals2_CH0_0x301/178 (Receive_MCU_VCU_Signals2_CH0_0x301) @09b17380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_MCU_VCU_Signals1_CH0_0x300/177 (Receive_MCU_VCU_Signals1_CH0_0x300) @09b17000
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_IMU_VCU_Signal_CH0_0x020/176 (Receive_IMU_VCU_Signal_CH0_0x020) @09b17ee0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_BCM_VCU_Signal5_CH0_0x585/175 (Receive_BCM_VCU_Signal5_CH0_0x585) @09b17e00
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_BCM_VCU_Signal4_CH0_0x595/174 (Receive_BCM_VCU_Signal4_CH0_0x595) @09b17d20
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_BCM_VCU_Signal3_CH0_0x590/173 (Receive_BCM_VCU_Signal3_CH0_0x590) @09b17c40
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_BCM_VCU_Signal2_CH0_0x580/172 (Receive_BCM_VCU_Signal2_CH0_0x580) @09b17b60
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
Receive_BCM_VCU_Signal1_CH0_0x570/171 (Receive_BCM_VCU_Signal1_CH0_0x570) @09b17a80
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
CAN_ch/170 (CAN_ch) @09b27630
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: can_main_ECU3/97 (write)can_main_ECU3/97 (write)can_main_ECU3/97 (write)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)can_main_ECU3/97 (read)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)clear_tx_buf/100 (write)clear_tx_buf/100 (write)clear_tx_buf/100 (write)clear_tx_ring/101 (read)clear_tx_ring/101 (write)clear_tx_ring/101 (read)clear_tx_ring/101 (write)clear_tx_ring/101 (read)clear_tx_ring/101 (write)can_tx_check/102 (read)can_tx_check/102 (read)can_send_txring/103 (read)can_send_txring/103 (write)can_send_txring/103 (read)can_send_txring/103 (write)can_send_txring/103 (read)can_send_txring/103 (write)can_send_txring/103 (read)can_send_txring/103 (write)can_send_txring/103 (read)can_send_txring/103 (write)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (read)can_transmit_txring/104 (addr)can_transmit_txring/104 (read)can_transmit_txring/104 (write)can_transmit_txring/104 (read)can_transmit_txring/104 (write)can_transmit_txring/104 (read)can_transmit_txring/104 (write)can_transmit_txring/104 (read)can_transmit_txring/104 (write)can_transmit_txring/104 (read)can_transmit_txring/104 (write)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
FlexCAN_Ip_Deinit_Privileged/169 (FlexCAN_Ip_Deinit_Privileged) @09b02620
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: CAN5_ErrCallback/95 CAN4_ErrCallback/93 CAN3_ErrCallback/91 CAN2_ErrCallback/89 CAN1_ErrCallback/87 CAN0_ErrCallback/85
|
|
Calls:
|
|
FlexCAN_Ip_Receive/168 (FlexCAN_Ip_Receive) @09b02380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 CAN5_Callback/94 CAN4_Callback/92 CAN3_Callback/90 CAN2_Callback/88 CAN1_Callback/86 CAN0_Callback/84
|
|
Calls:
|
|
Lpi2c_Ip_SlaveGetTransferStatus/167 (Lpi2c_Ip_SlaveGetTransferStatus) @09af7e00
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c_test/80
|
|
Calls:
|
|
Lpi2c_Ip_MasterGetTransferStatus/166 (Lpi2c_Ip_MasterGetTransferStatus) @09af7d20
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c_test/80
|
|
Calls:
|
|
Lpi2c_Ip_MasterSendData/165 (Lpi2c_Ip_MasterSendData) @09af7c40
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c_test/80
|
|
Calls:
|
|
Lpi2c_Ip_SlaveSetBuffer/164 (Lpi2c_Ip_SlaveSetBuffer) @09af7b60
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c_test/80
|
|
Calls:
|
|
I2c_Lpi2cMasterChannel0_BOARD_InitPeripherals/163 (I2c_Lpi2cMasterChannel0_BOARD_InitPeripherals) @09af6dc8
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: i2c1_init/79 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpi2c_Ip_MasterInit/162 (Lpi2c_Ip_MasterInit) @09af79a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c1_init/79
|
|
Calls:
|
|
LPI2C1_Master_Slave_IRQHandler/161 (LPI2C1_Master_Slave_IRQHandler) @09af78c0
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: i2c1_init/79 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
I2c_Lpi2cSlaveChannel1_BOARD_InitPeripherals/160 (I2c_Lpi2cSlaveChannel1_BOARD_InitPeripherals) @09af6bd0
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: i2c0_init/78 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpi2c_Ip_SlaveInit/159 (Lpi2c_Ip_SlaveInit) @09af7700
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: i2c0_init/78
|
|
Calls:
|
|
LPI2C0_Master_Slave_IRQHandler/158 (LPI2C0_Master_Slave_IRQHandler) @09af7620
|
|
Type: function
|
|
Visibility: external public
|
|
Address is taken.
|
|
References:
|
|
Referring: i2c0_init/78 (addr)
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by:
|
|
Calls:
|
|
IntCtrl_Ip_InstallHandler/157 (IntCtrl_Ip_InstallHandler) @09af7540
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Uart_Init/118 Uart_Init/118 Uart_Init/118 Uart_Init/118 Adc_Init/109 Adc_Init/109 Adc_Init/109 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 i2c1_init/79 i2c0_init/78
|
|
Calls:
|
|
Lpuart_Lin_Ip_GetTransmitStatus/156 (Lpuart_Lin_Ip_GetTransmitStatus) @09af7380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Lin_tx_test/77
|
|
Calls:
|
|
Lpuart_Lin_Ip_MasterSendHeader/155 (Lpuart_Lin_Ip_MasterSendHeader) @09af72a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Lin_tx_test/77
|
|
Calls:
|
|
Lpuart_Lin_Ip_AsyncSendFrameData/154 (Lpuart_Lin_Ip_AsyncSendFrameData) @09af7000
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Lin2callback/76 Lin1callback/75
|
|
Calls:
|
|
Lpuart_Lin_Ip_pHwConfigPB_1_BOARD_INITPERIPHERALS/153 (Lpuart_Lin_Ip_pHwConfigPB_1_BOARD_INITPERIPHERALS) @09af6048
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Lin_init/74 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpuart_Lin_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS/152 (Lpuart_Lin_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS) @09af0f78
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Lin_init/74 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpuart_Lin_Ip_Init/151 (Lpuart_Lin_Ip_Init) @09aeeee0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Lin_init/74 Lin_init/74
|
|
Calls:
|
|
IntCtrl_Ip_EnableIrq/150 (IntCtrl_Ip_EnableIrq) @09aeee00
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Uart_Init/118 Uart_Init/118 Uart_Init/118 Uart_Init/118 Adc_Init/109 Adc_Init/109 Adc_Init/109 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 Can_Init_ECU3/98 i2c1_init/79 i2c0_init/78 Lin_init/74 Lin_init/74
|
|
Calls:
|
|
Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals/149 (Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals) @09af0d38
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: SPI_test/73 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpspi_Ip_SyncTransmit/148 (Lpspi_Ip_SyncTransmit) @09aeeb60
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: SPI_test/73
|
|
Calls:
|
|
Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_BOARD_InitPeripherals/147 (Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_BOARD_InitPeripherals) @09af0990
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: SPI_init/72 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Lpspi_Ip_Init/146 (Lpspi_Ip_Init) @09aee9a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: SPI_init/72
|
|
Calls:
|
|
Emios_Pwm_Ip_SetDutyCycle/145 (Emios_Pwm_Ip_SetDutyCycle) @09aee7e0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: Set_PWM_Duty/68 Set_PWM_Duty/68 Set_PWM_Duty/68 Set_PWM_Duty/68
|
|
Calls:
|
|
gb/144 (gb) @09af0708
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: Set_PWM_Duty/68 (read)Set_PWM_Duty/68 (read)Set_PWM_Duty/68 (write)CAN0_Callback/84 (read)CAN0_Callback/84 (write)CAN0_Callback/84 (write)CAN0_Callback/84 (write)CAN0_Callback/84 (read)CAN0_Callback/84 (read)CAN0_Callback/84 (write)CAN0_Callback/84 (write)CAN0_ErrCallback/85 (write)CAN0_ErrCallback/85 (read)CAN0_ErrCallback/85 (read)CAN0_ErrCallback/85 (read)CAN0_ErrCallback/85 (read)CAN0_ErrCallback/85 (write)CAN1_Callback/86 (read)CAN1_Callback/86 (write)CAN1_Callback/86 (write)CAN1_Callback/86 (write)CAN1_Callback/86 (read)CAN1_Callback/86 (read)CAN1_Callback/86 (write)CAN1_Callback/86 (write)CAN1_ErrCallback/87 (write)CAN1_ErrCallback/87 (read)CAN1_ErrCallback/87 (read)CAN1_ErrCallback/87 (read)CAN1_ErrCallback/87 (read)CAN1_ErrCallback/87 (write)CAN2_Callback/88 (read)CAN2_Callback/88 (write)CAN2_Callback/88 (write)CAN2_Callback/88 (write)CAN2_Callback/88 (read)CAN2_Callback/88 (read)CAN2_Callback/88 (write)CAN2_Callback/88 (write)CAN2_ErrCallback/89 (write)CAN2_ErrCallback/89 (read)CAN2_ErrCallback/89 (read)CAN2_ErrCallback/89 (read)CAN2_ErrCallback/89 (read)CAN2_ErrCallback/89 (write)CAN3_Callback/90 (read)CAN3_Callback/90 (write)CAN3_Callback/90 (write)CAN3_Callback/90 (write)CAN3_Callback/90 (read)CAN3_Callback/90 (read)CAN3_Callback/90 (write)CAN3_Callback/90 (write)CAN3_ErrCallback/91 (write)CAN3_ErrCallback/91 (read)CAN3_ErrCallback/91 (read)CAN3_ErrCallback/91 (read)CAN3_ErrCallback/91 (read)CAN3_ErrCallback/91 (write)CAN4_Callback/92 (read)CAN4_Callback/92 (write)CAN4_Callback/92 (write)CAN4_Callback/92 (write)CAN4_Callback/92 (read)CAN4_Callback/92 (read)CAN4_Callback/92 (write)CAN4_Callback/92 (write)CAN4_ErrCallback/93 (write)CAN4_ErrCallback/93 (read)CAN4_ErrCallback/93 (read)CAN4_ErrCallback/93 (read)CAN4_ErrCallback/93 (read)CAN4_ErrCallback/93 (write)CAN5_Callback/94 (read)CAN5_Callback/94 (write)CAN5_Callback/94 (write)CAN5_Callback/94 (write)CAN5_Callback/94 (read)CAN5_Callback/94 (read)CAN5_Callback/94 (write)CAN5_Callback/94 (write)CAN5_ErrCallback/95 (write)CAN5_ErrCallback/95 (read)CAN5_ErrCallback/95 (read)CAN5_ErrCallback/95 (read)CAN5_ErrCallback/95 (read)CAN5_ErrCallback/95 (write)get_can_data/96 (read)get_can_data/96 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (read)can_main_ECU3/97 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)Can_Init_ECU3/98 (write)can_send_txring/103 (read)led_onoff/108 (write)ADC_Read/110 (read)ADC_Read/110 (read)ADC_Read/110 (read)ADC_Read/110 (read)ADC_Read/110 (read)ADC_Read/110 (read)Adc0EndOfChainNoti/111 (write)Adc1EndOfChainNoti/112 (write)Adc1EndOfChainNoti/112 (write)Adc2EndOfChainNoti/113 (write)Adc2EndOfChainNoti/113 (write)Adc2EndOfChainNoti/113 (write)tmr_delay/115 (read)tmr_delay/115 (read)Pit_Callback/116 (read)Pit_Callback/116 (write)Pit_Callback/116 (read)Pit_Callback/116 (write)Pit_Callback/116 (read)Pit_Callback/116 (write)Uart_Init/118 (addr)Uart_Init/118 (addr)Uart_Init/118 (addr)Uart_Init/118 (addr)UART0_RX_Callback/119 (read)UART0_RX_Callback/119 (read)UART0_RX_Callback/119 (write)UART0_RX_Callback/119 (read)UART0_RX_Callback/119 (write)UART0_RX_Callback/119 (addr)UART2_RX_Callback/120 (read)UART2_RX_Callback/120 (read)UART2_RX_Callback/120 (write)UART2_RX_Callback/120 (read)UART2_RX_Callback/120 (write)UART2_RX_Callback/120 (addr)UART10_RX_Callback/121 (read)UART10_RX_Callback/121 (read)UART10_RX_Callback/121 (write)UART10_RX_Callback/121 (read)UART10_RX_Callback/121 (write)UART10_RX_Callback/121 (addr)UART13_RX_Callback/122 (read)UART13_RX_Callback/122 (read)UART13_RX_Callback/122 (write)UART13_RX_Callback/122 (read)UART13_RX_Callback/122 (write)UART13_RX_Callback/122 (addr)UART1_RX_Callback/123 (read)UART1_RX_Callback/123 (read)UART1_RX_Callback/123 (write)UART1_RX_Callback/123 (read)UART1_RX_Callback/123 (write)UART1_RX_Callback/123 (addr)UART9_RX_Callback/124 (read)UART9_RX_Callback/124 (read)UART9_RX_Callback/124 (write)UART9_RX_Callback/124 (read)UART9_RX_Callback/124 (write)UART9_RX_Callback/124 (addr)Gvar_init/125 (write)Gvar_init/125 (write)Gvar_init/125 (write)Gvar_init/125 (write)Gvar_init/125 (write)Gvar_init/125 (write)register_bus_off_callback/126 (write)register_bus_off_callback/126 (write)get_char/127 (read)get_char/127 (read)get_char/127 (read)get_char/127 (read)get_char/127 (read)get_char/127 (write)get_line/129 (read)get_line/129 (addr)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (write)get_line/129 (write)get_line/129 (read)get_line/129 (read)get_line/129 (write)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (read)get_line/129 (write)get_line/129 (read)get_line/129 (write)get_line/129 (read)get_line/129 (write)get_line/129 (write)UART0_get_cmd/130 (read)UART0_get_cmd/130 (addr)UART0_get_cmd/130 (addr)
|
|
Availability: not_available
|
|
Varpool flags:
|
|
Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch3/143 (Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch3) @09af0318
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch2/142 (Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch2) @09af0288
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch1/141 (Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch1) @09af01f8
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch0/140 (Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch0) @09af0168
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Pwm_Ip_InitChannel/139 (Emios_Pwm_Ip_InitChannel) @09aee540
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: pwm_init/67 pwm_init/67 pwm_init/67 pwm_init/67
|
|
Calls:
|
|
Emios_Mcl_Ip_SetCounterBusPeriod/138 (Emios_Mcl_Ip_SetCounterBusPeriod) @09aee460
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: pwm_init/67
|
|
Calls:
|
|
Emios_Mcl_Ip_0_MasterBusConfig_BOARD_INITPERIPHERALS/137 (Emios_Mcl_Ip_0_MasterBusConfig_BOARD_INITPERIPHERALS) @09af0090
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (read)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Mcl_Ip_0_Config_BOARD_INITPERIPHERALS/136 (Emios_Mcl_Ip_0_Config_BOARD_INITPERIPHERALS) @09af0048
|
|
Type: variable
|
|
Body removed by symtab_remove_unreachable_nodes
|
|
Visibility: external public
|
|
References:
|
|
Referring: pwm_init/67 (addr)
|
|
Availability: not_available
|
|
Varpool flags: read-only
|
|
Emios_Mcl_Ip_Init/135 (Emios_Mcl_Ip_Init) @09aee380
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: pwm_init/67
|
|
Calls:
|
|
Emios_Mcl_Ip_Deinit/134 (Emios_Mcl_Ip_Deinit) @09aee2a0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: pwm_init/67
|
|
Calls:
|
|
Emios_Pwm_Ip_DeInitChannel/133 (Emios_Pwm_Ip_DeInitChannel) @09aee1c0
|
|
Type: function
|
|
Visibility: external public
|
|
References:
|
|
Referring:
|
|
Availability: not_available
|
|
Function flags: optimize_size
|
|
Called by: pwm_init/67 pwm_init/67 pwm_init/67 pwm_init/67
|
|
Calls:
|
|
setupCanTJA1153/132 (setupCanTJA1153) @09ae47e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: Can_Init_ECU3/98 Can_Init_ECU3/98
|
|
Calls: Siul2_Dio_Ip_WritePin/218 tmr_delay/115 FlexCAN_Ip_SendBlocking/285 FlexCAN_Ip_SendBlocking/285 FlexCAN_Ip_SendBlocking/285 FlexCAN_Ip_SendBlocking/285 FlexCAN_Ip_SendBlocking/285 Siul2_Dio_Ip_WritePin/218
|
|
debug_printf/131 (debug_printf) @09ae42a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: UART0_get_cmd/130 UART0_get_cmd/130 get_line/129 get_line/129 Adc_Init/109 Adc_Init/109 Adc_Init/109 Adc_Init/109 Adc_Init/109 Adc_Init/109 CAN5_ErrCallback/95 CAN5_ErrCallback/95 CAN4_ErrCallback/93 CAN4_ErrCallback/93 CAN3_ErrCallback/91 CAN3_ErrCallback/91 CAN2_ErrCallback/89 CAN2_ErrCallback/89 CAN1_ErrCallback/87 CAN0_ErrCallback/85 CAN0_ErrCallback/85 Lin_init/74 Lin_init/74
|
|
Calls: put_char/128 strlen/284 __builtin_va_end/283 vsprintf/282 __builtin_va_start/281
|
|
UART0_get_cmd/130 (UART0_get_cmd) @09ae4ee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (addr)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 debug_printf/131 strcmp/280 get_line/129
|
|
get_line/129 (get_line) @09ae4c40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (addr)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: UART0_get_cmd/130
|
|
Calls: put_char/128 debug_printf/131 debug_printf/131 get_char/127
|
|
put_char/128 (put_char) @09ae49a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: debug_printf/131 get_line/129
|
|
Calls: Lpuart_Uart_Ip_SyncSend/279
|
|
get_char/127 (get_char) @09ae4700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: get_line/129
|
|
Calls:
|
|
register_bus_off_callback/126 (register_bus_off_callback) @09ae4460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls:
|
|
Gvar_init/125 (Gvar_init) @09ae41c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (write)gb/144 (write)gb/144 (write)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls:
|
|
UART9_RX_Callback/124 (UART9_RX_Callback) @09adcd20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
UART1_RX_Callback/123 (UART1_RX_Callback) @09adc540
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
UART13_RX_Callback/122 (UART13_RX_Callback) @09adcee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
UART10_RX_Callback/121 (UART10_RX_Callback) @09adcc40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
UART2_RX_Callback/120 (UART2_RX_Callback) @09adc9a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
UART0_RX_Callback/119 (UART0_RX_Callback) @09adc700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_SetRxBuffer/278
|
|
Uart_Init/118 (Uart_Init) @09adc460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: LPUART_UART_IP_0_IRQHandler/268 (addr)LPUART_UART_IP_2_IRQHandler/269 (addr)LPUART_UART_IP_10_IRQHandler/270 (addr)LPUART_UART_IP_13_IRQHandler/271 (addr)Lpuart_Uart_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS/273 (addr)Lpuart_Uart_Ip_pHwConfigPB_2_BOARD_INITPERIPHERALS/274 (addr)Lpuart_Uart_Ip_pHwConfigPB_10_BOARD_INITPERIPHERALS/275 (addr)Lpuart_Uart_Ip_pHwConfigPB_13_BOARD_INITPERIPHERALS/276 (addr)gb/144 (addr)gb/144 (addr)gb/144 (addr)gb/144 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Uart_Ip_AsyncReceive/277 Lpuart_Uart_Ip_AsyncReceive/277 Lpuart_Uart_Ip_AsyncReceive/277 Lpuart_Uart_Ip_AsyncReceive/277 Lpuart_Uart_Ip_Init/272 Lpuart_Uart_Ip_Init/272 Lpuart_Uart_Ip_Init/272 Lpuart_Uart_Ip_Init/272 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150
|
|
board_init/117 (board_init) @09adc1c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: led_onoff/108
|
|
Pit_Callback/116 (Pit_Callback) @09ad0e00
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: t.15143/265 (read)t.15143/265 (write)gb/144 (read)gb/144 (write)t.15143/265 (write)gb/144 (read)gb/144 (write)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: task_500us/267 uds_timer_interrupt/266
|
|
tmr_delay/115 (tmr_delay) @09ad0620
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: setupCanTJA1153/132
|
|
Calls:
|
|
Adc_Read_ch/114 (Adc_Read_ch) @09ad00e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Adc_Sar_Ip_StartConversion/264
|
|
Adc2EndOfChainNoti/113 (Adc2EndOfChainNoti) @09ad0d20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Adc_Sar_Ip_GetConvData/263 Adc_Sar_Ip_GetConvData/263 Adc_Sar_Ip_GetConvData/263
|
|
Adc1EndOfChainNoti/112 (Adc1EndOfChainNoti) @09ad0a80
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Adc_Sar_Ip_GetConvData/263 Adc_Sar_Ip_GetConvData/263
|
|
Adc0EndOfChainNoti/111 (Adc0EndOfChainNoti) @09ad07e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
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Called by:
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Calls: Adc_Sar_Ip_GetConvData/263
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ADC_Read/110 (ADC_Read) @09ad0540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls:
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Adc_Init/109 (Adc_Init) @09ad02a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: AdcHwUnit_0_BOARD_INITPERIPHERALS/255 (addr)AdcHwUnit_1_BOARD_INITPERIPHERALS/256 (addr)AdcHwUnit_2_BOARD_INITPERIPHERALS/257 (addr)Adc_Sar_0_Isr/258 (addr)Adc_Sar_1_Isr/259 (addr)Adc_Sar_2_Isr/260 (addr)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Adc_Sar_Ip_EnableNotifications/262 Adc_Sar_Ip_EnableNotifications/262 Adc_Sar_Ip_EnableNotifications/262 debug_printf/131 Adc_Sar_Ip_DoCalibration/261 debug_printf/131 Adc_Sar_Ip_DoCalibration/261 debug_printf/131 Adc_Sar_Ip_DoCalibration/261 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_InstallHandler/157 debug_printf/131 Adc_Sar_Ip_Init/254 debug_printf/131 Adc_Sar_Ip_Init/254 debug_printf/131 Adc_Sar_Ip_Init/254
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led_onoff/108 (led_onoff) @09ad0000
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Type: function definition analyzed
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Visibility: externally_visible public
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References: gb/144 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by: board_init/117
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Calls: Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218
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Digital_Read/107 (Digital_Read) @09ac0b60
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Type: function definition analyzed
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Visibility: externally_visible public
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References:
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253 Siul2_Dio_Ip_ReadPin/253
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Digital_Write/106 (Digital_Write) @09ac0620
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Type: function definition analyzed
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Visibility: externally_visible public
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References:
|
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Referring:
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Availability: available
|
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Function flags: body optimize_size
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Called by:
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Calls: Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218
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DIN_TEST/105 (DIN_TEST) @09ac00e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: din_test/45 (write)
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Referring:
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Availability: available
|
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Function flags: body optimize_size
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Called by:
|
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Calls: Siul2_Dio_Ip_ReadPin/253
|
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can_transmit_txring/104 (can_transmit_txring) @09ac0d20
|
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Type: function definition analyzed
|
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Visibility: externally_visible public
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References: CAN_ch/170 (read)CAN_ch/170 (read)tx_info/64 (write)CAN_ch/170 (read)CAN_ch/170 (read)tx_info/64 (write)CAN_ch/170 (read)CAN_ch/170 (read)tx_info/64 (write)CAN_ch/170 (read)CAN_ch/170 (read)tx_info/64 (write)CAN_ch/170 (read)CAN_ch/170 (read)tx_info/64 (write)CAN_ch/170 (read)tx_info/64 (addr)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (addr)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)vcan_send_miss_message/46 (read)vcan_send_miss_message/46 (write)
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Referring:
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Availability: available
|
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Function flags: body optimize_size
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Called by: can_tx_check/102
|
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Calls: clear_tx_ring/101 clear_tx_ring/101 FlexCAN_Ip_Send/252
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can_send_txring/103 (can_send_txring) @09ac0a80
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Type: function definition analyzed
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Visibility: externally_visible public
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References: tx_info/64 (read)gb/144 (read)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: clear_tx_buf/100
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can_tx_check/102 (can_tx_check) @09ac07e0
|
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Type: function definition analyzed
|
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Visibility: externally_visible public
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References: CAN_ch/170 (read)CAN_ch/170 (read)
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Referring:
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Availability: available
|
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Function flags: body optimize_size
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Called by:
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Calls: can_transmit_txring/104
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clear_tx_ring/101 (clear_tx_ring) @09ac0540
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Type: function definition analyzed
|
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Visibility: externally_visible public
|
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References: CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (write)
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Referring:
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Availability: available
|
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Function flags: body optimize_size
|
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Called by: can_transmit_txring/104 can_transmit_txring/104
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Calls:
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clear_tx_buf/100 (clear_tx_buf) @09ac02a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: CAN_ch/170 (write)CAN_ch/170 (write)CAN_ch/170 (write)
|
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Referring:
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|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: can_send_txring/103 Can_Init_ECU3/98
|
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Calls:
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ECU3_Data_Init/99 (ECU3_Data_Init) @09ac0000
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Type: function definition analyzed
|
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Visibility: externally_visible public
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References: ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)ECU3/251 (write)
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Referring:
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Availability: available
|
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Function flags: body optimize_size
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Called by: Can_Init_ECU3/98
|
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Calls:
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Can_Init_ECU3/98 (Can_Init_ECU3) @099ea540
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Type: function definition analyzed
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Visibility: externally_visible public
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References: CAN0_ORED_IRQHandler/216 (addr)CAN0_ORED_0_31_MB_IRQHandler/217 (addr)FlexCAN_State0/220 (addr)FlexCAN_Config0/221 (addr)rx_info/65 (addr)can0_rxData/58 (addr)gb/144 (write)gb/144 (write)CAN1_ORED_IRQHandler/226 (addr)CAN1_ORED_0_31_MB_IRQHandler/227 (addr)FlexCAN_State1/228 (addr)FlexCAN_Config1/229 (addr)rx_info/65 (addr)g_messageObjectConf_ECU3_1ch_RX/230 (read)can1_rxData/59 (addr)gb/144 (write)gb/144 (write)CAN2_ORED_IRQHandler/231 (addr)CAN2_ORED_0_31_MB_IRQHandler/232 (addr)FlexCAN_State2/233 (addr)FlexCAN_Config2/234 (addr)rx_info/65 (addr)g_messageObjectConf_ECU3_2ch_RX/235 (read)can2_rxData/60 (addr)gb/144 (write)gb/144 (write)CAN3_ORED_IRQHandler/236 (addr)CAN3_ORED_0_31_MB_IRQHandler/237 (addr)FlexCAN_State3/238 (addr)FlexCAN_Config3/239 (addr)rx_info/65 (addr)g_messageObjectConf_ECU3_3ch_RX/240 (read)can3_rxData/61 (addr)gb/144 (write)gb/144 (write)CAN4_ORED_IRQHandler/241 (addr)CAN4_ORED_0_31_MB_IRQHandler/242 (addr)FlexCAN_State4/243 (addr)FlexCAN_Config_500k/66 (addr)FlexCAN_State4/243 (addr)FlexCAN_Config4/244 (addr)rx_info/65 (addr)g_messageObjectConf_ECU3_4ch_RX/245 (read)can4_rxData/62 (addr)gb/144 (write)gb/144 (write)CAN5_ORED_IRQHandler/246 (addr)CAN5_ORED_0_31_MB_IRQHandler/247 (addr)FlexCAN_State5/248 (addr)FlexCAN_Config_500k/66 (addr)FlexCAN_State5/248 (addr)FlexCAN_Config5/249 (addr)rx_info/65 (addr)g_messageObjectConf_ECU3_5ch_RX/250 (read)can5_rxData/63 (addr)gb/144 (write)gb/144 (write)CAN_ch/170 (write)CAN_ch/170 (write)CAN_ch/170 (write)
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Referring:
|
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Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
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Calls: FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 setupCanTJA1153/132 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 setupCanTJA1153/132 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 clear_tx_buf/100 ECU3_Data_Init/99 FlexCAN_Ip_Receive/168 FlexCAN_Ip_ConfigRxMb/225 FlexCAN_Ip_SetStartMode_Privileged/224 FlexCAN_Ip_SetRxIndividualMask_Privileged/223 FlexCAN_Ip_SetRxMaskType_Privileged/222 FlexCAN_Ip_Init_Privileged/219 Siul2_Dio_Ip_WritePin/218 Siul2_Dio_Ip_WritePin/218 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150
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can_main_ECU3/97 (can_main_ECU3) @099ea700
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Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)CAN_ch/170 (write)gb/144 (read)gb/144 (read)CAN_ch/170 (write)gb/144 (read)CAN_ch/170 (write)CAN_ch/170 (write)gb/144 (read)gb/144 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)GV_CH0_0x301_CNT/179 (read)GV_CH0_0x301_CNT/179 (write)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)CAN_ch/170 (read)CAN_ch/170 (write)CAN_ch/170 (read)
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Referring:
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|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
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Calls: Receive_RWS_VCU_stat_Signal_CH5_0x072/215 Receive_RWS_VCU_Rack_AngleFbk_CH5_0x073/214 Receive_RWS_VCU_stat_Signal_CH4_0x072/213 Receive_RWS_VCU_Rack_AngleFbk_CH4_0x073/212 Receive_RCU_UdsResponse_CH3_0x799/211 Receive_RCU_Status_CH3_0x093/210 Receive_RCU_WheelStatus_CH3_0x08D/209 Receive_RCU_TireSlipStatus_CH3_0x097/208 Receive_RWA_Status3_CH3_0x0AA/207 Receive_RWA_Status2_CH3_0x073/206 Receive_RWA_Status1_CH3_0x072/205 Receive_RCU_PressureStatus_CH3_0x0A1/204 Receive_RCU_BrakeStatus2_CH3_0x0C9/203 Receive_RCU_BrakeStatus1_CH3_0x09B/202 Receive_RWA_Status3_CH2_0x0AA/201 Receive_RWA_Status2_CH2_0x073/200 Receive_RWA_Status1_CH2_0x072/199 Receive_IDB_WheelStatus_CH2_0x08C/198 Receive_IDB_UdsResponse_CH2_0x798/197 Receive_IDB_TireSlipStatus_CH2_0x096/196 Receive_IDB_Status_CH2_0x092/195 Receive_IDB_RegenTcsRequest_CH2_0x082/194 Receive_IDB_PressureStatus_CH2_0x0A0/193 Receive_IDB_BrakeStatus2_CH2_0x0C8/192 Receive_IDB_BrakeStatus1_CH2_0x09A/191 Receive_ACU_BCM_Signal_1_CH1_0x150/190 Receive_ACU_VCU_Signal3_CH1_0x093/189 Receive_ACU_VCU_Signal2_CH1_0x092/188 Receive_ACU_VCU_Signal1_CH1_0x091/187 Receive_EPAM_VCU_CH0_0x221/186 Receive_RC_VCU_BCM_Signal_1_CH0_0x155/185 Receive_IMU_TX1_CH0_0x17C/184 Receive_IMU_TX1_CH0_0x178/183 Receive_IMU_TX1_CH0_0x174/182 Receive_RC_VCU_Signal2_CH0_0x041/181 Receive_RC_VCU_Signal1_CH0_0x040/180 Receive_MCU_VCU_Signals2_CH0_0x301/178 Receive_MCU_VCU_Signals1_CH0_0x300/177 Receive_IMU_VCU_Signal_CH0_0x020/176 Receive_BCM_VCU_Signal5_CH0_0x585/175 Receive_BCM_VCU_Signal4_CH0_0x595/174 Receive_BCM_VCU_Signal3_CH0_0x590/173 Receive_BCM_VCU_Signal2_CH0_0x580/172 Receive_BCM_VCU_Signal1_CH0_0x570/171 get_can_data/96
|
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get_can_data/96 (get_can_data) @099ea460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: can_main_ECU3/97
|
|
Calls:
|
|
CAN5_ErrCallback/95 (CAN5_ErrCallback) @099ea1c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
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|
Calls: debug_printf/131 FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN5_Callback/94 (CAN5_Callback) @099dfee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can5_rxData/63 (addr)gb/144 (read)can5_rxData/63 (read)gb/144 (write)can5_rxData/63 (read)gb/144 (write)can5_rxData/63 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
CAN4_ErrCallback/93 (CAN4_ErrCallback) @099dfc40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN4_Callback/92 (CAN4_Callback) @099df9a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can4_rxData/62 (addr)gb/144 (read)can4_rxData/62 (read)gb/144 (write)can4_rxData/62 (read)gb/144 (write)can4_rxData/62 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
CAN3_ErrCallback/91 (CAN3_ErrCallback) @099df700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN3_Callback/90 (CAN3_Callback) @099df460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can3_rxData/61 (addr)gb/144 (read)can3_rxData/61 (read)gb/144 (write)can3_rxData/61 (read)gb/144 (write)can3_rxData/61 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
CAN2_ErrCallback/89 (CAN2_ErrCallback) @099df1c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN2_Callback/88 (CAN2_Callback) @099d30e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can2_rxData/60 (addr)gb/144 (read)can2_rxData/60 (read)gb/144 (write)can2_rxData/60 (read)gb/144 (write)can2_rxData/60 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
CAN1_ErrCallback/87 (CAN1_ErrCallback) @099d3d20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN1_Callback/86 (CAN1_Callback) @099d3a80
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can1_rxData/59 (addr)gb/144 (read)can1_rxData/59 (read)gb/144 (write)can1_rxData/59 (read)gb/144 (write)can1_rxData/59 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
CAN0_ErrCallback/85 (CAN0_ErrCallback) @099d37e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 FlexCAN_Ip_Deinit_Privileged/169 debug_printf/131
|
|
Indirect call
|
|
CAN0_Callback/84 (CAN0_Callback) @099d3540
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: can0_rxData/58 (addr)gb/144 (read)can0_rxData/58 (read)gb/144 (write)can0_rxData/58 (read)gb/144 (write)can0_rxData/58 (read)gb/144 (write)gb/144 (read)gb/144 (read)gb/144 (write)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: FlexCAN_Ip_Receive/168
|
|
i2c_delay/83 (i2c_delay) @099d32a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: sda_out/82 sda_in/81
|
|
Calls:
|
|
sda_out/82 (sda_out) @099d3000
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: i2c_delay/83
|
|
sda_in/81 (sda_in) @099ccb60
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: i2c_delay/83
|
|
i2c_test/80 (i2c_test) @099cc460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: rxBufferSlave/49 (addr)txBuffer/50 (addr)txBuffer/50 (read)rxBufferSlave/49 (read)txBuffer/50 (read)txBuffer/50 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpi2c_Ip_SlaveGetTransferStatus/167 Lpi2c_Ip_MasterGetTransferStatus/166 Lpi2c_Ip_MasterSendData/165 Lpi2c_Ip_SlaveSetBuffer/164
|
|
i2c1_init/79 (i2c1_init) @099cc1c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: LPI2C1_Master_Slave_IRQHandler/161 (addr)I2c_Lpi2cMasterChannel0_BOARD_InitPeripherals/163 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpi2c_Ip_MasterInit/162 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150
|
|
i2c0_init/78 (i2c0_init) @099c9700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: LPI2C0_Master_Slave_IRQHandler/158 (addr)I2c_Lpi2cSlaveChannel1_BOARD_InitPeripherals/160 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpi2c_Ip_SlaveInit/159 IntCtrl_Ip_InstallHandler/157 IntCtrl_Ip_EnableIrq/150
|
|
Lin_tx_test/77 (Lin_tx_test) @099c20e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: isSend/57 (read)isSend/57 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Lin_Ip_GetTransmitStatus/156 Lpuart_Lin_Ip_MasterSendHeader/155
|
|
Lin2callback/76 (Lin2callback) @099c2d20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: isSend/57 (write)txBuff_lin/55 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Lin_Ip_AsyncSendFrameData/154
|
|
Lin1callback/75 (Lin1callback) @099c2a80
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: isSend/57 (write)txBuff_lin/55 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpuart_Lin_Ip_AsyncSendFrameData/154
|
|
Lin_init/74 (Lin_init) @099c27e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: Lpuart_Lin_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS/152 (addr)Lpuart_Lin_Ip_pHwConfigPB_1_BOARD_INITPERIPHERALS/153 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: debug_printf/131 Lpuart_Lin_Ip_Init/151 Lpuart_Lin_Ip_Init/151 debug_printf/131 IntCtrl_Ip_EnableIrq/150 IntCtrl_Ip_EnableIrq/150
|
|
SPI_test/73 (SPI_test) @099c2540
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: passed/69 (write)numberOfBytes/53 (read)timeOut/54 (read)Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals/149 (addr)txBuffer_spi/51 (addr)rxBuffer_spi/52 (addr)trans_ret/71 (write)txBuffer_spi/51 (read)rxBuffer_spi/52 (read)passed/69 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpspi_Ip_SyncTransmit/148
|
|
SPI_init/72 (SPI_init) @099c22a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_BOARD_InitPeripherals/147 (addr)init_ret/70 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Lpspi_Ip_Init/146
|
|
trans_ret/71 (trans_ret) @09a41a68
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (write)
|
|
Availability: available
|
|
Varpool flags:
|
|
init_ret/70 (init_ret) @09a419d8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_init/72 (write)
|
|
Availability: available
|
|
Varpool flags:
|
|
passed/69 (passed) @09a41948
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (write)SPI_test/73 (write)
|
|
Availability: available
|
|
Varpool flags:
|
|
Set_PWM_Duty/68 (Set_PWM_Duty) @09a40ee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: gb/144 (read)gb/144 (read)gb/144 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Emios_Pwm_Ip_SetDutyCycle/145 Emios_Pwm_Ip_SetDutyCycle/145 Emios_Pwm_Ip_SetDutyCycle/145 Emios_Pwm_Ip_SetDutyCycle/145
|
|
pwm_init/67 (pwm_init) @09a40c40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: Emios_Mcl_Ip_0_Config_BOARD_INITPERIPHERALS/136 (addr)Emios_Mcl_Ip_0_MasterBusConfig_BOARD_INITPERIPHERALS/137 (read)Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch0/140 (addr)Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch1/141 (addr)Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch2/142 (addr)Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch3/143 (addr)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Emios_Pwm_Ip_InitChannel/139 Emios_Pwm_Ip_InitChannel/139 Emios_Pwm_Ip_InitChannel/139 Emios_Pwm_Ip_InitChannel/139 Emios_Mcl_Ip_SetCounterBusPeriod/138 Emios_Mcl_Ip_Init/135 Emios_Mcl_Ip_Deinit/134 Emios_Pwm_Ip_DeInitChannel/133 Emios_Pwm_Ip_DeInitChannel/133 Emios_Pwm_Ip_DeInitChannel/133 Emios_Pwm_Ip_DeInitChannel/133
|
|
FlexCAN_Config_500k/66 (FlexCAN_Config_500k) @09a417e0
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags: initialized read-only const-value-known
|
|
rx_info/65 (rx_info) @09a41678
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
tx_info/64 (tx_info) @09a41438
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: can_send_txring/103 (read)can_transmit_txring/104 (write)can_transmit_txring/104 (write)can_transmit_txring/104 (write)can_transmit_txring/104 (write)can_transmit_txring/104 (write)can_transmit_txring/104 (addr)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
can5_rxData/63 (can5_rxData) @09a411f8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN5_Callback/94 (addr)CAN5_Callback/94 (read)CAN5_Callback/94 (read)CAN5_Callback/94 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
can4_rxData/62 (can4_rxData) @09a41168
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN4_Callback/92 (addr)CAN4_Callback/92 (read)CAN4_Callback/92 (read)CAN4_Callback/92 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
can3_rxData/61 (can3_rxData) @09a410d8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN3_Callback/90 (addr)CAN3_Callback/90 (read)CAN3_Callback/90 (read)CAN3_Callback/90 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
can2_rxData/60 (can2_rxData) @09a41048
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN2_Callback/88 (addr)CAN2_Callback/88 (read)CAN2_Callback/88 (read)CAN2_Callback/88 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
can1_rxData/59 (can1_rxData) @09a39750
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN1_Callback/86 (addr)CAN1_Callback/86 (read)CAN1_Callback/86 (read)CAN1_Callback/86 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
can0_rxData/58 (can0_rxData) @09a39f78
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: CAN0_Callback/84 (addr)CAN0_Callback/84 (read)CAN0_Callback/84 (read)CAN0_Callback/84 (read)Can_Init_ECU3/98 (addr)
|
|
Availability: available
|
|
Varpool flags:
|
|
isSend/57 (isSend) @09a39ab0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output externally_visible public
|
|
References:
|
|
Referring: Lin1callback/75 (write)Lin2callback/76 (write)Lin_tx_test/77 (read)Lin_tx_test/77 (read)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
txBuff/56 (txBuff) @09a39a20
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
txBuff_lin/55 (txBuff_lin) @09a399d8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: Lin1callback/75 (addr)Lin2callback/76 (addr)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
timeOut/54 (timeOut) @09a39948
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (read)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
numberOfBytes/53 (numberOfBytes) @09a398b8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (read)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
rxBuffer_spi/52 (rxBuffer_spi) @09a39828
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (addr)SPI_test/73 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
txBuffer_spi/51 (txBuffer_spi) @09a39798
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: SPI_test/73 (addr)SPI_test/73 (read)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
txBuffer/50 (txBuffer) @09a396c0
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: i2c_test/80 (addr)i2c_test/80 (read)i2c_test/80 (read)i2c_test/80 (write)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
rxBufferSlave/49 (rxBufferSlave) @09a395e8
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: i2c_test/80 (addr)i2c_test/80 (read)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
hscan_test_buf/48 (hscan_test_buf) @0970d750
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
canfd_test_buf/47 (canfd_test_buf) @0970d6c0
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
vcan_send_miss_message/46 (vcan_send_miss_message) @0970d630
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: can_transmit_txring/104 (read)can_transmit_txring/104 (write)
|
|
Availability: available
|
|
Varpool flags: initialized
|
|
din_test/45 (din_test) @0970d5a0
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring: DIN_TEST/105 (write)
|
|
Availability: available
|
|
Varpool flags:
|
|
adc_test1/44 (adc_test1) @0970d510
|
|
Type: variable definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Varpool flags:
|
|
setupCanTJA1153 (int instance, struct Siul2_Dio_Ip_GpioType * const stb_port, Siul2_Dio_Ip_PinsChannelType stb_pin)
|
|
{
|
|
uint8_t sendData[8];
|
|
struct Flexcan_Ip_DataInfoType tx_info;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 0;
|
|
tx_info.data_length = 8;
|
|
tx_info.fd_enable = 0;
|
|
tx_info.fd_padding = 0;
|
|
tx_info.enable_brs = 0;
|
|
tx_info.is_remote = 0;
|
|
tx_info.is_polling = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sendData = "\x00\x00\x00\x00\x00\x00\x00";
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (stb_port, stb_pin, 0);
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.is_polling = 1;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 0;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.data_length = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) instance;
|
|
FlexCAN_Ip_SendBlocking (_1, 0, &tx_info, 1365, &sendData, 100);
|
|
# DEBUG BEGIN_STMT
|
|
sendData[0] = 16;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[1] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[2] = 80;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[3] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[4] = 7;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[5] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 1;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.data_length = 6;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (unsigned char) instance;
|
|
FlexCAN_Ip_SendBlocking (_2, 0, &tx_info, 416940273, &sendData, 100);
|
|
# DEBUG BEGIN_STMT
|
|
sendData[0] = 16;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[1] = 1;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[2] = 159;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[3] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[4] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[5] = 255;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 1;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.data_length = 6;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (unsigned char) instance;
|
|
FlexCAN_Ip_SendBlocking (_3, 0, &tx_info, 416940273, &sendData, 100);
|
|
# DEBUG BEGIN_STMT
|
|
sendData[0] = 16;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[1] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[2] = 192;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[3] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[4] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[5] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 1;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.data_length = 6;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (unsigned char) instance;
|
|
FlexCAN_Ip_SendBlocking (_4, 0, &tx_info, 416940273, &sendData, 100);
|
|
# DEBUG BEGIN_STMT
|
|
sendData[0] = 113;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[1] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[2] = 3;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[3] = 4;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[4] = 5;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[5] = 6;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[6] = 7;
|
|
# DEBUG BEGIN_STMT
|
|
sendData[7] = 8;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.msg_id_type = 1;
|
|
# DEBUG BEGIN_STMT
|
|
tx_info.data_length = 8;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (unsigned char) instance;
|
|
FlexCAN_Ip_SendBlocking (_5, 0, &tx_info, 416940273, &sendData, 100);
|
|
# DEBUG BEGIN_STMT
|
|
tmr_delay (10);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (stb_port, stb_pin, 1);
|
|
tx_info = {CLOBBER};
|
|
sendData = {CLOBBER};
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
debug_printf (char * msg)
|
|
{
|
|
u8 len;
|
|
u8 i;
|
|
struct va_list argptr;
|
|
char str[256];
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__builtin_va_start (&argptr, 0);
|
|
# DEBUG BEGIN_STMT
|
|
vsprintf (&str, msg, argptr);
|
|
# DEBUG BEGIN_STMT
|
|
__builtin_va_end (&argptr);
|
|
# DEBUG BEGIN_STMT
|
|
_1 = strlen (&str);
|
|
len = (u8) _1;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) i;
|
|
_3 = str[_2];
|
|
put_char (_3);
|
|
# DEBUG BEGIN_STMT
|
|
i.40_4 = i;
|
|
i = i.40_4 + 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i < len)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
str = {CLOBBER};
|
|
argptr = {CLOBBER};
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART0_get_cmd ()
|
|
{
|
|
int ret;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
ret = get_line (128);
|
|
# DEBUG BEGIN_STMT
|
|
if (ret == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.cmd_buf[0];
|
|
if (_1 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_2 = strcmp (&gb.cmd_buf, "test1");
|
|
if (_2 == 0)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("test1\r\n");
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("Command not found : %s\r\n", &gb.cmd_buf);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
get_line (u32 max_len)
|
|
{
|
|
int D.15443;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.cmd_idx;
|
|
_2 = &gb.cmd_buf[_1];
|
|
_3 = get_char (_2);
|
|
if (_3 == 1)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15443 = 1;
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_4 = gb.cmd_idx;
|
|
_5 = gb.cmd_buf[_4];
|
|
_6 = (int) _5;
|
|
switch (_6) <default: <L7> [INV], case 8: <L4> [INV], case 10: <L2> [INV], case 13: <L2> [INV]>
|
|
|
|
<bb 5> :
|
|
<L2>:
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("\r\n");
|
|
# DEBUG BEGIN_STMT
|
|
_7 = gb.cmd_idx;
|
|
gb.cmd_buf[_7] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
gb.cmd_idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
D.15443 = 0;
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 6> :
|
|
<L4>:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = gb.cmd_idx;
|
|
if (_8 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = gb.cmd_idx;
|
|
_10 = _9 + 4294967295;
|
|
gb.cmd_idx = _10;
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("\b \b");
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 8> :
|
|
<L7>:
|
|
# DEBUG BEGIN_STMT
|
|
_11 = gb.cmd_idx;
|
|
_12 = gb.cmd_buf[_11];
|
|
_13 = _12 + 224;
|
|
if (_13 <= 94)
|
|
goto <bb 9>; [INV]
|
|
else
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
_14 = gb.cmd_idx;
|
|
_15 = gb.cmd_buf[_14];
|
|
put_char (_15);
|
|
# DEBUG BEGIN_STMT
|
|
_16 = gb.cmd_idx;
|
|
_17 = gb.cmd_buf[_16];
|
|
_18 = gb.cmd_idx;
|
|
_19 = _17 + 208;
|
|
gb.cmd_buf_no[_18] = _19;
|
|
# DEBUG BEGIN_STMT
|
|
_20 = gb.cmd_idx;
|
|
_21 = _20 + 1;
|
|
gb.cmd_idx = _21;
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
_22 = gb.cmd_idx;
|
|
if (max_len <= _22)
|
|
goto <bb 11>; [INV]
|
|
else
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
_23 = max_len + 4294967295;
|
|
gb.cmd_buf[_23] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
gb.cmd_idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
D.15443 = 0;
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15443 = 1;
|
|
|
|
<bb 13> :
|
|
return D.15443;
|
|
|
|
}
|
|
|
|
|
|
put_char (char ch)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SyncSend (0, &ch, 1);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
get_char (char * ch)
|
|
{
|
|
int D.15439;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.ubuf_head;
|
|
_2 = gb.ubuf_tail;
|
|
if (_1 == _2)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15439 = 1;
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.ubuf_head;
|
|
_4 = gb.ubuf[_3];
|
|
*ch = _4;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = gb.ubuf_head;
|
|
_6 = _5 + 1;
|
|
_7 = _6 & 255;
|
|
gb.ubuf_head = _7;
|
|
# DEBUG BEGIN_STMT
|
|
D.15439 = 0;
|
|
|
|
<bb 5> :
|
|
return D.15439;
|
|
|
|
}
|
|
|
|
|
|
register_bus_off_callback (int ch, void (*user_callback) (int) fp, int param)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off_callback = fp;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].param = param;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Gvar_init ()
|
|
{
|
|
u32 i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
gb.ubuf_head = 0;
|
|
# DEBUG BEGIN_STMT
|
|
gb.ubuf_tail = 0;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[i].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 5)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[i].bus_off_callback = 0B;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 5)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.pwm_freq = 50000;
|
|
# DEBUG BEGIN_STMT
|
|
gb.pwm_max_tick = 3200;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART9_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.uart9_buf_tail;
|
|
_2 = gb.uart9_temp[0];
|
|
gb.uart9_buf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.uart9_buf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.uart9_buf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.uart9_temp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART1_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.uart1_buf_tail;
|
|
_2 = gb.uart1_temp[0];
|
|
gb.uart1_buf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.uart1_buf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.uart1_buf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.uart1_temp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART13_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.uart13_buf_tail;
|
|
_2 = gb.uart13_temp[0];
|
|
gb.uart13_buf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.uart13_buf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.uart13_buf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.uart13_temp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART10_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.uart10_buf_tail;
|
|
_2 = gb.uart10_temp[0];
|
|
gb.uart10_buf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.uart10_buf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.uart10_buf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.uart10_temp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART2_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.bbuf_tail;
|
|
_2 = gb.btemp[0];
|
|
gb.bbuf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.bbuf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.bbuf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.btemp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
UART0_RX_Callback (uint32_t instance, void * driverState, Lpuart_Uart_Ip_EventType event, void * userData)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (event == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.ubuf_tail;
|
|
_2 = gb.utemp[0];
|
|
gb.ubuf[_1] = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.ubuf_tail;
|
|
_4 = _3 + 1;
|
|
_5 = _4 & 255;
|
|
gb.ubuf_tail = _5;
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_SetRxBuffer (instance, &gb.utemp, 1);
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Uart_Init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (141);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (141, LPUART_UART_IP_0_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (143);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (143, LPUART_UART_IP_2_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (151);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (151, LPUART_UART_IP_10_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (154);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (154, LPUART_UART_IP_13_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_Init (0, &Lpuart_Uart_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_Init (2, &Lpuart_Uart_Ip_pHwConfigPB_2_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_Init (10, &Lpuart_Uart_Ip_pHwConfigPB_10_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_Init (13, &Lpuart_Uart_Ip_pHwConfigPB_13_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_AsyncReceive (0, &gb.utemp, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_AsyncReceive (2, &gb.btemp, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_AsyncReceive (10, &gb.uart10_temp, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Uart_Ip_AsyncReceive (13, &gb.uart13_temp, 1);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
board_init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
led_onoff (0);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Pit_Callback ()
|
|
{
|
|
static uint8_t t = 0;
|
|
u32 i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
t.39_1 = t;
|
|
if (t.39_1 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
t = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = gb.x500us;
|
|
_3 = _2 + 1;
|
|
gb.x500us = _3;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
uds_timer_interrupt ();
|
|
# DEBUG BEGIN_STMT
|
|
t = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = gb.x500us;
|
|
_5 = _4 + 1;
|
|
gb.x500us = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = gb.tmr_cnt;
|
|
_7 = _6 + 1;
|
|
gb.tmr_cnt = _7;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
task_500us ();
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
tmr_delay (u32 delay)
|
|
{
|
|
volatile u64 elapse;
|
|
volatile u64 start;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.tmr_cnt;
|
|
start = _1;
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_2 = gb.tmr_cnt;
|
|
start.37_3 = start;
|
|
_4 = _2 - start.37_3;
|
|
elapse = _4;
|
|
# DEBUG BEGIN_STMT
|
|
elapse.38_5 = elapse;
|
|
if (delay < elapse.38_5)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 3>; [INV]
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Adc_Read_ch (uint8_t ch)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (long unsigned int) ch;
|
|
Adc_Sar_Ip_StartConversion (_1, 0);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Adc2EndOfChainNoti ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Adc_Sar_Ip_GetConvData (2, 3);
|
|
gb.ADC2 = _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = Adc_Sar_Ip_GetConvData (2, 4);
|
|
gb.ADC3 = _2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Adc_Sar_Ip_GetConvData (2, 5);
|
|
gb.ADC4 = _3;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Adc1EndOfChainNoti ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Adc_Sar_Ip_GetConvData (1, 2);
|
|
gb.ADC1 = _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = Adc_Sar_Ip_GetConvData (1, 43);
|
|
gb.AIN_bat = _2;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Adc0EndOfChainNoti ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Adc_Sar_Ip_GetConvData (0, 6);
|
|
gb.ADC0 = _1;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
ADC_Read (uint8_t ADC_No)
|
|
{
|
|
uint16_t ret;
|
|
uint16_t D.15419;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) ADC_No;
|
|
switch (_1) <default: <L6> [INV], case 0: <L0> [INV], case 1: <L1> [INV], case 2: <L2> [INV], case 3: <L3> [INV], case 4: <L4> [INV], case 5: <L5> [INV]>
|
|
|
|
<bb 3> :
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.ADC0;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 4> :
|
|
<L1>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.ADC1;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 5> :
|
|
<L2>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.ADC2;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 6> :
|
|
<L3>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.ADC3;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 7> :
|
|
<L4>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.ADC4;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 8> :
|
|
<L5>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = gb.AIN_bat;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 9> :
|
|
<L6>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = 255;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15419 = ret;
|
|
return D.15419;
|
|
|
|
}
|
|
|
|
|
|
Adc_Init ()
|
|
{
|
|
uint8_t status;
|
|
uint8_t retry;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_Init (0, &AdcHwUnit_0_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.31_1 = retry;
|
|
retry = retry.31_1 + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Init failed\n", 0);
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 11>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_Init (1, &AdcHwUnit_1_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 12>; [INV]
|
|
else
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.32_2 = retry;
|
|
retry = retry.32_2 + 1;
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 9>; [INV]
|
|
else
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 13>; [INV]
|
|
else
|
|
goto <bb 14>; [INV]
|
|
|
|
<bb 13> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Init failed\n", 1);
|
|
|
|
<bb 14> :
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 17>; [INV]
|
|
|
|
<bb 15> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_Init (2, &AdcHwUnit_2_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 18>; [INV]
|
|
else
|
|
goto <bb 16>; [INV]
|
|
|
|
<bb 16> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.33_3 = retry;
|
|
retry = retry.33_3 + 1;
|
|
|
|
<bb 17> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 15>; [INV]
|
|
else
|
|
goto <bb 18>; [INV]
|
|
|
|
<bb 18> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 19>; [INV]
|
|
else
|
|
goto <bb 20>; [INV]
|
|
|
|
<bb 19> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Init failed\n", 2);
|
|
|
|
<bb 20> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (180, Adc_Sar_0_Isr, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (181, Adc_Sar_1_Isr, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (182, Adc_Sar_2_Isr, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (180);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (181);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (182);
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 23>; [INV]
|
|
|
|
<bb 21> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_DoCalibration (0);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 24>; [INV]
|
|
else
|
|
goto <bb 22>; [INV]
|
|
|
|
<bb 22> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.34_4 = retry;
|
|
retry = retry.34_4 + 1;
|
|
|
|
<bb 23> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 21>; [INV]
|
|
else
|
|
goto <bb 24>; [INV]
|
|
|
|
<bb 24> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 25>; [INV]
|
|
else
|
|
goto <bb 26>; [INV]
|
|
|
|
<bb 25> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Calibration failed\n", 0);
|
|
|
|
<bb 26> :
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 29>; [INV]
|
|
|
|
<bb 27> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_DoCalibration (1);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 30>; [INV]
|
|
else
|
|
goto <bb 28>; [INV]
|
|
|
|
<bb 28> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.35_5 = retry;
|
|
retry = retry.35_5 + 1;
|
|
|
|
<bb 29> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 27>; [INV]
|
|
else
|
|
goto <bb 30>; [INV]
|
|
|
|
<bb 30> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 31>; [INV]
|
|
else
|
|
goto <bb 32>; [INV]
|
|
|
|
<bb 31> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Calibration failed\n", 1);
|
|
|
|
<bb 32> :
|
|
# DEBUG BEGIN_STMT
|
|
retry = 0;
|
|
goto <bb 35>; [INV]
|
|
|
|
<bb 33> :
|
|
# DEBUG BEGIN_STMT
|
|
status = Adc_Sar_Ip_DoCalibration (2);
|
|
# DEBUG BEGIN_STMT
|
|
if (status == 0)
|
|
goto <bb 36>; [INV]
|
|
else
|
|
goto <bb 34>; [INV]
|
|
|
|
<bb 34> :
|
|
# DEBUG BEGIN_STMT
|
|
retry.36_6 = retry;
|
|
retry = retry.36_6 + 1;
|
|
|
|
<bb 35> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry <= 9)
|
|
goto <bb 33>; [INV]
|
|
else
|
|
goto <bb 36>; [INV]
|
|
|
|
<bb 36> :
|
|
# DEBUG BEGIN_STMT
|
|
if (retry > 9)
|
|
goto <bb 37>; [INV]
|
|
else
|
|
goto <bb 38>; [INV]
|
|
|
|
<bb 37> :
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("ADC[%d] Calibration failed\n", 2);
|
|
|
|
<bb 38> :
|
|
# DEBUG BEGIN_STMT
|
|
Adc_Sar_Ip_EnableNotifications (0, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Adc_Sar_Ip_EnableNotifications (1, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Adc_Sar_Ip_EnableNotifications (2, 1);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
led_onoff (int flag)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
if (flag == 1)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 2, 0);
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 2, 1);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.led_flag = flag;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Digital_Read (uint8_t DIN_No)
|
|
{
|
|
uint8_t ret;
|
|
uint8_t D.15396;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) DIN_No;
|
|
switch (_1) <default: <L8> [INV], case 0: <L0> [INV], case 1: <L1> [INV], case 2: <L2> [INV], case 3: <L3> [INV], case 4: <L4> [INV], case 5: <L5> [INV], case 6: <L6> [INV], case 7: <L7> [INV]>
|
|
|
|
<bb 3> :
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434694B, 8);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 4> :
|
|
<L1>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434690B, 11);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 5> :
|
|
<L2>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434706B, 1);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 6> :
|
|
<L3>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434694B, 11);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 7> :
|
|
<L4>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434692B, 4);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 8> :
|
|
<L5>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434692B, 5);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 9> :
|
|
<L6>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434692B, 8);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 10> :
|
|
<L7>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = Siul2_Dio_Ip_ReadPin (1076434692B, 10);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
<L8>:
|
|
# DEBUG BEGIN_STMT
|
|
ret = 255;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15396 = ret;
|
|
return D.15396;
|
|
|
|
}
|
|
|
|
|
|
Digital_Write (uint8_t DOUT_No, uint8_t Value)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
if (Value > 1)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
Value = 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) DOUT_No;
|
|
switch (_1) <default: <L12> [INV], case 0: <L2> [INV], case 1: <L3> [INV], case 2: <L4> [INV], case 3: <L5> [INV], case 4: <L6> [INV], case 5: <L7> [INV], case 6: <L8> [INV], case 7: <L9> [INV]>
|
|
|
|
<bb 5> :
|
|
<L2>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434690B, 0, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 6> :
|
|
<L3>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434704B, 10, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 7> :
|
|
<L4>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434690B, 12, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 8> :
|
|
<L5>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434688B, 2, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 9> :
|
|
<L6>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434690B, 13, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 10> :
|
|
<L7>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434690B, 14, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 11> :
|
|
<L8>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434690B, 15, Value);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 12> :
|
|
<L9>:
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434688B, 0, Value);
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 13> :
|
|
<L12>:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
DIN_TEST ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Siul2_Dio_Ip_ReadPin (1076434690B, 11);
|
|
din_test = _1;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
can_transmit_txring (uint8_t ch)
|
|
{
|
|
uint8_t can_ret;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) ch;
|
|
_2 = (int) ch;
|
|
_3 = CAN_ch[_2].p_rd;
|
|
_4 = (int) _3;
|
|
_5 = CAN_ch[_1].tx_ring[_4].len;
|
|
if (_5 <= 8)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = (int) ch;
|
|
tx_info[_6].data_length = 8;
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_7 = (int) ch;
|
|
_8 = (int) ch;
|
|
_9 = CAN_ch[_8].p_rd;
|
|
_10 = (int) _9;
|
|
_11 = CAN_ch[_7].tx_ring[_10].len;
|
|
if (_11 <= 16)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_12 = (int) ch;
|
|
tx_info[_12].data_length = 16;
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) ch;
|
|
_14 = (int) ch;
|
|
_15 = CAN_ch[_14].p_rd;
|
|
_16 = (int) _15;
|
|
_17 = CAN_ch[_13].tx_ring[_16].len;
|
|
if (_17 <= 24)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) ch;
|
|
tx_info[_18].data_length = 24;
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
_19 = (int) ch;
|
|
_20 = (int) ch;
|
|
_21 = CAN_ch[_20].p_rd;
|
|
_22 = (int) _21;
|
|
_23 = CAN_ch[_19].tx_ring[_22].len;
|
|
if (_23 <= 32)
|
|
goto <bb 9>; [INV]
|
|
else
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
_24 = (int) ch;
|
|
tx_info[_24].data_length = 32;
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
_25 = (int) ch;
|
|
_26 = (int) ch;
|
|
_27 = CAN_ch[_26].p_rd;
|
|
_28 = (int) _27;
|
|
_29 = CAN_ch[_25].tx_ring[_28].len;
|
|
if (_29 <= 64)
|
|
goto <bb 11>; [INV]
|
|
else
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
_30 = (int) ch;
|
|
tx_info[_30].data_length = 64;
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
_31 = (int) ch;
|
|
_32 = CAN_ch[_31].tx_mb_idx;
|
|
_33 = (int) ch;
|
|
_34 = &tx_info[_33];
|
|
_35 = (int) ch;
|
|
_36 = (int) ch;
|
|
_37 = CAN_ch[_36].p_rd;
|
|
_38 = (int) _37;
|
|
_39 = CAN_ch[_35].tx_ring[_38].id;
|
|
_40 = (int) ch;
|
|
_41 = (int) ch;
|
|
_42 = CAN_ch[_41].p_rd;
|
|
_43 = (int) _42;
|
|
_44 = &CAN_ch[_40].tx_ring[_43].buf;
|
|
can_ret = FlexCAN_Ip_Send (ch, _32, _34, _39, _44);
|
|
# DEBUG BEGIN_STMT
|
|
_45 = (int) ch;
|
|
_46 = CAN_ch[_45].tx_mb_idx;
|
|
_47 = (int) _46;
|
|
_48 = _47 + 1;
|
|
_49 = (unsigned int) _48;
|
|
_50 = _49 % 13;
|
|
_51 = (int) ch;
|
|
_52 = (unsigned char) _50;
|
|
CAN_ch[_51].tx_mb_idx = _52;
|
|
# DEBUG BEGIN_STMT
|
|
_53 = (int) can_ret;
|
|
switch (_53) <default: <L18> [INV], case 0: <L14> [INV], case 2: <L15> [INV]>
|
|
|
|
<bb 13> :
|
|
<L14>:
|
|
# DEBUG BEGIN_STMT
|
|
clear_tx_ring (ch);
|
|
# DEBUG BEGIN_STMT
|
|
_54 = (int) ch;
|
|
_55 = (int) ch;
|
|
_56 = CAN_ch[_55].p_rd;
|
|
_57 = (int) _56;
|
|
CAN_ch[_54].tx_ring[_57].xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_58 = (int) ch;
|
|
_59 = CAN_ch[_58].p_rd;
|
|
_60 = (int) _59;
|
|
_61 = _60 + 1;
|
|
_62 = _61 % 200;
|
|
_63 = (int) ch;
|
|
_64 = (short unsigned int) _62;
|
|
CAN_ch[_63].p_rd = _64;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 15>; [INV]
|
|
|
|
<bb 14> :
|
|
<L15>:
|
|
# DEBUG BEGIN_STMT
|
|
clear_tx_ring (ch);
|
|
# DEBUG BEGIN_STMT
|
|
_65 = (int) ch;
|
|
_66 = (int) ch;
|
|
_67 = CAN_ch[_66].p_rd;
|
|
_68 = (int) _67;
|
|
CAN_ch[_65].tx_ring[_68].xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_69 = (int) ch;
|
|
_70 = CAN_ch[_69].p_rd;
|
|
_71 = (int) _70;
|
|
_72 = _71 + 1;
|
|
_73 = _72 % 200;
|
|
_74 = (int) ch;
|
|
_75 = (short unsigned int) _73;
|
|
CAN_ch[_74].p_rd = _75;
|
|
# DEBUG BEGIN_STMT
|
|
vcan_send_miss_message.30_76 = vcan_send_miss_message;
|
|
_77 = vcan_send_miss_message.30_76 + 1;
|
|
vcan_send_miss_message = _77;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 15> :
|
|
<L18>:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
can_send_txring (uint8_t ch, uint32_t id, uint8_t * buf, uint8_t len)
|
|
{
|
|
uint8_t i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) ch;
|
|
_2 = tx_info[_1].data_length;
|
|
if (_2 > 64)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) ch;
|
|
_4 = gb.can[_3].bus_off;
|
|
if (_4 == 0)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (sizetype) i;
|
|
_6 = buf + _5;
|
|
_7 = (int) ch;
|
|
_8 = (int) ch;
|
|
_9 = CAN_ch[_8].p_wr;
|
|
_10 = (int) _9;
|
|
_11 = (int) i;
|
|
_12 = *_6;
|
|
CAN_ch[_7].tx_ring[_10].buf[_11] = _12;
|
|
# DEBUG BEGIN_STMT
|
|
i.29_13 = i;
|
|
i = i.29_13 + 1;
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i < len)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
clear_tx_buf (ch);
|
|
# DEBUG BEGIN_STMT
|
|
_14 = (int) ch;
|
|
_15 = (int) ch;
|
|
_16 = CAN_ch[_15].p_wr;
|
|
_17 = (int) _16;
|
|
CAN_ch[_14].tx_ring[_17].id = id;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) ch;
|
|
_19 = (int) ch;
|
|
_20 = CAN_ch[_19].p_wr;
|
|
_21 = (int) _20;
|
|
CAN_ch[_18].tx_ring[_21].len = len;
|
|
# DEBUG BEGIN_STMT
|
|
_22 = (int) ch;
|
|
_23 = (int) ch;
|
|
_24 = CAN_ch[_23].p_wr;
|
|
_25 = (int) _24;
|
|
CAN_ch[_22].tx_ring[_25].xreq = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_26 = (int) ch;
|
|
_27 = CAN_ch[_26].p_wr;
|
|
_28 = (int) _27;
|
|
_29 = _28 + 1;
|
|
_30 = _29 % 200;
|
|
_31 = (int) ch;
|
|
_32 = (short unsigned int) _30;
|
|
CAN_ch[_31].p_wr = _32;
|
|
|
|
<bb 10> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
can_tx_check ()
|
|
{
|
|
uint8_t i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) i;
|
|
_2 = (int) i;
|
|
_3 = CAN_ch[_2].p_rd;
|
|
_4 = (int) _3;
|
|
_5 = CAN_ch[_1].tx_ring[_4].xreq;
|
|
if (_5 == 1)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
can_transmit_txring (i);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
i.28_6 = i;
|
|
i = i.28_6 + 1;
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 5)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 7> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
clear_tx_ring (uint8_t ch)
|
|
{
|
|
uint8_t j;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) ch;
|
|
_2 = (int) ch;
|
|
_3 = CAN_ch[_2].p_rd;
|
|
_4 = (int) _3;
|
|
CAN_ch[_1].tx_ring[_4].len = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (int) ch;
|
|
_6 = (int) ch;
|
|
_7 = CAN_ch[_6].p_rd;
|
|
_8 = (int) _7;
|
|
CAN_ch[_5].tx_ring[_8].id = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
j = 0;
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) ch;
|
|
_10 = (int) ch;
|
|
_11 = CAN_ch[_10].p_rd;
|
|
_12 = (int) _11;
|
|
_13 = (int) j;
|
|
CAN_ch[_9].tx_ring[_12].buf[_13] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
j.27_14 = j;
|
|
j = j.27_14 + 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (j <= 31)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
clear_tx_buf (uint8_t ch)
|
|
{
|
|
uint8_t i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) ch;
|
|
CAN_ch[_1].tx.id = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) ch;
|
|
CAN_ch[_2].tx.len = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) ch;
|
|
_4 = (int) i;
|
|
CAN_ch[_3].tx.buf[_4] = 0;
|
|
# DEBUG BEGIN_STMT
|
|
i.26_5 = i;
|
|
i = i.26_5 + 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 31)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
ECU3_Data_Init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_RTRN = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_Reverse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_LTRN = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_Head = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_HBEAM = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_Hazard = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_BRAKE = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Status_Wiper = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_CE1_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_CE2_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_CE3_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_CE4_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_CE5_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_MAINSW_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Battery_Voltage = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_DRL = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.Lamp_Position = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_VCU_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal1_0x570.BCM_VCU_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.ChargingStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BCM_ChgeCon_DTD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BMS_HVOn_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.IntLckSta_OBC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.IntLckSta_BMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BMS_SOC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BMS_SOH = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.CommSta_OBC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.CommSta_VCU = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.CommSta_BMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.CommSta_LDC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.CommSta_TMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BMS_SOH_INV = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BMS_SOC_INV = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.Bms_Soc_Wrng = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.Bms_SoH_Wrng = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BCM_VCU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal2_0x580.BCM_VCU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal3_0x590.Bms_PackVolt = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal3_0x590.Bms_PackCur = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal3_0x590.Bms_PackPwr = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal3_0x590.BCM_VCU_counter3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal3_0x590.BCM_VCU_CRC3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal4_0x595.LDC_ACTL_CUR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal4_0x595.LDC_INP_VOLT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.OBC_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.BMS_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.LDC_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.BCM_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.BMS_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.LDC_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.OBC_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.BCM_VCU_counter5 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_BCM_VCU_Signal5_0x585.BCM_VCU_CRC5 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_IMU_VCU_Signal_0x020.LatAccelVal = -1.0229999542236328125e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_IMU_VCU_Signal_0x020.LongAccelVal = -1.0229999542236328125e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_IMU_VCU_Signal_0x020.YawRate = -1.63839996337890625e+2;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_IMU_VCU_Signal_0x020.IMU_VCU_counter = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_Ready = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_Controlable = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_Flt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_Interlock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_CurGearSta = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_GearStaInv = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_Derating = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_SvrFlt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_MtrTemp = -5.0e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_InvTemp = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_EstSpd = -3.2768e+4;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals1_0x300.MCU_EstTrq = -2.0e+2;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals2_0x301.FaultMessage1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_MCU_VCU_Signals2_0x301.FaultMessage2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_BrakeTorqueCommand = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_RWA_RackAngleCommand = -6.65e+2;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_Drive_ACC_Cmd = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_Vx_Command = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_VCU_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal1_0x040.RC_VCU_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_Drive_Mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_GearSelStat = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_ParkBrake_Cmd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_Emergency_Stop = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_VCU_long_Ctl_mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_Signal2_0x041.RC_VCU_ARC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_BRAKE_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_Hazard_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_HBEAM_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_Head_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_LTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_Reverse_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_RTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_Position_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Lamp_DRL_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RC_VCU_BCM_Signal_1_CH0_0x155.Wiper_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_driveSensor = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_parkSensor = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_parkLock = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_ParkRequestStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_Voltage = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_Current = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_Temperature = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_HallPosition = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_MotStallMiddle = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_MotStallUnPark = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_MotStallPark = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_MotOpen = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_MotFail = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.EPAM_State = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_CommErr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_HallSenErr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_OT_ECU = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_CANErr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_HallPaternError = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_HallTimeOut = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_DCBusUnderVoltage = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_DCBusOverVoltage = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH0_RX_EPAM_VCU_0x155.ErrEPAM_DCBusOverCurrent = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal1_0x091.ACU_Vx_Command = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal1_0x091.ACU_Drive_ACC_Cmd = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal1_0x091.ACU_BrakeTorqueCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal1_0x091.ACU_VCU_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal1_0x091.ACU_VCU_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal2_0x092.ACU_RWA_cmd_deg = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal2_0x092.ACU_RWS_cmd_deg = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal2_0x092.ACU_VCU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal2_0x092.ACU_VCU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_Drive_mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_long_Ctl_mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_EPAM_req = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_VCU_GearPos = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_Emergency_Stop = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_VCU_counter3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_VCU_Signal3_0x093.ACU_VCU_CRC3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_BRAKE_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_Hazard_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_HBEAM_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_Head_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_LTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_Reverse_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_RTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_Position_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Lamp_DRL_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Wiper_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.LDC_ACT_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.HV_ON_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.CE_ON_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.LDC_TRGT_CUR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Vcu_OperMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.Vcu_SysMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.ACU_VCU_counter = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH1_ACU_BCM_Signal_1_0x150.ACU_VCU_CRC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EstimatedVehicleSpeed = -1.494999980926513671875e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.IsControllingEcu = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.MasterCylinderPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.RoadFrictionCoefficient = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.RoadFrictionCoefficientValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.VehicleSpeedValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.EstimatedVehicleSpeed = -1.494999980926513671875e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.IsControllingEcu = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.MasterCylinderPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.RoadFrictionCoefficient = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.RoadFrictionCoefficientValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_BrakeStatus1_0x09A.VehicleSpeedValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.FrontLeftEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.FrontLeftEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.FrontRightEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.FrontRightEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.RearLeftEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.RearLeftEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.RearRightEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_PressureStatus_0x0A0.RearRightEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_RegenTcsRequest_0x082.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_RegenTcsRequest_0x082.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_RegenTcsRequest_0x082.RbcTargetRegenTorque = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_RegenTcsRequest_0x082.TcsTorqueCmd = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.AbsFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.AbsState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.BbsFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.BbsState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.CanCommunicationFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EbdFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EbdState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EpbFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EpbState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EpbTransition = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EscFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EscState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.EscYawRateThreshold = -5.00000007450580596923828125e-2;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.InternalCanCommunicationFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.RbcFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.RbcState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.RopFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.RopState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.SplitMuDetection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.SsmFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.SsmState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.TcsFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_Status_0x092.TcsState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.FrontLeftTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.FrontLeftWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.FrontRightTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.FrontRightWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.RearLeftTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.RearLeftWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.RearRightTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_TireSlipStatus_0x096.RearRightWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_UdsResponse_0x798.UdsResponse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_UdsResponse_0x798.UdsResponse_MSB = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_UdsResponse_0x798.UdsResponse_LSB = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontLeftWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontLeftWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontLeftWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontLeftWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontRightWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontRightWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontRightWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.FrontRightWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearLeftWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearLeftWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearLeftWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearLeftWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearRightWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearRightWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearRightWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_IDB_WheelStatus_0x08C.RearRightWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.EcuPowerMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.MaxMotorOutput = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.MaxMotorOutputValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.RackAngleSpeedFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.RackAngleSpeedFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.SysInfo = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status1_0x072.WarningLamp = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.RackAngleFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.RackAngleFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.RackForceFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status2_0x073.RackForceFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.PolFault = 1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.PolLimiterFlag = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.PolStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.PolValue = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.SysBatteryVoltage = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH2_RWA_Status3_0x0AA.SysIqCurrent = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.EstimatedVehicleSpeed = -1.494999980926513671875e+1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.IsControllingEcu = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.MasterCylinderPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.RoadFrictionCoefficient = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.RoadFrictionCoefficientValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus1_0x09B.VehicleSpeedValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.BrakeFluidState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.FrontLeftBrakePadState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.FrontRightBrakePadState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.MotorTemperatureWarning = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Reserved3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Reserved4 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Reserved5 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_BrakeStatus2_0x0CA.Reserved6 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.FrontLeftEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.FrontLeftEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.FrontRightEstimatedPressure = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_PressureStatus_0x0A1.FrontRightEstimatedPressureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.EcuPowerMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.MaxMotorOutput = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.MaxMotorOutputValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.RackAngleSpeedFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.RackAngleSpeedFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.SysInfo = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status1_0x072.WarningLamp = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.RackAngleFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.RackAngleFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.RackForceFbk = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status2_0x073.RackForceFbkValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.PolFault = 1;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.PolLimiterFlag = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.PolStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.PolValue = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.SysBatteryVoltage = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RWA_Status3_0x0AA.SysIqCurrent = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.FrontLeftTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.FrontLeftWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.FrontRightTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.FrontRightWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.RearLeftTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.RearLeftWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.RearRightTireSlipRatio = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_TireSlipStatus_0x097.RearRightWheelSlipStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontLeftWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontLeftWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontLeftWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontLeftWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontRightWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontRightWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontRightWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.FrontRightWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearLeftWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearLeftWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearLeftWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearLeftWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearRightWheelDirection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearRightWheelPulse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearRightWheelPulseValidity = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_WheelStatus_0x08D.RearRightWssFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.AbsFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.AbsState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.BbsFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.BbsState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.CanCommunicationFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EpbFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EpbState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EpbTransition = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EscFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EscState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.EscYawRateThreshold = -5.00000007450580596923828125e-2;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.InternalCanCommunicationFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.SplitMuDetSsmFaultection = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.SsmFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_Status_0x093.SsmState = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH3_RCU_UdsResponse_0x799.UdsResponse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH4_RWS_VCU_Rack_AngleFbk_0x073.RWS_RackAngleFbk1 = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH4_RWS_VCU_stat_Signal_0x072.RWS_EcuStatus1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH4_RWS_VCU_stat_Signal_0x072.RWS_RackAngleSpeedFbk1 = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH5_RWS_VCU_Rack_AngleFbk_0x073.RWS_RackAngleFbk2 = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH5_RWS_VCU_stat_Signal_0x072.RWS_EcuStatus2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.RX.CH5_RWS_VCU_stat_Signal_0x072.RWS_RackAngleSpeedFbk2 = 0.0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_RackAngleFbk1_0x050.RWA_RackAngleFbk1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_RackAngleFbk1_0x050.RWA_RackAngleSpeedFbk1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_RackAngleFbk1_0x050.RWA_VCU_RC_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_RackAngleFbk1_0x050.RWA_VCU_RC_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_RackAngleFbk1_0x050.CAR_ARC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x051.RWA_RackAngleFbk2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x051.RWA_RackAngleSpeedFbk2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x051.RWA_VCU_RC_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x051.RWA_VCU_RC_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWS_VCU_RC_Signal1_0x060.RWS_RackAngleFbk1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWS_VCU_RC_Signal1_0x060.RWS_RackAngleSpeedFbk1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWS_VCU_RC_Signal1_0x060.RWS_VCU_RC_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWS_VCU_RC_Signal1_0x060.RWS_VCU_RC_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x061.RWS_RackAngleFbk2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x061.RWS_RackAngleSpeedFbk2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x061.RWS_VCU_RC_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_RWA_VCU_RC_Signal2_0x061.RWS_VCU_RC_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_BRAKE_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_Hazard_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_HBEAM_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_Head_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_LTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_Reverse_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_RTRN_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_Position_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Lamp_DRL_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Wiper_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.LDC_ACT_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.HV_ON_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.CE_ON_CMD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.LDC_TRGT_CUR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Vcu_OperMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.Vcu_SysMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.VCU_BCM_counter = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_BCM_Signal_1_0x150.VCU_BCM_CRC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_TorqueContol = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_Ready = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_ControlMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_PwrEnable = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_GearCmd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_MtrDir = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_BmsFlt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_BmsHvSt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_PosTrqLimit = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_NegTrqLimit = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_MCU_Signals1_0x250.VCU_TrqCmd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_MCU_EstTrq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_RWA_Rack_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_Brk_Pressure_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_Vx_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_RC_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x010.VCU_RC_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_RC_BMS_SOC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_RC_long_Ctl_mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_RC_Emergency_Stop = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_GearSelStat = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_Drive_Mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_ParkBrake_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_Acc_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_VCU_RC_Signals1_0x011.VCU_Acc_Limit = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_SW_VER_0x100.YEAR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_SW_VER_0x100.Month = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_SW_VER_0x100.Day = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_SW_VER_0x100.Ver = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_SW_VER_0x100.CAR_NUM = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_MCU_MtrTemp = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_MCU_InvTemp = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_Bms_PackCur = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_Battery_Voltage = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_LDC_ACTL_VOLT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_ChargingStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH0_CAR_STAT_CH0_0x012.CAR_BMS_HVOn_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_RTRN = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_Reverse = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_LTRN = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_Head = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_HBEAM = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_Hazard = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Lamp_BRAKE = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Status_Wiper = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_CE1_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_CE2_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_CE3_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_CE4_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_CE5_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.BCM_MAINSW_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal1_0x570.Battery_Voltage = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.ChargingStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BCM_ChgeCon_DTD = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BMS_HVOn_STA = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.IntLckSta_OBC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.IntLckSta_BMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BMS_SOC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BMS_SOH = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.CommSta_OBC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.CommSta_VCU = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.CommSta_BMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.CommSta_LDC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.CommSta_TMS = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BMS_SOH_INV = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BMS_SOC_INV = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.Bms_Soc_Wrng = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.Bms_SoH_Wrng = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BCM_VCU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal2_0x580.BCM_VCU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal3_0x590.Bms_PackVolt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal3_0x590.Bms_PackCur = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal3_0x590.Bms_PackPwr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal3_0x590.BCM_VCU_counter3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal3_0x590.BCM_VCU_CRC3 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal4_0x595.LDC_ACTL_CUR = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal4_0x595.LDC_INP_VOLT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.OBC_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.BMS_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.LDC_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.BCM_FltSta = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.BMS_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.LDC_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.OBC_TEMP_FAULT = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.BCM_VCU_counter5 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_BCM_VCU_ACU_Signal5_0x585.BCM_VCU_CRC5 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal1_0x050.RWA_RackAngleFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal1_0x050.RWA_RackAngleSpeedFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal1_0x050.RWA_VCU_ACU_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal1_0x050.RWA_VCU_ACU_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal2_0x051.RWA_RackAngleFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal2_0x051.RWA_RackAngleSpeedFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal2_0x051.RWA_VCU_ACU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWA_VCU_ACU_Signal2_0x051.RWA_VCU_ACU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal1_0x060.RWS_RackAngleFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal1_0x060.RWS_RackAngleSpeedFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal1_0x060.RWS_VCU_ACU_counter1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal1_0x060.RWS_VCU_ACU_CRC1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal2_0x061.RWS_RackAngleFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal2_0x061.RWS_RackAngleSpeedFbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal2_0x061.RWS_VCU_ACU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_RWS_VCU_ACU_Signal2_0x061.RWS_VCU_ACU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_MCU_EstTrq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_RWA_Rack_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_Brk_Pressure_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_RC_BMS_SOC = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_long_Ctl_mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_GearPos = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_ParkBrake_Fbk = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal1_0x013.VCU_ACU_Emergency_Stop = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.RWA_Flt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.RWS_Flt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.IDB_Flt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.MCU_Flt = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.Drive_Mode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.VCU_IGN_SIG = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.VCU_ACU_counter2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH1_VCU_ACU_Signal2_0x014.VCU_ACU_CRC2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.BrakeHoldRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.BrakeTorqueCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.DriveTorqueCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.DriveTorqueCommandValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.EscActivation = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.GearPosition = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.ParkBrakeRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.PowertrainMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.RbcActivation = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.Reserved1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.Reserved2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.RopActivation = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_BrakeCommand_0x064.TcsActivation = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.LateralAcceleration = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.LateralAccelerationValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.LongitudinalAcceleration = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.LongitudinalAccelerationValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.VehicleSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.VehicleSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.VehicleYawRate = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IMU_0x070.VehicleYawRateValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_StartupCommand_0x032.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_StartupCommand_0x032.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_StartupCommand_0x032.WakeUpCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_IDB_UdsRequest_0x796.UdsRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.ActualMotorTorque = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.ActualMotorTorqueValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.MaxAvailableRegenTorque = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.MaxAvailableRegenTorqueValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RegenCommand_0x06A.TractionMotorFault = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_RackCommand_0x040.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_RackCommand_0x040.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_RackCommand_0x040.RackAngleCmd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_RackCommand_0x040.RackAngleCmdValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_Sister_0x350.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_Sister_0x350.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_Sister_0x350.EcuPowerMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_Sister_0x350.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_Sister_0x350.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_StartupCommand_0x310.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_StartupCommand_0x310.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_StartupCommand_0x310.ModeCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_RWA_StartupCommand_0x310.WakeUpCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.EnvironmentTemperature = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.EnvironmentTemperatureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampDay = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampHour = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampMinute = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampMonth = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampSecond = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_BSC_VehicleEnvironment_0x384.TimestampYear = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.FrontLeftWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.FrontLeftWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.FrontRightWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.FrontRightWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.RearLeftWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.RearLeftWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.RearRightWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH2_IDB_WheelSpeedStatus_0x088.RearRightWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.LateralAcceleration = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.LateralAccelerationValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.LongitudinalAcceleration = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.LongitudinalAccelerationValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.VehicleSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.VehicleSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.VehicleYawRate = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_IMU_0x071.VehicleYawRateValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.BrakeHoldRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.BrakeTorqueCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.EscActivation = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.GearPosition = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.ParkBrakeRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.PowertrainMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.Reserved1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_BrakeCommand_0x065.Reserved2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_RackCommand_0x040.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_RackCommand_0x040.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_RackCommand_0x040.RackAngleCmd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_RackCommand_0x040.RackAngleCmdValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_Sister_0x350.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_Sister_0x350.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_Sister_0x350.EcuPowerMode = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_Sister_0x350.EcuRole = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_Sister_0x350.EcuStatus = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_StartupCommand_0x310.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_StartupCommand_0x310.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_StartupCommand_0x310.ModeCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RWA_StartupCommand_0x310.WakeUpCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_StartupCommand_0x033.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_StartupCommand_0x033.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_StartupCommand_0x033.WakeUpCommand = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_RCU_UdsRequest_0x797.UdsRequest = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.EnvironmentTemperature = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.EnvironmentTemperatureValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampDay = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampHour = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampMinute = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampMonth = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampSecond = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_BSC_VehicleEnvironment_0x385.TimestampYear = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.FrontLeftWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.FrontLeftWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.FrontRightWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.FrontRightWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.RearLeftWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.RearLeftWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.RearRightWheelSpeed = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH3_RCU_WheelSpeedStatus_0x089.RearRightWheelSpeedValid = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Rack_Cmd_0x040.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Rack_Cmd_0x040.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Rack_Cmd_0x040.RackAngleCmd1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Rack_Cmd_0x040.RackAngleCmdValid1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Sister_0x350.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Sister_0x350.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Sister_0x350.EcuPowerMode1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Sister_0x350.EcuStatus1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_Sister_0x350.EcuRole1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_StartupCommand_0x310.RWS_ModeCommand1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH4_VCU_RWS_StartupCommand_0x310.RWS_WakeUpCommand1 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_Rack_Cmd_0x040.Arc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_Rack_Cmd_0x040.Crc = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_Rack_Cmd_0x040.RackAngleCmd2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_Rack_Cmd_0x040.RackAngleCmdValid2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_StartupCommand_0x310.RWS_ModeCommand2 = 0;
|
|
# DEBUG BEGIN_STMT
|
|
ECU3.TX.CH5_VCU_RWS_StartupCommand_0x310.RWS_WakeUpCommand2 = 0;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Can_Init_ECU3 (int ch)
|
|
{
|
|
uint8_t i;
|
|
uint8_t i;
|
|
uint8_t i;
|
|
uint8_t i;
|
|
uint8_t i;
|
|
uint8_t i;
|
|
uint8_t ret;
|
|
uint8_t idx;
|
|
int D.15369;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (109);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (109, CAN0_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (110);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (110, CAN0_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 8, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 5, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (0, &FlexCAN_State0, &FlexCAN_Config0);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetRxMaskType_Privileged (0, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetRxIndividualMask_Privileged (0, 13, 0);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (0);
|
|
# DEBUG BEGIN_STMT
|
|
_1 = &rx_info[ch];
|
|
FlexCAN_Ip_ConfigRxMb (0, 13, _1, 0);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Receive (0, 13, &can0_rxData[13], 0);
|
|
# DEBUG BEGIN_STMT
|
|
ECU3_Data_Init ();
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (unsigned char) ch;
|
|
clear_tx_buf (_2);
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 1)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (113);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (113, CAN1_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (114);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (114, CAN1_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434700B, 7, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434702B, 2, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (1, &FlexCAN_State1, &FlexCAN_Config1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (1);
|
|
# DEBUG BEGIN_STMT
|
|
idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = idx + 13;
|
|
_4 = &rx_info[ch];
|
|
_5 = (int) i;
|
|
_6 = g_messageObjectConf_ECU3_1ch_RX[_5].messageId;
|
|
_7 = (long unsigned int) _6;
|
|
FlexCAN_Ip_ConfigRxMb (1, _3, _4, _7);
|
|
# DEBUG BEGIN_STMT
|
|
_8 = idx + 13;
|
|
_9 = (unsigned int) idx;
|
|
_10 = _9 + 13;
|
|
_11 = &can1_rxData[_10];
|
|
FlexCAN_Ip_Receive (1, _8, _11, 0);
|
|
# DEBUG BEGIN_STMT
|
|
idx.15_12 = idx;
|
|
idx = idx.15_12 + 1;
|
|
# DEBUG BEGIN_STMT
|
|
i.16_13 = i;
|
|
i = i.16_13 + 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 3)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 2)
|
|
goto <bb 10>; [INV]
|
|
else
|
|
goto <bb 14>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (116);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (116, CAN2_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (117);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (117, CAN2_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434702B, 4, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434700B, 6, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (2, &FlexCAN_State2, &FlexCAN_Config2);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (2);
|
|
# DEBUG BEGIN_STMT
|
|
idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
_14 = idx + 13;
|
|
_15 = &rx_info[ch];
|
|
_16 = (int) i;
|
|
_17 = g_messageObjectConf_ECU3_2ch_RX[_16].messageId;
|
|
_18 = (long unsigned int) _17;
|
|
FlexCAN_Ip_ConfigRxMb (2, _14, _15, _18);
|
|
# DEBUG BEGIN_STMT
|
|
_19 = idx + 13;
|
|
_20 = (unsigned int) idx;
|
|
_21 = _20 + 13;
|
|
_22 = &can2_rxData[_21];
|
|
FlexCAN_Ip_Receive (2, _19, _22, 0);
|
|
# DEBUG BEGIN_STMT
|
|
idx.17_23 = idx;
|
|
idx = idx.17_23 + 1;
|
|
# DEBUG BEGIN_STMT
|
|
i.18_24 = i;
|
|
i = i.18_24 + 1;
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 10)
|
|
goto <bb 11>; [INV]
|
|
else
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 13> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 14> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 3)
|
|
goto <bb 15>; [INV]
|
|
else
|
|
goto <bb 19>; [INV]
|
|
|
|
<bb 15> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (119);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (119, CAN3_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (120);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (120, CAN3_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434694B, 0, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434694B, 1, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (3, &FlexCAN_State3, &FlexCAN_Config3);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (3);
|
|
# DEBUG BEGIN_STMT
|
|
idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 17>; [INV]
|
|
|
|
<bb 16> :
|
|
# DEBUG BEGIN_STMT
|
|
_25 = idx + 13;
|
|
_26 = &rx_info[ch];
|
|
_27 = (int) i;
|
|
_28 = g_messageObjectConf_ECU3_3ch_RX[_27].messageId;
|
|
_29 = (long unsigned int) _28;
|
|
FlexCAN_Ip_ConfigRxMb (3, _25, _26, _29);
|
|
# DEBUG BEGIN_STMT
|
|
_30 = idx + 13;
|
|
_31 = (unsigned int) idx;
|
|
_32 = _31 + 13;
|
|
_33 = &can3_rxData[_32];
|
|
FlexCAN_Ip_Receive (3, _30, _33, 0);
|
|
# DEBUG BEGIN_STMT
|
|
idx.19_34 = idx;
|
|
idx = idx.19_34 + 1;
|
|
# DEBUG BEGIN_STMT
|
|
i.20_35 = i;
|
|
i = i.20_35 + 1;
|
|
|
|
<bb 17> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 9)
|
|
goto <bb 16>; [INV]
|
|
else
|
|
goto <bb 18>; [INV]
|
|
|
|
<bb 18> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 19> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 4)
|
|
goto <bb 20>; [INV]
|
|
else
|
|
goto <bb 24>; [INV]
|
|
|
|
<bb 20> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (121);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (121, CAN4_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (122);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (122, CAN4_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 10, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434696B, 9, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (4, &FlexCAN_State4, &FlexCAN_Config_500k);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (4);
|
|
# DEBUG BEGIN_STMT
|
|
setupCanTJA1153 (ch, 1076434696B, 9);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (4, &FlexCAN_State4, &FlexCAN_Config4);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (4);
|
|
# DEBUG BEGIN_STMT
|
|
idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 22>; [INV]
|
|
|
|
<bb 21> :
|
|
# DEBUG BEGIN_STMT
|
|
_36 = idx + 13;
|
|
_37 = &rx_info[ch];
|
|
_38 = (int) i;
|
|
_39 = g_messageObjectConf_ECU3_4ch_RX[_38].messageId;
|
|
_40 = (long unsigned int) _39;
|
|
FlexCAN_Ip_ConfigRxMb (4, _36, _37, _40);
|
|
# DEBUG BEGIN_STMT
|
|
_41 = idx + 13;
|
|
_42 = (unsigned int) idx;
|
|
_43 = _42 + 13;
|
|
_44 = &can4_rxData[_43];
|
|
FlexCAN_Ip_Receive (4, _41, _44, 0);
|
|
# DEBUG BEGIN_STMT
|
|
idx.21_45 = idx;
|
|
idx = idx.21_45 + 1;
|
|
# DEBUG BEGIN_STMT
|
|
i.22_46 = i;
|
|
i = i.22_46 + 1;
|
|
|
|
<bb 22> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 1)
|
|
goto <bb 21>; [INV]
|
|
else
|
|
goto <bb 23>; [INV]
|
|
|
|
<bb 23> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 24> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ch == 5)
|
|
goto <bb 25>; [INV]
|
|
else
|
|
goto <bb 29>; [INV]
|
|
|
|
<bb 25> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (123);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (123, CAN5_ORED_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (124);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (124, CAN5_ORED_0_31_MB_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434700B, 14, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Siul2_Dio_Ip_WritePin (1076434704B, 1, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (5, &FlexCAN_State5, &FlexCAN_Config_500k);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (5);
|
|
# DEBUG BEGIN_STMT
|
|
setupCanTJA1153 (ch, 1076434704B, 1);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Init_Privileged (5, &FlexCAN_State5, &FlexCAN_Config5);
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_SetStartMode_Privileged (5);
|
|
# DEBUG BEGIN_STMT
|
|
idx = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 26> :
|
|
# DEBUG BEGIN_STMT
|
|
_47 = idx + 13;
|
|
_48 = &rx_info[ch];
|
|
_49 = (int) i;
|
|
_50 = g_messageObjectConf_ECU3_5ch_RX[_49].messageId;
|
|
_51 = (long unsigned int) _50;
|
|
FlexCAN_Ip_ConfigRxMb (5, _47, _48, _51);
|
|
# DEBUG BEGIN_STMT
|
|
_52 = idx + 13;
|
|
_53 = (unsigned int) idx;
|
|
_54 = _53 + 13;
|
|
_55 = &can5_rxData[_54];
|
|
FlexCAN_Ip_Receive (5, _52, _55, 0);
|
|
# DEBUG BEGIN_STMT
|
|
idx.23_56 = idx;
|
|
idx = idx.23_56 + 1;
|
|
# DEBUG BEGIN_STMT
|
|
i.24_57 = i;
|
|
i = i.24_57 + 1;
|
|
|
|
<bb 27> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 1)
|
|
goto <bb 26>; [INV]
|
|
else
|
|
goto <bb 28>; [INV]
|
|
|
|
<bb 28> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].bus_off = 1;
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[ch].error = 1;
|
|
|
|
<bb 29> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[ch].p_rd = 0;
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[ch].p_wr = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 31>; [INV]
|
|
|
|
<bb 30> :
|
|
# DEBUG BEGIN_STMT
|
|
_58 = (int) i;
|
|
CAN_ch[ch].tx_ring[_58].xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
i.25_59 = i;
|
|
i = i.25_59 + 1;
|
|
|
|
<bb 31> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 199)
|
|
goto <bb 30>; [INV]
|
|
else
|
|
goto <bb 32>; [INV]
|
|
|
|
<bb 32> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15369 = 0;
|
|
return D.15369;
|
|
|
|
}
|
|
|
|
|
|
can_main_ECU3 ()
|
|
{
|
|
uint8_t j;
|
|
u8 ch_idx;
|
|
u32 idx;
|
|
u8 i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
j = 0;
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned int) j;
|
|
_2 = get_can_data (_1);
|
|
if (_2 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) j;
|
|
idx = gb.can[_3].head;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) j;
|
|
_5 = (int) i;
|
|
_6 = (int) j;
|
|
_7 = (int) i;
|
|
_8 = gb.can[_4].data[idx][_5];
|
|
CAN_ch[_6].rx.buf[_7] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i.11_9 = i;
|
|
i = i.11_9 + 1;
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_10 = (unsigned int) i;
|
|
_11 = (int) j;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (_10 < _12)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) j;
|
|
_14 = gb.can[_13].len[idx];
|
|
_15 = (int) j;
|
|
_16 = (unsigned char) _14;
|
|
CAN_ch[_15].rx.len = _16;
|
|
# DEBUG BEGIN_STMT
|
|
_17 = (int) j;
|
|
_18 = (int) j;
|
|
_19 = gb.can[_17].msgId[idx];
|
|
CAN_ch[_18].rx.id = _19;
|
|
# DEBUG BEGIN_STMT
|
|
_20 = (int) j;
|
|
CAN_ch[_20].rx.xreq = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_21 = (int) j;
|
|
_22 = gb.can[_21].head;
|
|
_23 = _22 + 1;
|
|
_24 = (int) j;
|
|
_25 = _23 % 100;
|
|
gb.can[_24].head = _25;
|
|
|
|
<bb 8> :
|
|
# DEBUG BEGIN_STMT
|
|
j.12_26 = j;
|
|
j = j.12_26 + 1;
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
if (j <= 5)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 10>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
_27 = CAN_ch[0].rx.xreq;
|
|
if (_27 == 1)
|
|
goto <bb 11>; [INV]
|
|
else
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[0].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_28 = CAN_ch[0].rx.id;
|
|
switch (_28) <default: <L24> [INV], case 32: <L14> [INV], case 64: <L17> [INV], case 65: <L18> [INV], case 341: <L22> [INV], case 372: <L19> [INV], case 376: <L20> [INV], case 380: <L21> [INV], case 545: <L23> [INV], case 768: <L15> [INV], case 769: <L16> [INV], case 1392: <L9> [INV], case 1408: <L10> [INV], case 1413: <L13> [INV], case 1424: <L11> [INV], case 1429: <L12> [INV]>
|
|
|
|
<bb 12> :
|
|
<L9>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_BCM_VCU_Signal1_CH0_0x570 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 13> :
|
|
<L10>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_BCM_VCU_Signal2_CH0_0x580 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 14> :
|
|
<L11>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_BCM_VCU_Signal3_CH0_0x590 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 15> :
|
|
<L12>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_BCM_VCU_Signal4_CH0_0x595 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 16> :
|
|
<L13>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_BCM_VCU_Signal5_CH0_0x585 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 17> :
|
|
<L14>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IMU_VCU_Signal_CH0_0x020 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 18> :
|
|
<L15>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_MCU_VCU_Signals1_CH0_0x300 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 19> :
|
|
<L16>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_MCU_VCU_Signals2_CH0_0x301 ();
|
|
# DEBUG BEGIN_STMT
|
|
GV_CH0_0x301_CNT.13_29 = GV_CH0_0x301_CNT;
|
|
GV_CH0_0x301_CNT.14_30 = GV_CH0_0x301_CNT.13_29;
|
|
_31 = GV_CH0_0x301_CNT.14_30 + 1;
|
|
GV_CH0_0x301_CNT = _31;
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 20> :
|
|
<L17>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RC_VCU_Signal1_CH0_0x040 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 21> :
|
|
<L18>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RC_VCU_Signal2_CH0_0x041 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 22> :
|
|
<L19>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IMU_TX1_CH0_0x174 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 23> :
|
|
<L20>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IMU_TX1_CH0_0x178 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 24> :
|
|
<L21>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IMU_TX1_CH0_0x17C ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 25> :
|
|
<L22>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RC_VCU_BCM_Signal_1_CH0_0x155 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 27>; [INV]
|
|
|
|
<bb 26> :
|
|
<L23>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_EPAM_VCU_CH0_0x221 ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 27> :
|
|
<L24>:
|
|
# DEBUG BEGIN_STMT
|
|
_32 = CAN_ch[1].rx.xreq;
|
|
if (_32 == 1)
|
|
goto <bb 28>; [INV]
|
|
else
|
|
goto <bb 33>; [INV]
|
|
|
|
<bb 28> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[1].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_33 = CAN_ch[1].rx.id;
|
|
switch (_33) <default: <L32> [INV], case 145: <L28> [INV], case 146: <L29> [INV], case 147: <L30> [INV], case 336: <L31> [INV]>
|
|
|
|
<bb 29> :
|
|
<L28>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_ACU_VCU_Signal1_CH1_0x091 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 33>; [INV]
|
|
|
|
<bb 30> :
|
|
<L29>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_ACU_VCU_Signal2_CH1_0x092 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 33>; [INV]
|
|
|
|
<bb 31> :
|
|
<L30>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_ACU_VCU_Signal3_CH1_0x093 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 33>; [INV]
|
|
|
|
<bb 32> :
|
|
<L31>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_ACU_BCM_Signal_1_CH1_0x150 ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 33> :
|
|
<L32>:
|
|
# DEBUG BEGIN_STMT
|
|
_34 = CAN_ch[2].rx.xreq;
|
|
if (_34 == 1)
|
|
goto <bb 34>; [INV]
|
|
else
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 34> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[2].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_35 = CAN_ch[2].rx.id;
|
|
switch (_35) <default: <L47> [INV], case 114: <L44> [INV], case 115: <L45> [INV], case 130: <L39> [INV], case 140: <L43> [INV], case 146: <L40> [INV], case 150: <L41> [INV], case 154: <L36> [INV], case 160: <L38> [INV], case 170: <L46> [INV], case 200: <L37> [INV], case 1944: <L42> [INV]>
|
|
|
|
<bb 35> :
|
|
<L36>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_BrakeStatus1_CH2_0x09A ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 36> :
|
|
<L37>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_BrakeStatus2_CH2_0x0C8 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 37> :
|
|
<L38>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_PressureStatus_CH2_0x0A0 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 38> :
|
|
<L39>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_RegenTcsRequest_CH2_0x082 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 39> :
|
|
<L40>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_Status_CH2_0x092 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 40> :
|
|
<L41>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_TireSlipStatus_CH2_0x096 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 41> :
|
|
<L42>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_UdsResponse_CH2_0x798 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 42> :
|
|
<L43>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_IDB_WheelStatus_CH2_0x08C ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 43> :
|
|
<L44>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status1_CH2_0x072 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 44> :
|
|
<L45>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status2_CH2_0x073 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 46>; [INV]
|
|
|
|
<bb 45> :
|
|
<L46>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status3_CH2_0x0AA ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 46> :
|
|
<L47>:
|
|
# DEBUG BEGIN_STMT
|
|
_36 = CAN_ch[3].rx.xreq;
|
|
if (_36 == 1)
|
|
goto <bb 47>; [INV]
|
|
else
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 47> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[3].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_37 = CAN_ch[3].rx.id;
|
|
switch (_37) <default: <L61> [INV], case 114: <L54> [INV], case 115: <L55> [INV], case 141: <L58> [INV], case 147: <L59> [INV], case 151: <L57> [INV], case 155: <L51> [INV], case 161: <L53> [INV], case 170: <L56> [INV], case 201: <L52> [INV], case 1945: <L60> [INV]>
|
|
|
|
<bb 48> :
|
|
<L51>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_BrakeStatus1_CH3_0x09B ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 49> :
|
|
<L52>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_BrakeStatus2_CH3_0x0C9 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 50> :
|
|
<L53>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_PressureStatus_CH3_0x0A1 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 51> :
|
|
<L54>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status1_CH3_0x072 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 52> :
|
|
<L55>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status2_CH3_0x073 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 53> :
|
|
<L56>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWA_Status3_CH3_0x0AA ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 54> :
|
|
<L57>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_TireSlipStatus_CH3_0x097 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 55> :
|
|
<L58>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_WheelStatus_CH3_0x08D ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 56> :
|
|
<L59>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_Status_CH3_0x093 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 58>; [INV]
|
|
|
|
<bb 57> :
|
|
<L60>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RCU_UdsResponse_CH3_0x799 ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 58> :
|
|
<L61>:
|
|
# DEBUG BEGIN_STMT
|
|
_38 = CAN_ch[4].rx.xreq;
|
|
if (_38 == 1)
|
|
goto <bb 59>; [INV]
|
|
else
|
|
goto <bb 62>; [INV]
|
|
|
|
<bb 59> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[4].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_39 = CAN_ch[4].rx.id;
|
|
switch (_39) <default: <L67> [INV], case 114: <L66> [INV], case 115: <L65> [INV]>
|
|
|
|
<bb 60> :
|
|
<L65>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWS_VCU_Rack_AngleFbk_CH4_0x073 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 62>; [INV]
|
|
|
|
<bb 61> :
|
|
<L66>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWS_VCU_stat_Signal_CH4_0x072 ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 62> :
|
|
<L67>:
|
|
# DEBUG BEGIN_STMT
|
|
_40 = CAN_ch[5].rx.xreq;
|
|
if (_40 == 1)
|
|
goto <bb 63>; [INV]
|
|
else
|
|
goto <bb 66>; [INV]
|
|
|
|
<bb 63> :
|
|
# DEBUG BEGIN_STMT
|
|
CAN_ch[5].rx.xreq = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_41 = CAN_ch[5].rx.id;
|
|
switch (_41) <default: <L73> [INV], case 114: <L72> [INV], case 115: <L71> [INV]>
|
|
|
|
<bb 64> :
|
|
<L71>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWS_VCU_Rack_AngleFbk_CH5_0x073 ();
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 66>; [INV]
|
|
|
|
<bb 65> :
|
|
<L72>:
|
|
# DEBUG BEGIN_STMT
|
|
Receive_RWS_VCU_stat_Signal_CH5_0x072 ();
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 66> :
|
|
<L73>:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
get_can_data (u32 ch)
|
|
{
|
|
int D.15335;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.can[ch].head;
|
|
_2 = gb.can[ch].tail;
|
|
if (_1 == _2)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15335 = 1;
|
|
// predicted unlikely by early return (on trees) predictor.
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
D.15335 = 0;
|
|
|
|
<bb 5> :
|
|
return D.15335;
|
|
|
|
}
|
|
|
|
|
|
CAN5_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) instance;
|
|
gb.can[_1].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) eventType;
|
|
debug_printf ("CAN5 bus off detected : %d\n", _2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
_4 = gb.can[_3].bus_off_callback;
|
|
if (_4 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (int) instance;
|
|
_6 = gb.can[_5].bus_off_callback;
|
|
_7 = (int) instance;
|
|
_8 = gb.can[_7].param;
|
|
_6 (_8);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = gb.can[_9].error;
|
|
if (_10 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
gb.can[_11].error = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = (int) eventType;
|
|
debug_printf ("CAN5-BUS error detected : %d\n\r", _12);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN5_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can5_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (5, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can5_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can5_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can5_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN4_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) instance;
|
|
gb.can[_1].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) eventType;
|
|
debug_printf ("CAN4 bus off detected : %d\n", _2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
_4 = gb.can[_3].bus_off_callback;
|
|
if (_4 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (int) instance;
|
|
_6 = gb.can[_5].bus_off_callback;
|
|
_7 = (int) instance;
|
|
_8 = gb.can[_7].param;
|
|
_6 (_8);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = gb.can[_9].error;
|
|
if (_10 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
gb.can[_11].error = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = (int) eventType;
|
|
debug_printf ("CAN4-BUS error detected : %d\n\r", _12);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN4_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can4_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (4, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can4_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can4_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can4_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN3_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) instance;
|
|
gb.can[_1].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = (int) eventType;
|
|
debug_printf ("CAN3 bus off detected : %d\n", _2);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
_4 = gb.can[_3].bus_off_callback;
|
|
if (_4 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (int) instance;
|
|
_6 = gb.can[_5].bus_off_callback;
|
|
_7 = (int) instance;
|
|
_8 = gb.can[_7].param;
|
|
_6 (_8);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = gb.can[_9].error;
|
|
if (_10 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
gb.can[_11].error = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_12 = (int) eventType;
|
|
debug_printf ("CAN3-BUS error detected : %d\n\r", _12);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN3_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can3_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (3, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can3_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can3_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can3_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN2_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[2].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) eventType;
|
|
debug_printf ("CAN2 bus off detected : %d\n", _1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = gb.can[2].bus_off_callback;
|
|
if (_2 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.can[2].bus_off_callback;
|
|
_4 = gb.can[2].param;
|
|
_3 (_4);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = gb.can[2].error;
|
|
if (_5 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[2].error = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = (int) eventType;
|
|
debug_printf ("CAN2-BUS error detected : %d\n", _6);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN2_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can2_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (2, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can2_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can2_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can2_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN1_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[1].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) eventType;
|
|
debug_printf ("CAN1 bus off detected : %d\n", _1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = gb.can[1].bus_off_callback;
|
|
if (_2 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.can[1].bus_off_callback;
|
|
_4 = gb.can[1].param;
|
|
_3 (_4);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = gb.can[1].error;
|
|
if (_5 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[1].error = 0;
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN1_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can1_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (1, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can1_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can1_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can1_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN0_ErrCallback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t u32ErrStatus, const struct FlexCANState * driverState)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 11)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[0].bus_off = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (int) eventType;
|
|
debug_printf ("CAN0 bus off detected : %d\n", _1);
|
|
# DEBUG BEGIN_STMT
|
|
_2 = gb.can[0].bus_off_callback;
|
|
if (_2 != 0B)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = gb.can[0].bus_off_callback;
|
|
_4 = gb.can[0].param;
|
|
_3 (_4);
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
FlexCAN_Ip_Deinit_Privileged (instance);
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_5 = gb.can[0].error;
|
|
if (_5 != 0)
|
|
goto <bb 7>; [INV]
|
|
else
|
|
goto <bb 8>; [INV]
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.can[0].error = 0;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = (int) eventType;
|
|
debug_printf ("CAN0-BUS error detected : %d\n\r", _6);
|
|
|
|
<bb 8> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
CAN0_Callback (uint8_t instance, Flexcan_Ip_EventType eventType, uint32_t buffIdx, const struct FlexCANState * driverState)
|
|
{
|
|
u32 i;
|
|
u32 idx;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (eventType == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (unsigned char) buffIdx;
|
|
_2 = &can0_rxData[buffIdx];
|
|
FlexCAN_Ip_Receive (0, _1, _2, 0);
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) instance;
|
|
idx = gb.can[_3].tail;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) instance;
|
|
_5 = can0_rxData[buffIdx].msgId;
|
|
gb.can[_4].msgId[idx] = _5;
|
|
# DEBUG BEGIN_STMT
|
|
_6 = can0_rxData[buffIdx].dataLen;
|
|
_7 = (int) instance;
|
|
_8 = (unsigned int) _6;
|
|
gb.can[_7].len[idx] = _8;
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (int) instance;
|
|
_10 = can0_rxData[buffIdx].data[i];
|
|
gb.can[_9].data[idx][i] = _10;
|
|
# DEBUG BEGIN_STMT
|
|
i = i + 1;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_11 = (int) instance;
|
|
_12 = gb.can[_11].len[idx];
|
|
if (i < _12)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_13 = (int) instance;
|
|
_14 = gb.can[_13].tail;
|
|
_15 = _14 + 1;
|
|
_16 = (int) instance;
|
|
_17 = _15 % 100;
|
|
gb.can[_16].tail = _17;
|
|
# DEBUG BEGIN_STMT
|
|
_18 = (int) instance;
|
|
gb.can[_18].error = 1;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
i2c_delay (u32 tick)
|
|
{
|
|
volatile u32 time;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
time = tick;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
time.9_1 = time;
|
|
time.10_2 = time.9_1;
|
|
_3 = time.10_2 + 4294967295;
|
|
time = _3;
|
|
if (time.10_2 != 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 4> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
sda_out ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 1076428800B;
|
|
_1->MSCR[32] = 2621440;
|
|
# DEBUG BEGIN_STMT
|
|
i2c_delay (500);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
sda_in ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 1076428800B;
|
|
_1->MSCR[32] = 524288;
|
|
# DEBUG BEGIN_STMT
|
|
i2c_delay (500);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
i2c_test ()
|
|
{
|
|
uint8_t i;
|
|
uint8_t checkOk;
|
|
uint32_t slavetimeout;
|
|
uint32_t mastertimeout;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
mastertimeout = 65535;
|
|
# DEBUG BEGIN_STMT
|
|
slavetimeout = 65535;
|
|
# DEBUG BEGIN_STMT
|
|
checkOk = 1;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
Lpi2c_Ip_SlaveSetBuffer (1, &rxBufferSlave, 8);
|
|
# DEBUG BEGIN_STMT
|
|
Lpi2c_Ip_MasterSendData (0, &txBuffer, 8, 1);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
mastertimeout = mastertimeout + 4294967295;
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Lpi2c_Ip_MasterGetTransferStatus (0, 0B);
|
|
if (_1 == 2)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 5> :
|
|
if (mastertimeout != 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
slavetimeout = slavetimeout + 4294967295;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
_2 = Lpi2c_Ip_SlaveGetTransferStatus (1, 0B);
|
|
if (_2 == 2)
|
|
goto <bb 8>; [INV]
|
|
else
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 8> :
|
|
if (slavetimeout != 0)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 9>; [INV]
|
|
|
|
<bb 9> :
|
|
# DEBUG BEGIN_STMT
|
|
i = 0;
|
|
goto <bb 14>; [INV]
|
|
|
|
<bb 10> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = (int) i;
|
|
_4 = txBuffer[_3];
|
|
_5 = (int) i;
|
|
_6 = rxBufferSlave[_5];
|
|
if (_4 != _6)
|
|
goto <bb 11>; [INV]
|
|
else
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
# DEBUG BEGIN_STMT
|
|
checkOk = 0;
|
|
goto <bb 13>; [INV]
|
|
|
|
<bb 12> :
|
|
# DEBUG BEGIN_STMT
|
|
_7 = (int) i;
|
|
_8 = txBuffer[_7];
|
|
_9 = _8;
|
|
_10 = _9 + 1;
|
|
txBuffer[_7] = _10;
|
|
|
|
<bb 13> :
|
|
# DEBUG BEGIN_STMT
|
|
i.8_11 = i;
|
|
i = i.8_11 + 1;
|
|
|
|
<bb 14> :
|
|
# DEBUG BEGIN_STMT
|
|
if (i <= 7)
|
|
goto <bb 10>; [INV]
|
|
else
|
|
goto <bb 15>; [INV]
|
|
|
|
<bb 15> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
i2c1_init ()
|
|
{
|
|
u32 i;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (162);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (162, LPI2C1_Master_Slave_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 1076428800B;
|
|
_1->MSCR[104] = 2621442;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = 1076428800B;
|
|
_2->IMCR[219] = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 1076428800B;
|
|
_3->MSCR[105] = 2621442;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = 1076428800B;
|
|
_4->IMCR[217] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
Lpi2c_Ip_MasterInit (0, &I2c_Lpi2cMasterChannel0_BOARD_InitPeripherals);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
i2c0_init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (161);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_InstallHandler (161, LPI2C0_Master_Slave_IRQHandler, 0B);
|
|
# DEBUG BEGIN_STMT
|
|
_1 = 1076428800B;
|
|
_1->MSCR[109] = 2621444;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = 1076428800B;
|
|
_2->IMCR[214] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = 1076428800B;
|
|
_3->MSCR[110] = 2621444;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = 1076428800B;
|
|
_4->IMCR[212] = 2;
|
|
# DEBUG BEGIN_STMT
|
|
Lpi2c_Ip_SlaveInit (1, &I2c_Lpi2cSlaveChannel1_BOARD_InitPeripherals);
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Lin_tx_test (uint8_t instance)
|
|
{
|
|
volatile Lpuart_Lin_Ip_StatusType transmissionStatus;
|
|
uint8_t bytesRemaining[3];
|
|
volatile uint32_t timeoutValue;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
timeoutValue = 0;
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
transmissionStatus = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_1 = (long unsigned int) instance;
|
|
Lpuart_Lin_Ip_MasterSendHeader (_1, 26);
|
|
# DEBUG BEGIN_STMT
|
|
timeoutValue = 1600000;
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
isSend.3_2 = isSend;
|
|
_3 = ~isSend.3_2;
|
|
if (_3 != 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
isSend.4_4 = isSend;
|
|
if (isSend.4_4 != 0)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
_5 = (long unsigned int) instance;
|
|
_6 = Lpuart_Lin_Ip_GetTransmitStatus (_5, &bytesRemaining);
|
|
transmissionStatus = _6;
|
|
# DEBUG BEGIN_STMT
|
|
timeoutValue.5_7 = timeoutValue;
|
|
timeoutValue.6_8 = timeoutValue.5_7;
|
|
_9 = timeoutValue.6_8 + 4294967295;
|
|
timeoutValue = _9;
|
|
if (timeoutValue.6_8 != 0)
|
|
goto <bb 6>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
transmissionStatus.7_10 = transmissionStatus;
|
|
if (transmissionStatus.7_10 != 0)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 7> :
|
|
bytesRemaining = {CLOBBER};
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Lin2callback (uint32_t instance, struct Lpuart_Lin_Ip_StateStructType * lpuartStateStruct)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = lpuartStateStruct->currentEventId;
|
|
_2 = (int) _1;
|
|
if (_2 == 6)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
isSend = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = lpuartStateStruct->currentId;
|
|
if (_3 == 42)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Lin_Ip_AsyncSendFrameData (instance, &txBuff_lin, 3);
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Lin1callback (uint32_t instance, struct Lpuart_Lin_Ip_StateStructType * lpuartStateStruct)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = lpuartStateStruct->currentEventId;
|
|
_2 = (int) _1;
|
|
if (_2 == 6)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
<L0>:
|
|
# DEBUG BEGIN_STMT
|
|
isSend = 1;
|
|
# DEBUG BEGIN_STMT
|
|
_3 = lpuartStateStruct->currentId;
|
|
if (_3 == 26)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Lin_Ip_AsyncSendFrameData (instance, &txBuff_lin, 3);
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Lin_init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (142);
|
|
# DEBUG BEGIN_STMT
|
|
IntCtrl_Ip_EnableIrq (150);
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("start\r\n");
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Lin_Ip_Init (0, &Lpuart_Lin_Ip_pHwConfigPB_0_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
Lpuart_Lin_Ip_Init (1, &Lpuart_Lin_Ip_pHwConfigPB_1_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
debug_printf ("end\r\n");
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SPI_test ()
|
|
{
|
|
uint8_t count;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
passed = 1;
|
|
# DEBUG BEGIN_STMT
|
|
numberOfBytes.0_1 = numberOfBytes;
|
|
timeOut.1_2 = timeOut;
|
|
_3 = Lpspi_Ip_SyncTransmit (&Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals, &txBuffer_spi, &rxBuffer_spi, numberOfBytes.0_1, timeOut.1_2);
|
|
trans_ret = _3;
|
|
# DEBUG BEGIN_STMT
|
|
count = 0;
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_4 = (int) count;
|
|
_5 = txBuffer_spi[_4];
|
|
_6 = (int) count;
|
|
_7 = rxBuffer_spi[_6];
|
|
if (_5 != _7)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
passed = 0;
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
count.2_8 = count;
|
|
count = count.2_8 + 1;
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
if (count <= 9)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 7> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SPI_init ()
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Lpspi_Ip_Init (&Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_BOARD_InitPeripherals);
|
|
init_ret = _1;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Set_PWM_Duty (u32 ch, float ratio)
|
|
{
|
|
u32 val;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
if (ratio >= 1.0e+2)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 4>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
val = gb.pwm_max_tick;
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
if (ratio <= 0.0)
|
|
goto <bb 5>; [INV]
|
|
else
|
|
goto <bb 6>; [INV]
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
val = 0;
|
|
goto <bb 7>; [INV]
|
|
|
|
<bb 6> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = gb.pwm_max_tick;
|
|
_2 = (float) _1;
|
|
_3 = ratio * _2;
|
|
_4 = (double) _3;
|
|
_5 = _4 / 1.0e+2;
|
|
val = (u32) _5;
|
|
|
|
<bb 7> :
|
|
# DEBUG BEGIN_STMT
|
|
gb.pwm_duty[ch] = ratio;
|
|
# DEBUG BEGIN_STMT
|
|
switch (ch) <default: <L10> [INV], case 0: <L6> [INV], case 1: <L7> [INV], case 2: <L8> [INV], case 3: <L9> [INV]>
|
|
|
|
<bb 8> :
|
|
<L6>:
|
|
# DEBUG BEGIN_STMT
|
|
_6 = (short unsigned int) val;
|
|
Emios_Pwm_Ip_SetDutyCycle (0, 0, _6);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 9> :
|
|
<L7>:
|
|
# DEBUG BEGIN_STMT
|
|
_7 = (short unsigned int) val;
|
|
Emios_Pwm_Ip_SetDutyCycle (0, 1, _7);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 10> :
|
|
<L8>:
|
|
# DEBUG BEGIN_STMT
|
|
_8 = (short unsigned int) val;
|
|
Emios_Pwm_Ip_SetDutyCycle (0, 2, _8);
|
|
# DEBUG BEGIN_STMT
|
|
goto <bb 12>; [INV]
|
|
|
|
<bb 11> :
|
|
<L9>:
|
|
# DEBUG BEGIN_STMT
|
|
_9 = (short unsigned int) val;
|
|
Emios_Pwm_Ip_SetDutyCycle (0, 3, _9);
|
|
# DEBUG BEGIN_STMT
|
|
|
|
<bb 12> :
|
|
<L10>:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
pwm_init (u32 period)
|
|
{
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_DeInitChannel (0, 0);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_DeInitChannel (0, 1);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_DeInitChannel (0, 2);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_DeInitChannel (0, 3);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Mcl_Ip_Deinit (0);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Mcl_Ip_Init (0, &Emios_Mcl_Ip_0_Config_BOARD_INITPERIPHERALS);
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Emios_Mcl_Ip_0_MasterBusConfig_BOARD_INITPERIPHERALS[0].hwChannel;
|
|
_2 = (short unsigned int) period;
|
|
Emios_Mcl_Ip_SetCounterBusPeriod (0, _1, _2);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_InitChannel (0, &Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch0);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_InitChannel (0, &Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch1);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_InitChannel (0, &Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch2);
|
|
# DEBUG BEGIN_STMT
|
|
Emios_Pwm_Ip_InitChannel (0, &Emios_Pwm_Ip_BOARD_InitPeripherals_I0_Ch3);
|
|
return;
|
|
|
|
}
|
|
|
|
|