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215 lines
7.6 KiB
C
215 lines
7.6 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral : FLEXCAN
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* Dependencies :
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file
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*
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* @brief FlexCAN Registers and Default Reg Values
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* @details <File details>
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*
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* @addtogroup FlexCAN
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* @{
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*/
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#ifndef FLEXCAN_IP_DEVICEREG_H_
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#define FLEXCAN_IP_DEVICEREG_H_
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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#include "Platform_Types.h"
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#include "S32K344_FLEXCAN.h"
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#include "S32K344_DCM_GPR.h"
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define FLEXCAN_IP_DEVICEREG_VENDOR_ID_H 43
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#define FLEXCAN_IP_DEVICEREG_AR_RELEASE_MAJOR_VERSION_H 4
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#define FLEXCAN_IP_DEVICEREG_AR_RELEASE_MINOR_VERSION_H 4
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#define FLEXCAN_IP_DEVICEREG_AR_RELEASE_REVISION_VERSION_H 0
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#define FLEXCAN_IP_DEVICEREG_SW_MAJOR_VERSION_H 0
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#define FLEXCAN_IP_DEVICEREG_SW_MINOR_VERSION_H 9
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#define FLEXCAN_IP_DEVICEREG_SW_PATCH_VERSION_H 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
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/* Check if current file and Platform_Types header file are of the same version */
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/* Check if current file and S32K344_FLEXCAN header file are of the same version */
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#endif
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/*==================================================================================================
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* CONSTANTS
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==================================================================================================*/
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/*==================================================================================================
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* DEFINES AND MACROS
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==================================================================================================*/
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/* Default value for register */
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/**
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* @brief Default value for the MCR register
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*/
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#define FLEXCAN_MCR_DEFAULT_VALUE_U32 ((uint32)0xD890000FU)
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/**
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* @brief Default value for the CTRL1 register
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*/
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#define FLEXCAN_CTRL1_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the TIMER register
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*/
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#define FLEXCAN_TIMER_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ECR register
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*/
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#define FLEXCAN_ECR_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ESR1 register
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*/
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#define FLEXCAN_ESR1_DEFAULT_VALUE_U32 ((uint32)0x0003B006U)
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/**
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* @brief Default value for the IMASK2 register
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*/
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#define FLEXCAN_IMASK_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the IFLAG4 register
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*/
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#define FLEXCAN_IFLAG_DEFAULT_VALUE_U32 ((uint32)0xFFFFFFFFU)
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/**
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* @brief Default value for the CTRL2 register
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*/
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#define FLEXCAN_CTRL2_DEFAULT_VALUE_U32 ((uint32)0x00100000U)
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/**
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* @brief Default value for the CTRL2 register
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*/
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#define FLEXCAN_CBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the MECR register
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*/
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#define FLEXCAN_MECR_DEFAULT_VALUE_U32 ((uint32)0x000C0080U)
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/**
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* @brief Default value for the ERRIAR register
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*/
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#define FLEXCAN_ERRIAR_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERRIDPR register
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*/
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#define FLEXCAN_ERRIDPR_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERRIPPR register
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*/
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#define FLEXCAN_ERRIPPR_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERRSR register
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*/
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#define FLEXCAN_ERRSR_DEFAULT_VALUE_U32 ((uint32)0x000D000DU)
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/**
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* @brief Default value for the FDCTRL register
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*/
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#define FLEXCAN_FDCTRL_DEFAULT_VALUE_U32 ((uint32)0x80004100U)
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/**
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* @brief Default value for the FDCBT register
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*/
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#define FLEXCAN_FDCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERFCR register
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*/
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#define FLEXCAN_ERFCR_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERFIER register
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*/
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#define FLEXCAN_ERFIER_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ERFSR register
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*/
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#define FLEXCAN_ERFSR_DEFAULT_VALUE_U32 ((uint32)0xF8000000U)
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/**
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* @brief Default value for the EPRS register
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*/
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#define FLEXCAN_EPRS_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ENCBT register
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*/
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#define FLEXCAN_ENCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the EDCBT register
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*/
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#define FLEXCAN_EDCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/**
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* @brief Default value for the ETDC register
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*/
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#define FLEXCAN_ETDC_DEFAULT_VALUE_U32 ((uint32)0x00000000U)
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/* @brief number of CAN peripheral has Enhanced Rx FIFO mode */
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#define FEATURE_CAN_ENHANCED_RX_FIFO_NUM (1u)
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/** Array initializer of CAN peripheral base addresses has Enhanced Rx FIFO mode*/
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#define CAN_BASE_PTRS_HAS_ENHANCED_RX_FIFO { CAN_0 }
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#define FEATURE_CAN_BUSOFF_ERROR_INTERRUPT_UNIFIED (STD_ON)
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/* Workaround for difference base address naming defined in BASE */
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/** Peripheral FLEXCAN_0 base address */
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#define FLEXCAN_0_BASE CAN_0_BASE
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/** Peripheral FLEXCAN_1 base address */
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#define FLEXCAN_1_BASE CAN_1_BASE
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/** Peripheral FLEXCAN_2 base address */
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#define FLEXCAN_2_BASE CAN_2_BASE
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/** Peripheral FLEXCAN_3 base address */
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#define FLEXCAN_3_BASE CAN_3_BASE
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/** Peripheral FLEXCAN_4 base address */
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#define FLEXCAN_4_BASE CAN_4_BASE
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/** Peripheral FLEXCAN_5 base address */
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#define FLEXCAN_5_BASE CAN_5_BASE
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#define CAN_RAMn_COUNT 384u
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#define CAN_RAM2n_COUNT 20u
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/* Registers used By Timestamp HR source in FlexCAN_ConfigTimestampModule */
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#define TIMESTAMP_REG DCM_GPR->DCMRWF1
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#define CAN_TIMESTAMP_SEL(x) DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL(x)
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#define CAN_TIMESTAMP_EN_MASK DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_MASK
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#endif /* FLEXCAN_IP_DEVICEREG_H_ */
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/** @} */
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