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https://github.com/Dev-KATECH/ADM.git
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463 lines
16 KiB
C
463 lines
16 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral : DMA,CACHE,TRGMUX,LCU,EMIOS,FLEXIO
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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/**
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* @file Flexio_Mcl_Ip_HwAccess.c
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*
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* @version 0.9.0
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*
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* @brief AUTOSAR Mcl - Flexio Common driver source file.
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* @details
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*
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* @addtogroup FLEXIO_IP_DRIVER FLEXIO IP Driver
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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#include "Flexio_Mcl_Ip_HwAccess.h"
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#include "SchM_Mcl.h"
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define FLEXIO_MCL_IP_HWACCESS_VENDOR_ID_C 43
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#define FLEXIO_MCL_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION_C 4
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#define FLEXIO_MCL_IP_HWACCESS_AR_RELEASE_MINOR_VERSION_C 4
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#define FLEXIO_MCL_IP_HWACCESS_AR_RELEASE_REVISION_VERSION_C 0
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#define FLEXIO_MCL_IP_HWACCESS_SW_MAJOR_VERSION_C 0
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#define FLEXIO_MCL_IP_HWACCESS_SW_MINOR_VERSION_C 9
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#define FLEXIO_MCL_IP_HWACCESS_SW_PATCH_VERSION_C 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/*==================================================================================================
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* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
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==================================================================================================*/
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/*==================================================================================================
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* LOCAL CONSTANTS
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==================================================================================================*/
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/*==================================================================================================
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* LOCAL VARIABLES
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL CONSTANTS
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL VARIABLES
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==================================================================================================*/
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/*==================================================================================================
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* LOCAL FUNCTION PROTOTYPES
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==================================================================================================*/
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/*==================================================================================================
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* LOCAL FUNCTIONS
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL FUNCTIONS PROTOTYPES
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==================================================================================================*/
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/*==================================================================================================
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GLOBAL FUNCTIONS
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==================================================================================================*/
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#define MCL_START_SEC_CODE
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#include "Mcl_MemMap.h"
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/*
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* Calling this function with enable parameter set to TRUE resets all internal
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* master logic and registers, except the FlexIO Control Register. The reset state
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* persists until this function is called with enable parameter set to false.
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*/
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void Flexio_Mcl_Ip_SetSoftwareReset(FLEXIO_Type *baseAddr, boolean enable)
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{
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_39();
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uint32 regValue = (uint32)baseAddr->CTRL;
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regValue &= (~((uint32)FLEXIO_CTRL_SWRST_MASK));
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regValue |= FLEXIO_CTRL_SWRST((enable ? 1U : 0U));
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baseAddr->CTRL = (uint32)regValue;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_39();
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}
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/*
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* This function enables or disables Debug Enable module.
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*/
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void Flexio_Mcl_Ip_SetDebugEnable(FLEXIO_Type *baseAddr, boolean enable)
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{
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_40();
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uint32 regValue = (uint32)baseAddr->CTRL;
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regValue &= (~((uint32)FLEXIO_CTRL_DBGE_MASK));
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regValue |= FLEXIO_CTRL_DBGE((enable ? 1U : 0U));
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baseAddr->CTRL = (uint32)regValue;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_40();
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}
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/*
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* This function enables or disables the FlexIO module.
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*/
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void Flexio_Mcl_Ip_SetEnable(FLEXIO_Type *baseAddr, boolean enable)
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{
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_41();
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uint32 regValue = (uint32)baseAddr->CTRL;
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regValue &= (~((uint32)FLEXIO_CTRL_FLEXEN_MASK));
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regValue |= FLEXIO_CTRL_FLEXEN((enable ? 1U : 0U));
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baseAddr->CTRL = (uint32)regValue;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_41();
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}
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/*
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* This function returns the value of the status flag for the specified shifter.
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* The meaning of the status flag depends on the current mode.
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* - Transmit mode: shifter buffer is empty and ready to accept more data
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* - Receive mode: shifter buffer is full and received data can be read from it
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* - Match Store mode: match occurred between shifter buffer and shifter
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* - Match Continuous mode: current match result between shifter buffer and shifter
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*/
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boolean Flexio_Mcl_Ip_GetShifterStatus(const FLEXIO_Type *baseAddr, uint8 shifter)
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{
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return ((((baseAddr->SHIFTSTAT >> shifter) & 1U) != 0U) ? TRUE : FALSE);
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}
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/*
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* This function returns the value of the status flags for all shifters. Each bit in
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* the returned value specifies the status for one shifter, starting with
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* shifter 0 from least significant bit.
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* The meaning of the status flag depends on the current mode.
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* - Transmit mode: shifter buffer is empty and ready to accept more data
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* - Receive mode: shifter buffer is full and received data can be read from it
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* - Match Store mode: match occurred between shifter buffer and shifter
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* - Match Continuous mode: current match result between shifter buffer and shifter
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*/
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uint32 Flexio_Mcl_Ip_GetAllShifterStatus(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->SHIFTSTAT;
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}
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/*
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* This function clears the status flag for the specified shifter. This is possible in
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* all modes except Match Continuous mode.
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*/
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void Flexio_Mcl_Ip_ClearShifterStatus(FLEXIO_Type *baseAddr, uint8 shifter)
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{
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baseAddr->SHIFTSTAT = 1UL << shifter;
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}
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/*
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* This function returns the value of the error status flag for the specified shifter.
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* The meaning of the error status flag depends on the current mode.
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* - Transmit mode: shifter buffer was not written before it was transferred in the shifter (buffer overrun)
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* - Receive mode: shifter buffer was not read before new data was transferred from the shifter (buffer underrun)
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* - Match Store mode: match event occurred before the previous match data was read from shifter buffer (buffer overrun)
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* - Match Continuous mode: match occurred between shifter buffer and shifter
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*/
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boolean Flexio_Mcl_Ip_GetShifterErrorStatus(const FLEXIO_Type *baseAddr, uint8 shifter)
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{
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return ((((baseAddr->SHIFTERR >> shifter) & 1U) != 0U) ? TRUE : FALSE);
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}
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/*
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* This function returns the value of the error status flags for all shifters. Each bit in
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* the returned value specifies the error status for one shifter, starting with
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* shifter 0 from least significant bit.
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* The meaning of the error status flag depends on the current mode.
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* - Transmit mode: shifter buffer was not written before it was transferred in the shifter (buffer overrun)
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* - Receive mode: shifter buffer was not read before new data was transferred from the shifter (buffer underrun)
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* - Match Store mode: match event occurred before the previous match data was read from shifter buffer (buffer overrun)
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* - Match Continuous mode: match occurred between shifter buffer and shifter
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*/
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uint32 Flexio_Mcl_Ip_GetAllShifterErrorStatus(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->SHIFTERR;
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}
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/*
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* This function clears the error status flag for the specified shifter.
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*/
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void Flexio_Mcl_Ip_ClearShifterErrorStatus(FLEXIO_Type *baseAddr, uint8 shifter)
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{
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baseAddr->SHIFTERR = 1UL << shifter;
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}
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/*
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* This function returns the value of the status flag for the specified timer.
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* The meaning of the status flag depends on the current mode.
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* - 8-bit counter mode: the timer status flag is set when the upper 8-bit counter equals zero
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* and decrements. This also causes the counter to reload with the value in the compare register.
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* - 8-bit PWM mode: the upper 8-bit counter equals zero and decrements. This also causes the
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* counter to reload with the value in the compare register.
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* - 16-bit counter mode: the 16-bit counter equals zero and decrements. This also causes the
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* counter to reload with the value in the compare register.
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*/
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boolean Flexio_Mcl_Ip_GetTimerStatus(const FLEXIO_Type *baseAddr, uint8 timer)
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{
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return ((((baseAddr->TIMSTAT >> timer) & 1U) != 0U) ? TRUE : FALSE);
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}
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boolean Flexio_Mcl_Ip_GetTimerInterruptEnable(const FLEXIO_Type *baseAddr, uint8 timer)
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{
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return ((((baseAddr->TIMIEN >> timer) & 1U) != 0U) ? TRUE : FALSE);
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}
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/*
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* This function returns the value of the status flags for all timers. Each bit in
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* the returned value specifies the status for one timer, starting with
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* timer 0 from least significant bit.
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* The meaning of the status flag depends on the current mode.
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* - 8-bit counter mode: the timer status flag is set when the upper 8-bit counter equals zero
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* and decrements. This also causes the counter to reload with the value in the compare register.
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* - 8-bit PWM mode: the upper 8-bit counter equals zero and decrements. This also causes the
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* counter to reload with the value in the compare register.
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* - 16-bit counter mode: the 16-bit counter equals zero and decrements. This also causes the
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* counter to reload with the value in the compare register.
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*/
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uint32 Flexio_Mcl_Ip_GetAllTimerStatus(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->TIMSTAT;
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}
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/*
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* This function clears the status flag for the specified timer.
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*/
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void Flexio_Mcl_Ip_ClearTimerStatus(FLEXIO_Type *baseAddr, uint8 timer)
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{
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baseAddr->TIMSTAT = 1UL << timer;
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}
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/*
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* Returns the state of the interrupt for all shifters. Each bit in
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* the returned value specifies the interrupt state for one shifter, starting with
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* shifter 0 from least significant bit.
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*/
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uint32 Flexio_Mcl_Ip_GetAllShifterInterrupt(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->SHIFTSIEN;
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}
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/*
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* Returns the state of the error interrupt for all shifters. Each bit in
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* the returned value specifies the interrupt state for one shifter, starting with
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* shifter 0 from least significant bit.
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*/
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uint32 Flexio_Mcl_Ip_GetAllShifterErrorInterrupt(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->SHIFTEIEN;
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}
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/*
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* Enable or disable specified shifter error interrupts. The interrupt mask must contain a
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* bit of 1 for each shifter who's error interrupt must be enabled or disabled.
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*/
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void Flexio_Mcl_Ip_SetShifterErrorInterrupt(FLEXIO_Type *baseAddr, uint8 interruptMask, boolean enable)
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{
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uint32 tmp;
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_42();
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tmp = baseAddr->SHIFTEIEN;
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if (enable == TRUE)
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{
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tmp |= (uint32)interruptMask;
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}
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else
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{
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tmp &= ~(uint32)interruptMask;
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}
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baseAddr->SHIFTEIEN = tmp;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_42();
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}
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/*
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* Enable or disable specified shifter interrupts. The interrupt mask must contain a
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* bit of 1 for each shifter who's interrupt must be enabled or disabled.
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*/
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void Flexio_Mcl_Ip_SetShifterInterrupt(FLEXIO_Type *baseAddr, uint8 interruptMask, boolean enable)
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{
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uint32 tmp;
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_43();
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tmp = baseAddr->SHIFTSIEN;
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if (enable == TRUE)
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{
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tmp |= (uint32)interruptMask;
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}
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else
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{
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tmp &= ~(uint32)interruptMask;
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}
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baseAddr->SHIFTSIEN = tmp;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_43();
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}
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/*
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* This function returns the content of PINSTAT register
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*/
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uint32 Flexio_Mcl_Ip_GetAllPinsStatus(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->PINSTAT;
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}
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/*
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* This function returns the content of PINIEN register
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*/
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uint32 Flexio_Mcl_Ip_GetAllPinsInterrupt(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->PINIEN;
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}
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/*
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* Enable or disable specified shifter DMA requests. The request mask must contain a
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* bit of 1 for each shifter who's DMA requests must be enabled or disabled.
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*/
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void Flexio_Mcl_Ip_SetShifterDMARequest(FLEXIO_Type *baseAddr, uint8 requestMask, boolean enable)
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{
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uint32 tmp;
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_44();
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tmp = baseAddr->SHIFTSDEN;
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if (enable == TRUE)
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{
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tmp |= (uint32)requestMask;
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}
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else
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{
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tmp &= ~(uint32)requestMask;
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}
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baseAddr->SHIFTSDEN = tmp;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_44();
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}
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/*
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* Returns the state of the interrupt for all timers. Each bit in
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* the returned value specifies the interrupt state for one timer, starting with
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* timer 0 from least significant bit.
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*/
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uint32 Flexio_Mcl_Ip_GetAllTimerInterrupt(const FLEXIO_Type *baseAddr)
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{
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return baseAddr->TIMIEN;
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}
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/*
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* Enable or disable specified timer interrupts. The interrupt mask must contain a
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* bit of 1 for each timer who's interrupt must be enabled or disabled.
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*/
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void Flexio_Mcl_Ip_SetTimerInterrupt(FLEXIO_Type *baseAddr, uint8 interruptMask, boolean enable)
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{
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uint32 tmp;
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_45();
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tmp = baseAddr->TIMIEN;
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if (enable == TRUE)
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{
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tmp |= (uint32)interruptMask;
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}
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else
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{
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tmp &= ~(uint32)interruptMask;
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}
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baseAddr->TIMIEN = tmp;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_45();
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}
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/*
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* This function initializes all the registers of the FlexIO module to
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* their reset value.
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*/
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void Flexio_Mcl_Ip_Init(FLEXIO_Type *baseAddr)
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{
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/* Use software reset bit to reset the module */
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Flexio_Mcl_Ip_SetSoftwareReset(baseAddr, TRUE);
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/* Control register is not affected by software reset */
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baseAddr->CTRL = 0x0U;
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}
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/*
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* Enable or disable specified timer DMA requests. The request mask must contain a
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* bit of 1 for each shifter who's DMA requests must be enabled or disabled.
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*/
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void Flexio_Mcl_Ip_SetTimerDMARequest(FLEXIO_Type *baseAddr, uint8 requestMask, boolean enable)
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{
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uint32 tmp;
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SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_46();
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tmp = baseAddr->TIMERSDEN;
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if (enable == TRUE)
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{
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tmp |= (uint32)requestMask;
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}
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else
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{
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tmp &= ~(uint32)requestMask;
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}
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baseAddr->TIMERSDEN = tmp;
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SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_46();
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}
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/*
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* This function clears the pin status flag for the specified pin.
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*/
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void Flexio_Mcl_Ip_ClearPinStatus(FLEXIO_Type *baseAddr, uint8 pin)
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{
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baseAddr->PINSTAT |= (uint8)(1U << pin);
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}
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#define MCL_STOP_SEC_CODE
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#include "Mcl_MemMap.h"
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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