mirror of
https://github.com/Dev-KATECH/ADM.git
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2140 lines
66 KiB
Plaintext
2140 lines
66 KiB
Plaintext
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Marking local functions:
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Marking externally visible functions: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 Spi_schm_read_msr
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Marking externally visible variables:
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Reclaiming functions:
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Reclaiming variables:
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Clearing address taken flags:
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Symbol table:
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Sys_GetCoreID/77 (Sys_GetCoreID) @05e49ee0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39
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Calls:
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18) @05e499a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18) @05e49700
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)msr_SPI_EXCLUSIVE_AREA_18/36 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17) @05e49460
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17) @05e491c0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)msr_SPI_EXCLUSIVE_AREA_17/34 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16) @05e40d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16) @05e407e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)msr_SPI_EXCLUSIVE_AREA_16/32 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15) @05e402a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15) @05e40ee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)msr_SPI_EXCLUSIVE_AREA_15/30 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14) @05e40c40
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14) @05e409a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)msr_SPI_EXCLUSIVE_AREA_14/28 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13) @05e40700
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13) @05e40460
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)msr_SPI_EXCLUSIVE_AREA_13/26 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12) @05e401c0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12) @05e3ad20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)msr_SPI_EXCLUSIVE_AREA_12/24 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11) @05e3a7e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11) @05e3a2a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)msr_SPI_EXCLUSIVE_AREA_11/22 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10) @05e3aee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10) @05e3ac40
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)msr_SPI_EXCLUSIVE_AREA_10/20 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09) @05e3a9a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09) @05e3a700
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)msr_SPI_EXCLUSIVE_AREA_09/18 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08) @05e3a460
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08) @05e3a1c0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)msr_SPI_EXCLUSIVE_AREA_08/16 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07) @05e33d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07) @05e337e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)msr_SPI_EXCLUSIVE_AREA_07/14 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06) @05e332a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)
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Referring:
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Availability: available
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Function flags: body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06) @05e33ee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)msr_SPI_EXCLUSIVE_AREA_06/12 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05) @05e33c40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05) @05e339a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)msr_SPI_EXCLUSIVE_AREA_05/10 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04) @05e33700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04) @05e33460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)msr_SPI_EXCLUSIVE_AREA_04/8 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03) @05e331c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03) @05d44ee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)msr_SPI_EXCLUSIVE_AREA_03/6 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02) @05d449a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02) @05d44460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)msr_SPI_EXCLUSIVE_AREA_02/4 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01) @05d44e00
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01) @05d44b60
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)msr_SPI_EXCLUSIVE_AREA_01/2 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00) @05d448c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00) @05d44620
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)msr_SPI_EXCLUSIVE_AREA_00/0 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by:
|
|
Calls: Spi_schm_read_msr/38 Sys_GetCoreID/77
|
|
Spi_schm_read_msr/38 (Spi_schm_read_msr) @05d44380
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: body optimize_size
|
|
Called by: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39
|
|
Calls:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (reentry_guard_SPI_EXCLUSIVE_AREA_18) @05d421b0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_18/36 (msr_SPI_EXCLUSIVE_AREA_18) @05d42120
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (reentry_guard_SPI_EXCLUSIVE_AREA_17) @05d42090
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_17/34 (msr_SPI_EXCLUSIVE_AREA_17) @05d42000
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (reentry_guard_SPI_EXCLUSIVE_AREA_16) @05d3df30
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_16/32 (msr_SPI_EXCLUSIVE_AREA_16) @05d3dea0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (reentry_guard_SPI_EXCLUSIVE_AREA_15) @05d3de10
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_15/30 (msr_SPI_EXCLUSIVE_AREA_15) @05d3dd80
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (reentry_guard_SPI_EXCLUSIVE_AREA_14) @05d3dcf0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_14/28 (msr_SPI_EXCLUSIVE_AREA_14) @05d3dc60
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (reentry_guard_SPI_EXCLUSIVE_AREA_13) @05d3dbd0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_13/26 (msr_SPI_EXCLUSIVE_AREA_13) @05d3db40
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (reentry_guard_SPI_EXCLUSIVE_AREA_12) @05d3dab0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_12/24 (msr_SPI_EXCLUSIVE_AREA_12) @05d3da20
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (reentry_guard_SPI_EXCLUSIVE_AREA_11) @05d3d990
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_11/22 (msr_SPI_EXCLUSIVE_AREA_11) @05d3d900
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (reentry_guard_SPI_EXCLUSIVE_AREA_10) @05d3d870
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_10/20 (msr_SPI_EXCLUSIVE_AREA_10) @05d3d7e0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (reentry_guard_SPI_EXCLUSIVE_AREA_09) @05d3d750
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_09/18 (msr_SPI_EXCLUSIVE_AREA_09) @05d3d6c0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (reentry_guard_SPI_EXCLUSIVE_AREA_08) @05d3d630
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_08/16 (msr_SPI_EXCLUSIVE_AREA_08) @05d3d5a0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (reentry_guard_SPI_EXCLUSIVE_AREA_07) @05d3d510
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_07/14 (msr_SPI_EXCLUSIVE_AREA_07) @05d3d480
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (reentry_guard_SPI_EXCLUSIVE_AREA_06) @05d3d3f0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_06/12 (msr_SPI_EXCLUSIVE_AREA_06) @05d3d360
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (reentry_guard_SPI_EXCLUSIVE_AREA_05) @05d3d2d0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_05/10 (msr_SPI_EXCLUSIVE_AREA_05) @05d3d240
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (reentry_guard_SPI_EXCLUSIVE_AREA_04) @05d3d1b0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_04/8 (msr_SPI_EXCLUSIVE_AREA_04) @05d3d120
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (reentry_guard_SPI_EXCLUSIVE_AREA_03) @05d3d090
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_03/6 (msr_SPI_EXCLUSIVE_AREA_03) @05d3d000
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (reentry_guard_SPI_EXCLUSIVE_AREA_02) @05d35f30
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_02/4 (msr_SPI_EXCLUSIVE_AREA_02) @05d35ea0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (reentry_guard_SPI_EXCLUSIVE_AREA_01) @05d35e10
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_01/2 (msr_SPI_EXCLUSIVE_AREA_01) @05d35d80
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (reentry_guard_SPI_EXCLUSIVE_AREA_00) @05d35cf0
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_00/0 (msr_SPI_EXCLUSIVE_AREA_00) @05d35c60
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> :
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId = (uint32) _1;
|
|
# DEBUG BEGIN_STMT
|
|
_2 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 3> :
|
|
# DEBUG BEGIN_STMT
|
|
_3 = Spi_schm_read_msr ();
|
|
msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 = msr_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 4>; [INV]
|
|
else
|
|
goto <bb 5>; [INV]
|
|
|
|
<bb 4> :
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> :
|
|
# DEBUG BEGIN_STMT
|
|
_6 = reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId];
|
|
_7 = _6 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = _7;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
Spi_schm_read_msr ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 D.4353;
|
|
|
|
<bb 2> :
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp);
|
|
# DEBUG BEGIN_STMT
|
|
D.4353 = reg_tmp;
|
|
return D.4353;
|
|
|
|
}
|
|
|
|
|