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1196211b1e
ADM/[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic.h
3minbe 1196211b1e Revert "1. Fail-Safety 적용" 
This reverts commit 73b84ca8fd.
2025-06-12 17:11:59 +09:00

269 lines
15 KiB
C
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/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: ADM_Integrated_Logic.h
*
* Code generated for Simulink model 'ADM_Integrated_Logic'.
*
* Model version : 13.63
* Simulink Coder version : 24.1 (R2024a) 19-Nov-2023
* C/C++ source code generated on : Wed Jun 4 15:25:59 2025
*
* Target selection: ert.tlc
* Embedded hardware selection: NXP->Cortex-M4
* Code generation objectives:
* 1. Execution efficiency
* 2. RAM efficiency
* 3. Debugging
* Validation result: Not run
*/
#ifndef ADM_Integrated_Logic_h_
#define ADM_Integrated_Logic_h_
#ifndef ADM_Integrated_Logic_COMMON_INCLUDES_
#define ADM_Integrated_Logic_COMMON_INCLUDES_
#include <stdbool.h>
#include <stdint.h>
#include "complex_types.h"
#endif /* ADM_Integrated_Logic_COMMON_INCLUDES_ */
#include "ADM_Integrated_Logic_types.h"
/* Block signals and states (default storage) for system '<Root>' */
typedef struct {
double Delay_DSTATE[2]; /* '<S35>/Delay' */
double Delay3_DSTATE[2]; /* '<S35>/Delay3' */
double Delay_DSTATE_p[2]; /* '<S27>/Delay' */
double Delay3_DSTATE_h[2]; /* '<S27>/Delay3' */
double DelayInput2_DSTATE; /* '<S46>/Delay Input2' */
double DelayInput2_DSTATE_m; /* '<S47>/Delay Input2' */
double Integrator_2_DSTATE; /* '<S8>/Integrator_2' */
double Memory_DSTATE; /* '<S7>/Memory' */
double DiscreteTransferFcn_states; /* '<S1>/Discrete Transfer Fcn' */
double d1_DSTATE; /* '<S21>/d1' */
double d_DSTATE; /* '<S21>/d' */
double d_DSTATE_i; /* '<S31>/d' */
double d1_DSTATE_p; /* '<S31>/d1' */
double d_DSTATE_c; /* '<S32>/d' */
double d1_DSTATE_h; /* '<S32>/d1' */
double d_DSTATE_d; /* '<S33>/d' */
double d1_DSTATE_l; /* '<S33>/d1' */
double Delay1_DSTATE; /* '<S35>/Delay1' */
double Delay2_DSTATE; /* '<S35>/Delay2' */
double d1_DSTATE_e; /* '<S34>/d1' */
double d_DSTATE_ij; /* '<S34>/d' */
double d_DSTATE_ir; /* '<S23>/d' */
double d1_DSTATE_o; /* '<S23>/d1' */
double d_DSTATE_m; /* '<S24>/d' */
double d1_DSTATE_hm; /* '<S24>/d1' */
double d_DSTATE_mw; /* '<S25>/d' */
double d1_DSTATE_g; /* '<S25>/d1' */
double d1_DSTATE_ej; /* '<S26>/d1' */
double d_DSTATE_j; /* '<S26>/d' */
double Delay1_DSTATE_c; /* '<S27>/Delay1' */
double Delay2_DSTATE_n; /* '<S27>/Delay2' */
double d1_DSTATE_ob; /* '<S41>/d1' */
double d_DSTATE_e; /* '<S41>/d' */
double d1_DSTATE_i; /* '<S42>/d1' */
double d_DSTATE_p; /* '<S42>/d' */
double d1_DSTATE_o1; /* '<S43>/d1' */
double d_DSTATE_n; /* '<S43>/d' */
double Integrator_1_DSTATE; /* '<S8>/Integrator_1' */
double d1_DSTATE_a; /* '<S44>/d1' */
double d_DSTATE_d1; /* '<S44>/d' */
double DelayInput2_DSTATE_c; /* '<S13>/Delay Input2' */
double DelayInput2_DSTATE_i; /* '<S14>/Delay Input2' */
double PrevY; /* '<S1>/Input_Vx_RateLimiter' */
double PrevY_o; /* '<S3>/Brake_Out_RateLimiter' */
double PrevY_a; /* '<S3>/TargetSpd_RateLimiter' */
double Memory_PreviousInput; /* '<S3>/Memory' */
double HAC_ON_FLAG; /* '<S8>/HAC_OFF_OK_Func' */
double Smoothed_Torque; /* '<S8>/HAC_OFF_OK_Func' */
double HAC_Desired_Torque; /* '<S8>/HAC_OFF_OK_Func' */
double HAC_ON_Timer; /* '<S8>/HAC_OFF_OK_Func' */
uint8_t is_active_c6_ADM_Integrated_Log;/* '<S8>/Chart' */
uint8_t is_c6_ADM_Integrated_Logic; /* '<S8>/Chart' */
} DW_ADM_Integrated_Logic_T;
/* Invariant block signals (default storage) */
typedef struct {
const double W_value; /* '<S40>/Multiply' */
const double W_Value_for_Brake; /* '<S40>/Multiply4' */
} ConstB_ADM_Integrated_Logic_T;
/* External inputs (root inport signals with default storage) */
typedef struct {
double GV_MCU_RPM; /* '<Root>/GV_MCU_RPM' */
double GV_BrakeTorqueCommand; /* '<Root>/GV_BrakeTorqueCommand' */
double GV_IMU_AX_Val; /* '<Root>/GV_IMU_AX_Val' */
double GV_IMU_AY_Val; /* '<Root>/GV_IMU_AY_Val' */
double GV_IMU_AZ_Val; /* '<Root>/GV_IMU_AZ_Val' */
double GV_IMU_PitchRtVal; /* '<Root>/GV_IMU_PitchRtVal' */
double GV_Vx_Command; /* '<Root>/GV_Vx_Command' */
double GV_VCU_GearSelStat; /* '<Root>/GV_VCU_GearSelStat' */
double GV_MCU_EstTrq; /* '<Root>/GV_MCU_EstTrq' */
double GV_Vx_Limit; /* '<Root>/GV_Vx_Limit' */
double GV_Vx_Fbk; /* '<Root>/GV_Vx_Fbk' */
double GV_RWA_RackAngleCommand; /* '<Root>/GV_RWA_RackAngleCommand' */
double GV_RWS_RackAngleCommand; /* '<Root>/GV_RWS_RackAngleCommand' */
double GV_RWA_Fault_Flag; /* '<Root>/GV_RWA_Fault_Flag' */
double GV_Operation_Mode; /* '<Root>/GV_Operation_Mode' */
} ExtU_ADM_Integrated_Logic_T;
/* External outputs (root outports fed by signals with default storage) */
typedef struct {
double GV_Brake_Command; /* '<Root>/GV_Brake_Command' */
double GV_Master_Rack_Angle_Cmd; /* '<Root>/GV_Master_Rack_Angle_Cmd' */
double GV_Hill_Torque_Assist; /* '<Root>/GV_Hill_Torque_Assist' */
double GV_Motor_Torque_Cmd; /* '<Root>/GV_Motor_Torque_Cmd' */
double Debug_HAC_FLAG; /* '<Root>/Debug_HAC_FLAG' */
double Debug_HAC_RPM_Decision; /* '<Root>/Debug_HAC_RPM_Decision' */
double Debug_HAC_Pitch_angle; /* '<Root>/Debug_HAC_Pitch_angle' */
double Debug_HAC_Brake_Output; /* '<Root>/Debug_HAC_Brake_Output' */
double Debug_CC_Brake_Output; /* '<Root>/Debug_CC_Brake_Output' */
double GV_RWS_RackAngleCmd1; /* '<Root>/GV_RWS_RackAngleCmd1' */
double GV_Speed_Limit; /* '<Root>/GV_Speed_Limit' */
double GV_Gear_Postion_Out; /* '<Root>/GV_Gear_Postion_Out' */
} ExtY_ADM_Integrated_Logic_T;
/* Block signals and states (default storage) */
extern DW_ADM_Integrated_Logic_T ADM_Integrated_Logic_DW;
/* External inputs (root inport signals with default storage) */
extern ExtU_ADM_Integrated_Logic_T ADM_Integrated_Logic_U;
/* External outputs (root outports fed by signals with default storage) */
extern ExtY_ADM_Integrated_Logic_T ADM_Integrated_Logic_Y;
extern const ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB;/* constant block i/o */
/* Model entry point functions */
extern void ADM_Integrated_Logic_initialize(void);
extern void ADM_Integrated_Logic_step(void);
extern void ADM_Integrated_Logic_terminate(void);
/*-
* These blocks were eliminated from the model due to optimizations:
*
* Block '<S18>/BW_PI' : Unused code path elimination
* Block '<S18>/Constant1' : Unused code path elimination
* Block '<S18>/Constant16' : Unused code path elimination
* Block '<S18>/Constant17' : Unused code path elimination
* Block '<S18>/Constant2' : Unused code path elimination
* Block '<S1>/Data Type Conversion2' : Unused code path elimination
* Block '<S1>/Gain2' : Unused code path elimination
* Block '<S40>/Abs' : Unused code path elimination
* Block '<S40>/Brake_Saturation' : Unused code path elimination
* Block '<S40>/Multiply5' : Unused code path elimination
* Block '<S40>/Radius1' : Unused code path elimination
* Block '<S46>/FixPt Data Type Duplicate' : Unused code path elimination
* Block '<S51>/Data Type Duplicate' : Unused code path elimination
* Block '<S51>/Data Type Propagation' : Unused code path elimination
* Block '<S47>/FixPt Data Type Duplicate' : Unused code path elimination
* Block '<S52>/Data Type Duplicate' : Unused code path elimination
* Block '<S52>/Data Type Propagation' : Unused code path elimination
* Block '<S8>/Scope2' : Unused code path elimination
* Block '<S13>/FixPt Data Type Duplicate' : Unused code path elimination
* Block '<S53>/Data Type Duplicate' : Unused code path elimination
* Block '<S53>/Data Type Propagation' : Unused code path elimination
* Block '<S14>/FixPt Data Type Duplicate' : Unused code path elimination
* Block '<S54>/Data Type Duplicate' : Unused code path elimination
* Block '<S54>/Data Type Propagation' : Unused code path elimination
* Block '<S3>/ControlFlag' : Eliminated nontunable gain of 1
* Block '<S18>/FBGain' : Eliminated nontunable gain of 1
* Block '<S29>/FFGain' : Eliminated nontunable gain of 1
* Block '<S1>/Data Type Conversion1' : Eliminate redundant data type conversion
* Block '<S1>/Data Type Conversion3' : Eliminate redundant data type conversion
* Block '<S40>/HAC_Gain' : Eliminated nontunable gain of 1
* Block '<S46>/Zero-Order Hold' : Eliminated since input and output rates are identical
* Block '<S47>/Zero-Order Hold' : Eliminated since input and output rates are identical
* Block '<S13>/Zero-Order Hold' : Eliminated since input and output rates are identical
* Block '<S14>/Zero-Order Hold' : Eliminated since input and output rates are identical
*/
/*-
* The generated code includes comments that allow you to trace directly
* back to the appropriate location in the model. The basic format
* is <system>/block_name, where system is the system number (uniquely
* assigned by Simulink) and block_name is the name of the block.
*
* Use the MATLAB hilite_system command to trace the generated code back
* to the model. For example,
*
* hilite_system('<S3>') - opens system 3
* hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
*
* Here is the system hierarchy for this model
*
* '<Root>' : 'ADM_Integrated_Logic'
* '<S1>' : 'ADM_Integrated_Logic/Delivery_Mobility'
* '<S2>' : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant'
* '<S3>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1'
* '<S4>' : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Brake_Func'
* '<S5>' : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Gear_Func1'
* '<S6>' : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Motor_Func'
* '<S7>' : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position'
* '<S8>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1'
* '<S9>' : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function1'
* '<S10>' : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function2'
* '<S11>' : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function5'
* '<S12>' : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function6'
* '<S13>' : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic'
* '<S14>' : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1'
* '<S15>' : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic'
* '<S16>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB'
* '<S17>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB_Gain'
* '<S18>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller'
* '<S19>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/GearCondition_Brake'
* '<S20>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Gear_pos_out'
* '<S21>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/LPFM'
* '<S22>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Target_RPM'
* '<S23>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot3'
* '<S24>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot4'
* '<S25>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot5'
* '<S26>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/LPFM'
* '<S27>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Second order LPF'
* '<S28>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB'
* '<S29>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF'
* '<S30>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB/P'
* '<S31>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot'
* '<S32>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot2'
* '<S33>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot3'
* '<S34>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/LPFM'
* '<S35>' : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Second order LPF'
* '<S36>' : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Compare To Constant'
* '<S37>' : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Gear_FUNCTION1'
* '<S38>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Chart'
* '<S39>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/HAC_OFF_OK_Func'
* '<S40>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2'
* '<S41>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM'
* '<S42>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM1'
* '<S43>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM2'
* '<S44>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM3'
* '<S45>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Pitch_calculate'
* '<S46>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic'
* '<S47>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1'
* '<S48>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_R'
* '<S49>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c'
* '<S50>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c1'
* '<S51>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic/Saturation Dynamic'
* '<S52>' : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1/Saturation Dynamic'
* '<S53>' : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic/Saturation Dynamic'
* '<S54>' : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1/Saturation Dynamic'
* '<S55>' : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Compare To Constant'
* '<S56>' : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Vx_OutPut_Function'
*/
/*-
* Requirements for '<Root>': ADM_Integrated_Logic
*/
#endif /* ADM_Integrated_Logic_h_ */
/*
* File trailer for generated code.
*
* [EOF]
*/
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