mirror of
https://github.com/Dev-KATECH/ADM.git
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225 lines
8.6 KiB
C
225 lines
8.6 KiB
C
#ifndef SIUL2_PORT_IP_CFG_H
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#define SIUL2_PORT_IP_CFG_H
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#include "S32K344_SIUL2.h"
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#include "Siul2_Port_Ip_Types.h"
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/***********************************************************************************************************************
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* Definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* SOURCE FILE VERSION INFORMATION
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**********************************************************************************************************************/
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#define SIUL2_PORT_IP_VENDOR_ID_CFG_H 43
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#define SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H 4
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#define SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H 4
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#define SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H 0
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#define SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H 0
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#define SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H 9
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#define SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H 0
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/*!
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* @addtogroup Siul2_Port_Ip_Cfg
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* @{
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*/
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/***********************************************************************************************************************
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* API
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**********************************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*! @brief Definitions for BOARD_InitPins Functional Group */
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#define SIUL2_MSCR_SSS_MASK (0x7U)
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#define SIUL2_MSCR_SSS_SHIFT (0U)
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#define SIUL2_MSCR_SSS_WIDTH (3U)
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#define SIUL2_MSCR_SSS(x) (((uint32)(((uint32)(x)) << SIUL2_MSCR_SSS_SHIFT)) & SIUL2_MSCR_SSS_MASK)
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#define SIUL2_MSCR_SRE_MASK (0x4000U)
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#define SIUL2_MSCR_SRE_SHIFT (14U)
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#define SIUL2_MSCR_SRE_WIDTH (1U)
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#define SIUL2_MSCR_SRE(x) (((uint32)(((uint32)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK)
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#define DEV_ASSERT(par)
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/*! @brief User number of configured pins */
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#define NUM_OF_CONFIGURED_PINS0 78
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/*! @brief User configuration structure */
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extern Siul2_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr0[NUM_OF_CONFIGURED_PINS0];
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/*! @brief Defines for user pin and port configurations */
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#define UART0_RX_PIN 2u
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#define UART0_RX_PORT PTA_L_HALF
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#define UART0_TX_PIN 3u
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#define UART0_TX_PORT PTA_L_HALF
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#define CAN0_RX_PIN 6u
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#define CAN0_RX_PORT PTA_L_HALF
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#define CAN0_TX_PIN 7u
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#define CAN0_TX_PORT PTA_L_HALF
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#define CAN0_EN_PIN 8u
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#define CAN0_EN_PORT PTC_H_HALF
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#define CAN0_STB_N_PIN 5u
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#define CAN0_STB_N_PORT PTC_H_HALF
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#define CAN1_TX_PIN 8u
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#define CAN1_TX_PORT PTC_L_HALF
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#define CAN1_RX_PIN 9u
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#define CAN1_RX_PORT PTC_L_HALF
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#define CAN1_EN_PIN 7u
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#define CAN1_EN_PORT PTD_H_HALF
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#define CAN1_STB_N_PIN 2u
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#define CAN1_STB_N_PORT PTD_L_HALF
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#define CAN2_TX_PIN 8u
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#define CAN2_TX_PORT PTE_H_HALF
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#define CAN3_TX_PIN 12u
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#define CAN3_TX_PORT PTC_H_HALF
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#define CAN3_RX_PIN 13u
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#define CAN3_RX_PORT PTC_H_HALF
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#define CAN4_TX_PIN 14u
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#define CAN4_TX_PORT PTC_H_HALF
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#define CAN4_RX_PIN 15u
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#define CAN4_RX_PORT PTC_H_HALF
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#define CAN5_TX_PIN 10u
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#define CAN5_TX_PORT PTC_L_HALF
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#define CAN5_RX_PIN 11u
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#define CAN5_RX_PORT PTC_L_HALF
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#define CAN2_EN_PIN 4u
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#define CAN2_EN_PORT PTD_L_HALF
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#define CAN3_EN_PIN 0u
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#define CAN3_EN_PORT PTB_L_HALF
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#define CAN4_EN_PIN 10u
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#define CAN4_EN_PORT PTC_H_HALF
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#define CAN5_EN_PIN 14u
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#define CAN5_EN_PORT PTD_H_HALF
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#define CAN2_STB_N_PIN 6u
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#define CAN2_STB_N_PORT PTD_H_HALF
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#define CAN3_STB_N_PIN 1u
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#define CAN3_STB_N_PORT PTB_L_HALF
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#define CAN4_STB_N_PIN 9u
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#define CAN4_STB_N_PORT PTC_H_HALF
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#define CAN5_STB_N_PIN 1u
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#define CAN5_STB_N_PORT PTE_H_HALF
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#define UART1_TX_PIN 7u
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#define UART1_TX_PORT PTC_L_HALF
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#define UART1_RX_PIN 6u
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#define UART1_RX_PORT PTC_L_HALF
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#define UART10_RX_PIN 12u
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#define UART10_RX_PORT PTC_L_HALF
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#define AIN_2_PIN 5u
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#define AIN_2_PORT PTE_H_HALF
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#define AIN_3_PIN 6u
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#define AIN_3_PORT PTE_H_HALF
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#define AIN_4_PIN 7u
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#define AIN_4_PORT PTE_H_HALF
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#define DOUT_2_PIN 12u
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#define DOUT_2_PORT PTA_L_HALF
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#define PWM_1_PIN 13u
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#define PWM_1_PORT PTB_L_HALF
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#define PWM_2_PIN 14u
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#define PWM_2_PORT PTB_L_HALF
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#define PWM_3_PIN 15u
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#define PWM_3_PORT PTB_L_HALF
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#define PWM_0_PIN 12u
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#define PWM_0_PORT PTB_L_HALF
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#define AIN_1_PIN 0u
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#define AIN_1_PORT PTE_L_HALF
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#define TEST_LED_PIN 2u
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#define TEST_LED_PORT PTC_H_HALF
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#define DOUT_0_PIN 0u
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#define DOUT_0_PORT PTA_L_HALF
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#define UART2_RX_PIN 8u
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#define UART2_RX_PORT PTA_L_HALF
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#define UART2_TX_PIN 9u
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#define UART2_TX_PORT PTA_L_HALF
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#define DOUT_5_PIN 14u
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#define DOUT_5_PORT PTA_L_HALF
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#define SPI1_CS0_PIN 5u
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#define SPI1_CS0_PORT PTA_H_HALF
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#define SPI1_SCK_PIN 12u
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#define SPI1_SCK_PORT PTA_H_HALF
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#define SPI1_MISO_PIN 14u
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#define SPI1_MISO_PORT PTA_H_HALF
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#define UART10_TX_PIN 13u
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#define UART10_TX_PORT PTC_L_HALF
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#define SPI2_CS1_PIN 3u
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#define SPI2_CS1_PORT PTC_H_HALF
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#define SPI1_CS1_PIN 4u
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#define SPI1_CS1_PORT PTE_L_HALF
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#define UART9_RX_PIN 2u
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#define UART9_RX_PORT PTB_L_HALF
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#define UART9_TX_PIN 3u
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#define UART9_TX_PORT PTB_L_HALF
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#define DIN_0_PIN 8u
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#define DIN_0_PORT PTB_L_HALF
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#define DIN_3_PIN 11u
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#define DIN_3_PORT PTB_L_HALF
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#define UART13_TX_PIN 2u
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#define UART13_TX_PORT PTB_H_HALF
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#define UART13_RX_PIN 3u
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#define UART13_RX_PORT PTB_H_HALF
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#define DIN_4_PIN 4u
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#define DIN_4_PORT PTB_H_HALF
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#define DIN_5_PIN 5u
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#define DIN_5_PORT PTB_H_HALF
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#define DIN_6_PIN 8u
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#define DIN_6_PORT PTB_H_HALF
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#define SPI2_CS0_PIN 9u
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#define SPI2_CS0_PORT PTB_H_HALF
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#define DIN_7_PIN 10u
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#define DIN_7_PORT PTB_H_HALF
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#define SPI2_MISO_PIN 11u
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#define SPI2_MISO_PORT PTB_H_HALF
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#define SPI2_MOSI_PIN 12u
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#define SPI2_MOSI_PORT PTB_H_HALF
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#define SPI2_SCK_PIN 13u
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#define SPI2_SCK_PORT PTB_H_HALF
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#define I2C1_SDA_PIN 8u
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#define I2C1_SDA_PORT PTD_L_HALF
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#define I2C1_SCL_PIN 9u
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#define I2C1_SCL_PORT PTD_L_HALF
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#define DOUT_4_PIN 13u
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#define DOUT_4_PORT PTA_L_HALF
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#define DOUT_6_PIN 15u
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#define DOUT_6_PORT PTA_L_HALF
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#define DOUT_7_PIN 0u
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#define DOUT_7_PORT PTA_H_HALF
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#define CAN2_RX_PIN 9u
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#define CAN2_RX_PORT PTE_H_HALF
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#define I2C0_SCL_PIN 14u
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#define I2C0_SCL_PORT PTD_L_HALF
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#define I2C0_SDA_PIN 13u
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#define I2C0_SDA_PORT PTD_L_HALF
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#define DIN_1_PIN 11u
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#define DIN_1_PORT PTA_L_HALF
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#define DOUT_3_PIN 2u
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#define DOUT_3_PORT PTA_H_HALF
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#define DIN_2_PIN 1u
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#define DIN_2_PORT PTE_L_HALF
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#define DOUT_1_PIN 10u
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#define DOUT_1_PORT PTE_H_HALF
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#define AIN_0_PIN 11u
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#define AIN_0_PORT PTE_L_HALF
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#define VRC_CTRL_PIN 10u
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#define VRC_CTRL_PORT PTE_L_HALF
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#define AIN_BAT_PIN 13u
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#define AIN_BAT_PORT PTE_L_HALF
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#define SPI1_MOSI_PIN 13u
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#define SPI1_MOSI_PORT PTA_H_HALF
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#ifdef __cplusplus
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}
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#endif
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/*!
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* @}
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*/
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#endif /* _SIUL2_PORT_IP_CFG_H_ */
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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