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ADM/GW/RTD/include/Adc_Sar_Ip_HeaderWrapper_S32K3.h
S2-CHICKEN 77297108b6 VCU C code first commit
2024-08-08 10:00:15 +09:00

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/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral : ADC_SAR
* Dependencies : none
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
#ifndef ADC_SAR_IP_HEADERWRAPPER_H
#define ADC_SAR_IP_HEADERWRAPPER_H
/**
* @file
*
* @addtogroup adc_sar_ip Adc Sar IPL
* @{
*/
#include "S32K344_ADC.h"
#include "S32K344_TEMPSENSE.h"
/*==================================================================================================
* SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define ADC_SAR_IP_VENDOR_ID_HEADERWRAPPER_H 43
#define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_H 4
#define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_H 4
#define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_H 0
#define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_H 0
#define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_H 9
#define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_H 0
/*==================================================================================================
* DEFINITIONS
==================================================================================================*/
#define ADC_SAR_IP_DEF_SAMPLE_TIME (0x16U) /* Default values for sample time. */
#define ADC_SAR_NUM_GROUP_CHAN (3U)
#define ADC_SAR_NUM_WDG_CHAN (8U)
#define ADC_SAR_CDR_COUNT (96U)
#define ADC_SAR_INSTANCE_COUNT (3U)
#define ADC_SAR_CWENR_COUNT (3U)
#define ADC_SAR_CEOCFR_COUNT (3U)
#define ADC_SAR_CIMR_COUNT (3U)
#define ADC_SAR_CTR_COUNT (3U)
#define ADC_SAR_NCMR_COUNT (3U)
#define ADC_SAR_JCMR_COUNT (3U)
#define ADC_SAR_DMAR_COUNT (3U)
#define ADC_SAR_AWORR_COUNT (3U)
#define ADC_SAR_THRHLR_COUNT ADC_THRHLR_COUNT
#define ADC_SAR_WTISR_CLEAR_MASK (0xFFFFFFFFU)
#define ADC_CWSELR_COUNT (3U)
#define ADC_MAX_RESOLUTION (14U)
#define ADC_HAS_THRHLR_ARRAY (1U)
#define ADC_HAS_CWSELR_UNROLLED (0U)
#define ADC_CALIBRATION_USES_MCR (0U)
#define ADC_PRESAMPLE_VREFL (0U)
#define ADC_PRESAMPLE_VREFH (1U)
#define FEATURE_ADC_BAD_ACCESS_PROT_FEATURE (1U)
#define FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL (1U)
#define FEATURE_ADC_HAS_CTU_TRIGGER_MODE (1U)
#define FEATURE_ADC_HAS_EXT_TRIGGER (1U)
#define FEATURE_ADC_HAS_INJ_EXT_TRIGGER (1U)
#define FEATURE_ADC_HAS_CTU (1U)
#define FEATURE_ADC_HAS_CLKSEL_EXTENDED (1U)
#define FEATURE_ADC_SAR_DECODE_DELAY (1U)
#define FEATURE_ADC_HAS_AVERAGING (1U)
#define FEATURE_ADC_SAR_W1C_ABORT (1U)
#define FEATURE_ADC_HAS_TEMPSENSE_CHN (1U)
#define FEATURE_ADC_SELFTEST_FULL_CLK (0U)
/* 31-28 3-0 63-60 35-32 95-92 67-64
\_/ \_/ \_/ \_/ \_/ \_/
|......| |......| |......| */
#define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00C7FFFFU, 0xFFFFFFFFU}, /* 0 */ \
{0x000000FFU, 0x00C3FFFFU, 0xFFFFFFFFU}, /* 1 */ \
{0x000000FFU, 0x00C3FFFFU, 0x00000000U}, /* 2 */ \
}
/* Adc Channels are divided into 3 Groups. */
/* This array shows max number of channels of each group. */
/* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */
/* Should be same with ADC_CDRx_COUNT in header file (from Base) */
#define FEATURE_ADC_MAX_CHN_COUNT {{8U, 24U, 32U}, /* Adc HW Unit 0 */ \
{8U, 24U, 32U}, /* Adc HW Unit 1 */ \
{8U, 24U, 0U}, /* Adc HW Unit 2 */ \
}
/* Bit0: DSDR is available
Bit1: PSCR is available
Bit2: CTU is available */
#define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x00000007U, /* Adc HW Unit 0 */ \
0x00000007U, /* Adc HW Unit 1 */ \
0x00000006U, /* Adc HW Unit 2 */ \
}
/* Register access defines */
#define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)]))))
#define CEOCFR(base, regIndex) REG_ACCESS(base->CEOCFR0, (regIndex))
#define CIMR(base, regIndex) REG_ACCESS(base->CIMR0, (regIndex))
#define DMAR(base, regIndex) REG_ACCESS(base->DMAR0, (regIndex))
#define PSR(base, regIndex) REG_ACCESS(base->PSR0, (regIndex))
#define CTR(base, regIndex) REG_ACCESS(base->CTR0, (regIndex))
#define NCMR(base, regIndex) REG_ACCESS(base->NCMR0, (regIndex))
#define JCMR(base, regIndex) REG_ACCESS(base->JCMR0, (regIndex))
#define CDR(base, chanIndex) REG_ACCESS(base->PCDR[0U], (chanIndex))
#define CWSELR(base, regIndex) REG_ACCESS(base->CWSELRPI[0U], (regIndex))
#define CWENR(base, regIndex) REG_ACCESS(base->CWENR0, (regIndex))
#define AWORR(base, regIndex) REG_ACCESS(base->AWORR0, (regIndex))
/* MCR */
#define ADC_MCR_CTU_MODE(x) ADC_MCR_BCTU_MODE(x)
#define ADC_MCR_CTUEN_MASK ADC_MCR_BCTUEN_MASK
#define ADC_MCR_CTUEN(x) ADC_MCR_BCTUEN(x)
/* MSR */
#define ADC_MSR_CTUSTART_MASK ADC_MSR_BCTUSTART_MASK
/* ISR */
#define ADC_ISR_EOCTU_MASK ADC_ISR_EOBCTU_MASK
#define ADC_ISR_EOCTU(x) ADC_ISR_EOBCTU(x)
/* IMR */
#define ADC_IMR_MSKEOCTU_MASK ADC_IMR_MSKEOBCTU_MASK
#define ADC_IMR_MSKEOCTU(x) ADC_IMR_MSKEOBCTU(x)
/* PSR */
#define ADC_PSR_PRES1_SHIFT ADC_PSR0_PRES1_SHIFT
/* CTR */
#define ADC_CTR_INPSAMP(x) ADC_CTR0_INPSAMP(x)
/* NCMR */
#define ADC_NCMR_CH0(x) ADC_NCMR0_CH0(x)
/* CDR */
#define ADC_CDR_CDATA_MASK ADC_PCDR_CDATA_MASK
#define ADC_CDR_CDATA_SHIFT ADC_PCDR_CDATA_SHIFT
#define ADC_CDR_CDATA_WIDTH ADC_PCDR_CDATA_WIDTH
#define ADC_CDR_RESULT_MASK ADC_PCDR_RESULT_MASK
#define ADC_CDR_RESULT(x) ADC_PCDR_RESULT(x)
#define ADC_CDR_OVERW_MASK ADC_PCDR_OVERW_MASK
#define ADC_CDR_OVERW_SHIFT ADC_PCDR_OVERW_SHIFT
#define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK
/* CWSELR */
#define ADC_CWSELR_WSEL_CH0_MASK ADC_CWSELRPI_WSEL_SI0_0_MASK
#define ADC_CWSELR_WSEL_CH0(x) ADC_CWSELRPI_WSEL_SI0_0(x)
#define ADC_CWSELR_WSEL_CH1_MASK ADC_CWSELRPI_WSEL_SI0_1_MASK
#define ADC_CWSELR_WSEL_CH1(x) ADC_CWSELRPI_WSEL_SI0_1(x)
#define ADC_CWSELR_WSEL_CH2_MASK ADC_CWSELRPI_WSEL_SI0_2_MASK
#define ADC_CWSELR_WSEL_CH2(x) ADC_CWSELRPI_WSEL_SI0_2(x)
#define ADC_CWSELR_WSEL_CH3_MASK ADC_CWSELRPI_WSEL_SI0_3_MASK
#define ADC_CWSELR_WSEL_CH3(x) ADC_CWSELRPI_WSEL_SI0_3(x)
#define ADC_CWSELR_WSEL_CH4_MASK ADC_CWSELRPI_WSEL_SI0_4_MASK
#define ADC_CWSELR_WSEL_CH4(x) ADC_CWSELRPI_WSEL_SI0_4(x)
#define ADC_CWSELR_WSEL_CH5_MASK ADC_CWSELRPI_WSEL_SI0_5_MASK
#define ADC_CWSELR_WSEL_CH5(x) ADC_CWSELRPI_WSEL_SI0_5(x)
#define ADC_CWSELR_WSEL_CH6_MASK ADC_CWSELRPI_WSEL_SI0_6_MASK
#define ADC_CWSELR_WSEL_CH6(x) ADC_CWSELRPI_WSEL_SI0_6(x)
#define ADC_CWSELR_WSEL_CH7_MASK ADC_CWSELRPI_WSEL_SI0_7_MASK
#define ADC_CWSELR_WSEL_CH7(x) ADC_CWSELRPI_WSEL_SI0_7(x)
/* USROFSGN - Offset and Gain User */
#define ADC_USER_OFFSET_GAIN_REG OFSGNUSR
#define ADC_USER_OFFSET(x) ADC_OFSGNUSR_OFFSET_USER(x)
#define ADC_USER_GAIN(x) ADC_OFSGNUSR_GAIN_USER(x)
/* Tempsense module */
#define TEMPSENSE_ADC_CHANNEL (49U)
#define TEMPSENSE_RESOLUTION (12U)
#define TEMPSENSE_RESOLUTION_12B (4096U)
#define TEMPSENSE_SIGN_MASK (0x8000U)
#define TEMPSENSE_INTEGER_MASK (0x7FF0U)
#define TEMPSENSE_INTEGER_SHIFT (4U)
#define TEMPSENSE_DECIMAL_MASK (0xFU)
#define TEMPSENSE_MULTIPLIER (100U)
/* Resolution of the result written by the ADC module */
#define ADC_RESULT_RESOLUTION (15U)
/** @} */
#endif /* ADC_SAR_IP_HEADERWRAPPER_H */
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