smbae/ADM
1
0
Fork 0
mirror of https://github.com/Dev-KATECH/ADM.git synced 2026-05-17 01:43:59 +09:00
Code Issues Actions Packages Projects Releases Wiki Activity
main
ADM/GW/RTD/include/Clock_Ip_Specific.h
S2-CHICKEN 77297108b6 VCU C code first commit
2024-08-08 10:00:15 +09:00

356 lines
15 KiB
C
Raw Permalink Blame History

/*==================================================================================================
* Project : RTD AUTOSAR 4.4
* Platform : CORTEXM
* Peripheral :
* Dependencies : none
*
* Autosar Version : 4.4.0
* Autosar Revision : ASR_REL_4_4_REV_0000
* Autosar Conf.Variant :
* SW Version : 0.9.0
* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
* (c) Copyright 2020 - 2021 NXP Semiconductors
* All Rights Reserved.
*
* NXP Confidential. This software is owned or controlled by NXP and may only be
* used strictly in accordance with the applicable license terms. By expressly
* accepting such terms or by downloading, installing, activating and/or otherwise
* using the software, you are agreeing that you have read, and that you agree to
* comply with and are bound by, such license terms. If you do not agree to be
* bound by the applicable license terms, then you may not retain, install,
* activate or otherwise use the software.
==================================================================================================*/
/**
* @file Clock_Ip_Specific.h
* @version 0.9.0
*
* @brief CLOCK IP specific header file.
* @details CLOCK IP specific header file.
* @addtogroup CLOCK_DRIVER Clock Ip Driver
* @{
*/
#if !defined(SPECIFIC_CLOCK_S32K344_H)
#define SPECIFIC_CLOCK_S32K344_H
#include "S32K344_COMMON.h"
#include "S32K344_MC_CGM.h"
#include "S32K344_FIRC.h"
#include "S32K344_SIRC.h"
#include "S32K344_FXOSC.h"
#include "S32K344_SXOSC.h"
#include "S32K344_PLL.h"
#include "S32K344_MC_ME.h"
#include "S32K344_PRAMC.h"
#include "S32K344_FLASH.h"
#include "S32K344_CMU_FC.h"
#include "S32K344_SYSTICK.h"
#include "S32K344_EMIOS.h"
#include "S32K344_RTC.h"
#include <stdbool.h>
#include <stddef.h>
#include "Mcal.h"
/*==================================================================================================
SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define CLOCK_IP_SPECIFIC_VENDOR_ID 43
#define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION 4
#define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION 4
#define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION 0
#define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION 0
#define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION 9
#define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION 0
/*==================================================================================================
FILE VERSION CHECKS
==================================================================================================*/
/* Check if Clock_Ip_Specific.h file and Mcal.h file have same versions */
#if (CLOCK_IP_SPECIFIC_VENDOR_ID != MCAL_VENDOR_ID)
#error "Clock_Ip_Specific.h and Mcal.h have different vendor IDs"
#endif
/* Check if Clock_Ip_Specific.h file and Mcal.h file are of the same Autosar version */
#if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
(CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION) || \
(CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != MCAL_AR_RELEASE_REVISION_VERSION))
#error "AutoSar Version Numbers of Clock_Ip_Specific.h and Mcal.h are different"
#endif
/* Check if Clock_Ip_Specific.h file and Mcal.h file are of the same Software version */
#if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION != MCAL_SW_MAJOR_VERSION) || \
(CLOCK_IP_SPECIFIC_SW_MINOR_VERSION != MCAL_SW_MINOR_VERSION) || \
(CLOCK_IP_SPECIFIC_SW_PATCH_VERSION != MCAL_SW_PATCH_VERSION))
#error "Software Version Numbers of Clock_Ip_Specific.h and Mcal.h are different"
#endif
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
#define CALC_FREQ_CALLBACKS_NO 35U
#define CONSUMER_CALLBACKS_COUNT FEATURE_CLOCK_CONSUMER_COUNT
#define SELECTOR_HARDWARE_VALUES_NO 32U
#define PCFS_ENTRIES_NO 1U
#define PCFS_PLLPHI0 0U
#define CMU_ENTRIES_NO 4U
#define DIVIDER_CALLBACKS_COUNT 5U
#define CGM_X_DE_DIV_STAT_WITHOUT_PHASE 1U
#define CGM_X_DE_DIV_STAT_WITH_PHASE 2U
#define PLL_PLL0DIV_DE_DIV_OUTPUT 3U
#define PLL_PLLDV_ODIV2_OUTPUT 4U
#define DIVIDERTRIGGER_CALLBACKS_COUNT 2U
#define CGM_X_DIV_TRIG_CTRL_TCTL_HHEN_UPD_STAT 1U
#define XOSC_CALLBACKS_COUNT 3U
#define FXOSC_OSCON_BYP_EOCV_GM_SEL 1U
#define SXOSC_OSCON_EOCV 2U
#define IRCOSC_CALLBACKS_COUNT 3U
#define FIRC_STDBY_ENABLE 1U
#define SIRC_STDBY_ENABLE 2U
#define GATE_CALLBACKS_COUNT 2U
#define MC_ME_PARTITION_COFB_ENABLE_REQUEST 1U
#define FRACTIONAL_DIVIDER_CALLBACKS_COUNT 1U
#define PLL_CALLBACKS_COUNT 2U
#define PLL_RDIV_MFI_MFN_ODIV2_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE 1U
#define NUMBER_OF_HARDWARE_PLL 1U
#define SELECTOR_CALLBACKS_COUNT 4U
#define CGM_X_CSC_CSS_CLK_SW_SWIP 1U
#define CGM_X_CSC_CSS_CLK_SW_RAMPDOWN_RAMPUP_SWIP 2U
#define CGM_X_CSC_CSS_CS_GRIP 3U
#define PCFS_CALLBACKS_COUNT 2U
#define CGM_X_PCFS_SDUR_DIVC_DIVE_DIVS 1U
#define CMU_CALLBACKS_COUNT 2U
#define CMU_FC_FCE_REF_CNT_LFREF_HFREF 1U
#define ALL_CALLBACKS_COUNT 9U
#define MC_CGM_MUX_MUX_DIV_COUNT 7u
typedef struct {
uint32 CSC;
const uint32 CSS;
uint32 divider[MC_CGM_MUX_MUX_DIV_COUNT];
uint8 RESERVED_0[16];
uint32 MUX_DIV_TRIG_CTRL; /**< Clock Mux 0 Divider Trigger Control Register, offset: 0x334 */
uint32 MUX_DIV_TRIG; /**< Clock Mux 0 Divider Trigger Register, offset: 0x338 */
const uint32 MUX_DIV_UPD_STAT;
}cgmMux_Type;
#define MC_CGM_PCFS_COUNT 8u
typedef struct {
volatile uint32 PCFS_SDUR; /**< PCFS Step Duration, offset: 0x0 */
struct { /* offset: 0x4, array step: 0xC */
volatile uint32 DIVC; /**< PCFS Divider Change 8 Register, array offset: 0x4, array step: 0xC */
volatile uint32 DIVE; /**< PCFS Divider End 8 Register, array offset: 0x8, array step: 0xC */
volatile uint32 DIVS; /**< PCFS Divider Start 8 Register, array offset: 0xC, array step: 0xC */
} PCFS[MC_CGM_PCFS_COUNT];
}cgmPcfs_Type;
#define PRTN_COFB_NO 4u
typedef struct {
uint32 PRTN_COFB_CLKEN[PRTN_COFB_NO];
}setMcmePartition_Type;
typedef struct {
uint32 PRTN_COFB_STAT[PRTN_COFB_NO];
}getMcmePartition_Type;
typedef struct {
uint32 PRTN_PCONF;
uint32 PRTN_PUPD;
const uint32 PRTN_STAT;
}triggerMcmePartition_Type;
typedef struct{
Clock_Ip_NameType name; /* Name of the clock source that supports pcfs (ramp up / ramp down) */
uint8 configIndex;
uint32 sdur;
uint32 divc_init;
uint32 divc_rate;
uint32 div_startValue;
uint32 div_endValue;
}pcfsEntry;
typedef struct{
Clock_Ip_NameType name; /* Name of the clock that can be monitored/supports cmu (clock monitor) */
uint8 configIndex;
uint32 enable;
uint32 refCount;
uint32 hfRef;
uint32 lfRef;
}cmuEntry;
/** XOSC - Register Layout Typedef */
typedef struct {
uint32 CTRL; /**< XOSC Control Register, offset: 0x0 */
const uint32 STAT; /**< Oscillator Status Register, offset: 0x4 */
} ExtOSC_Type;
/** CMU - Register Layout Typedef */
typedef struct {
uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */
uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */
uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */
uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */
uint32_t SR; /**< Status Register, offset: 0x10 */
uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */
} ClockMonitor_Type;
#define MC_CGM_instances_count 1U
#define MC_CGM_muxs_count 12U
#define XOSC_INSTANCES_ARRAY_SIZE 2U
#define PLL_INSTANCES_ARRAY_SIZE 1U
#define CMU_INSTANCES_ARRAY_SIZE 4U
#define MC_ME_partitions_count 3U
#define MC_CGM_MUX_DC_DE_MASK MC_CGM_MUX_0_DC_0_DE_MASK
#define MC_CGM_MUX_DC_DE_SHIFT MC_CGM_MUX_0_DC_0_DE_SHIFT
#define MC_CGM_MUX_DC_DIV_MASK MC_CGM_MUX_6_DC_0_DIV_MASK
#define MC_CGM_MUX_DC_DIV_SHIFT MC_CGM_MUX_6_DC_0_DIV_SHIFT
#define MC_CGM_MUX_DC_DIV(x) MC_CGM_MUX_6_DC_0_DIV(x)
#define MC_CGM_MUX_CSS_SELSTAT_MASK MC_CGM_MUX_5_CSS_SELSTAT_MASK
#define MC_CGM_MUX_CSS_SELSTAT_SHIFT MC_CGM_MUX_5_CSS_SELSTAT_SHIFT
#define MC_CGM_MUX_CSC_SELCTL(x) MC_CGM_MUX_5_CSC_SELCTL(x)
#define MC_CGM_MUX_CSC_SELCTL_MASK MC_CGM_MUX_5_CSC_SELCTL_MASK
#define MC_CGM_MUX_CSC_SELCTL_SHIFT MC_CGM_MUX_5_CSC_SELCTL_SHIFT
#define MC_CGM_MUX_CSC_SAFE_SW_MASK MC_CGM_MUX_0_CSS_SAFE_SW_MASK
#define MC_CGM_MUX_CSC_CLK_SW_MASK MC_CGM_MUX_0_CSC_CLK_SW_MASK
#define MC_CGM_MUX_CSC_RAMPUP_MASK MC_CGM_MUX_0_CSC_RAMPUP_MASK
#define MC_CGM_MUX_CSC_RAMPDOWN_MASK MC_CGM_MUX_0_CSC_RAMPDOWN_MASK
#define MC_CGM_MUX_CSS_SWIP_MASK MC_CGM_MUX_0_CSS_SWIP_MASK
#define MC_CGM_MUX_CSS_SWIP_IN_PROGRESS MC_CGM_MUX_CSS_SWIP_MASK
#define MC_CGM_MUX_CSS_SWTRG_MASK MC_CGM_MUX_0_CSS_SWTRG_MASK
#define MC_CGM_MUX_CSS_SWTRG_SHIFT MC_CGM_MUX_0_CSS_SWTRG_SHIFT
#define MC_CGM_MUX_CSS_SWTRG_SUCCEEDED 1U
#define MC_CGM_MUX_CSS_CLK_SW_MASK MC_CGM_MUX_0_CSS_CLK_SW_MASK
#define MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED 0U
#define MC_CGM_MUX_CSC_CG_MASK MC_CGM_MUX_5_CSC_CG_MASK
#define MC_CGM_MUX_CSC_FCG_MASK MC_CGM_MUX_5_CSC_FCG_MASK
#define MC_CGM_MUX_CSS_CS_MASK MC_CGM_MUX_5_CSS_CS_MASK
#define MC_CGM_MUX_CSS_CS_TRANSPARENT MC_CGM_MUX_CSS_CS_MASK
#define MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK
#define MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK
#define MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL_MASK
#define MC_CGM_MUX_DIV_TRIG_TRIGGER(x) MC_CGM_MUX_0_DIV_TRIG_CTRL_TCTL(x)
#define MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK
#define MC_CGM_MUX_DC_PHASE_MASK 0xFFU
#define MC_CGM_MUX_DC_PHASE_SHIFT 0x0U
#define MC_CGM_MUX_DC_PHASE(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_DC_PHASE_SHIFT)) & MC_CGM_MUX_DC_PHASE_MASK)
#define MC_CGM_PCFS_DIVC_INIT(x) MC_CGM_PCFS_DIVC8_INIT(x)
#define MC_CGM_PCFS_DIVC_RATE(x) MC_CGM_PCFS_DIVC8_RATE(x)
#define MC_CGM_PCFS_DIVE_DIVE(x) MC_CGM_PCFS_DIVE8_DIVE(x)
#define MC_CGM_PCFS_DIVS_DIVS(x) MC_CGM_PCFS_DIVS8_DIVS(x)
#define CMU_FREQUENCY_CHECK_ENABLED CMU_FC_GCR_FCE_MASK
#define CMU_FREQUENCY_CHECK_STOPPED 0U
#define CMU_ISR_MASK 3U
#define CMU_RESET_COUNTER_VALUE 0U
#define CMU_RESET_LOW_LIMIT 0U
#define CMU_RESET_HIGH_LIMIT 0xffffffU
/** @brief Clock start constant section data */
#define MCU_START_SEC_CONST_UNSPECIFIED
#include "Mcu_MemMap.h"
extern volatile cgmMux_Type* const cgm[MC_CGM_instances_count][MC_CGM_muxs_count];
extern volatile cgmPcfs_Type* const cgmPcfs[MC_CGM_instances_count];
extern volatile ExtOSC_Type* const xosc[XOSC_INSTANCES_ARRAY_SIZE];
extern volatile PLL_Type* const pll[PLL_INSTANCES_ARRAY_SIZE];
extern volatile ClockMonitor_Type * const cmu[CMU_INSTANCES_ARRAY_SIZE];
extern volatile setMcmePartition_Type* const mcmeSetPartitions[MC_ME_partitions_count];
extern volatile const getMcmePartition_Type* const mcmeGetPartitions[MC_ME_partitions_count];
extern volatile triggerMcmePartition_Type* const mcmeTriggerPartitions[MC_ME_partitions_count];
/** @brief Clock stop constant section data */
#define MCU_STOP_SEC_CONST_UNSPECIFIED
#include "Mcu_MemMap.h"
/** @brief Clock start initialized section data */
#define MCU_START_SEC_VAR_INIT_UNSPECIFIED
#include "Mcu_MemMap.h"
extern pcfsEntry pcfsEntries[PCFS_ENTRIES_NO];
extern cmuEntry cmuEntries[CMU_ENTRIES_NO];
/** @brief Clock stop initialized section data */
#define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
#include "Mcu_MemMap.h"
/*==================================================================================================
* FUNCTION PROTOTYPES
==================================================================================================*/
/** @brief Clock start section code */
#define MCU_START_SEC_CODE
#include "Mcu_MemMap.h"
#if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
#if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
void SpecificSetUserAccessAllowed(void);
#endif
#endif
void McMeEnterKey(void);
/** @brief Clock stop section code */
#define MCU_STOP_SEC_CODE
#include "Mcu_MemMap.h"
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*! @}*/
#endif /* SPECIFIC_CLOCK_S32K344_H */
/*******************************************************************************
* EOF
******************************************************************************/
Reference in New Issue View Git Blame Copy Permalink