mirror of
https://github.com/Dev-KATECH/ADM.git
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173 lines
8.0 KiB
C
173 lines
8.0 KiB
C
/*==================================================================================================
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* Project : RTD AUTOSAR 4.4
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* Platform : CORTEXM
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* Peripheral : SIUL2
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* Dependencies : none
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*
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* Autosar Version : 4.4.0
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* Autosar Revision : ASR_REL_4_4_REV_0000
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* Autosar Conf.Variant :
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* SW Version : 0.9.0
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* Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
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*
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* (c) Copyright 2020 - 2021 NXP Semiconductors
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* All Rights Reserved.
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*
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* NXP Confidential. This software is owned or controlled by NXP and may only be
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* used strictly in accordance with the applicable license terms. By expressly
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* accepting such terms or by downloading, installing, activating and/or otherwise
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* using the software, you are agreeing that you have read, and that you agree to
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* comply with and are bound by, such license terms. If you do not agree to be
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* bound by the applicable license terms, then you may not retain, install,
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* activate or otherwise use the software.
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==================================================================================================*/
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#ifndef SIUL2_PORT_IP_DEFINES
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#define SIUL2_PORT_IP_DEFINES
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/**
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* @file Siul2_Port_Ip_Defines.h
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*
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* @addtogroup Port_CFG
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* @{
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*/
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*==================================================================================================
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* INCLUDE FILES
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* 1) system and project includes
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* 2) needed interfaces from external units
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* 3) internal and external interfaces from this unit
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==================================================================================================*/
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/*==================================================================================================
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* SOURCE FILE VERSION INFORMATION
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==================================================================================================*/
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#define SIUL2_PORT_IP_DEFINES_VENDOR_ID_H 43
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#define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MAJOR_VERSION_H 4
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#define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MINOR_VERSION_H 4
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#define SIUL2_PORT_IP_DEFINES_AR_RELEASE_REVISION_VERSION_H 0
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#define SIUL2_PORT_IP_DEFINES_SW_MAJOR_VERSION_H 0
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#define SIUL2_PORT_IP_DEFINES_SW_MINOR_VERSION_H 9
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#define SIUL2_PORT_IP_DEFINES_SW_PATCH_VERSION_H 0
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/*==================================================================================================
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* FILE VERSION CHECKS
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==================================================================================================*/
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/*==================================================================================================
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* CONSTANTS
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==================================================================================================*/
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/*==================================================================================================
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* DEFINES AND MACROS
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==================================================================================================*/
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/* S32K3XX */
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#define SIUL2_PORT_IP_S32K3XX_PLATFORM
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/**
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* @brief Number of SIUL2 instances present on the subderivative
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*/
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#define SIUL2_NUM_SIUL2_INSTANCES_U8 (1)
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/*! @brief SIUL2 module has DSE bit */
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#define FEATURE_SIUL2_PORT_IP_HAS_DRIVE_STRENGTH
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/*! @brief SIUL2 module has IFE bit */
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#define FEATURE_SIUL2_PORT_IP_HAS_INPUT_FILTER
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/*! @brief SIUL2 module has PKE bit */
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#define FEATURE_SIUL2_PORT_IP_HAS_PULL_KEEPER
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/*! @brief SIUL2 module has INV bit */
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#define FEATURE_SIUL2_PORT_IP_HAS_INVERT_DATA
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/**
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* @brief Macros defined for the SIUL2 IPV that are protected.
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*/
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#define MCAL_SIUL2_REG_PROT_AVAILABLE (STD_ON)
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/**
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* @brief Macros defined for the protection size
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*/
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#define SIUL2_PROT_MEM_U32 ((uint32)0x00000008UL)
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/**
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* @brief Support for User mode.
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* If this parameter has been configured to STD_ON, the PORT driver code can be executed from both supervisor and user mode.
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*/
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#define PORT_ENABLE_USER_MODE_SUPPORT (STD_OFF)
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#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
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#ifdef PORT_ENABLE_USER_MODE_SUPPORT
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#if (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT)
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#error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Port in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
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#endif /* (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT) */
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#endif /* ifdef PORT_ENABLE_USER_MODE_SUPPORT*/
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#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */
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/* Pre-processor switch to enable/disable development error detection for Siul2 Ip API */
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#define SIUL2_PORT_IP_DEV_ERROR_DETECT (STD_OFF)
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/* Pre-processor switch to enable/disable VirtWrapper support */
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#define PORT_VIRTWRAPPER_SUPPORT (STD_OFF)
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#define SIUL2_MSCR_BASE (SIUL2->MSCR)
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/** SIUL2 */
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/** Peripheral PORTA_L_HALF base pointer */
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#define PORTA_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x00))
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/** Peripheral PORTA_H_HALF base pointer */
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#define PORTA_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x10))
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/** Peripheral PORTB_L_HALF base pointer */
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#define PORTB_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x20))
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/** Peripheral PORTB_H_HALF base pointer */
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#define PORTB_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x30))
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/** Peripheral PORTC_L_HALF base pointer */
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#define PORTC_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x40))
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/** Peripheral PORTC_H_HALF base pointer */
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#define PORTC_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x50))
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/** Peripheral PORTD_L_HALF base pointer */
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#define PORTD_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x60))
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/** Peripheral PORTD_H_HALF base pointer */
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#define PORTD_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x70))
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/** Peripheral PORTE_L_HALF base pointer */
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#define PORTE_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x80))
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/** Peripheral PORTE_H_HALF base pointer */
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#define PORTE_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x90))
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/** Peripheral PORTF_L_HALF base pointer */
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#define PORTF_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xA0))
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/** Peripheral PORTF_H_HALF base pointer */
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#define PORTF_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xB0))
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/** Peripheral PORTG_L_HALF base pointer */
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#define PORTG_L_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xC0))
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/** Peripheral PORTG_H_HALF base pointer */
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#define PORTG_H_HALF ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xD0))
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/*==================================================================================================
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* ENUMS
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==================================================================================================*/
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/*==================================================================================================
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* STRUCTURES AND OTHER TYPEDEFS
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==================================================================================================*/
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/*==================================================================================================
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* GLOBAL VARIABLE DECLARATIONS
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==================================================================================================*/
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/*==================================================================================================
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* FUNCTION PROTOTYPES
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==================================================================================================*/
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* SIUL2_PORT_IP_DEFINES */
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