mirror of
https://github.com/Dev-KATECH/ADM.git
synced 2026-05-17 09:53:59 +09:00
3minbe
85257c3f29
- Drive_Mode.c 수정 : bool 변수 삭제 - Drive_Mode.c/RcRequestCheck 함수 수정 : RC ACU 동시 요청 시 비상정지 : 마지막 요청을 RC_ModeReq에 저장하도록 수정 - Drive_Mode.c/ExecuteEmergencyMode 함수 수정 : VCU_Emergency_Flag 조건 추가 - VSCode에서 빌드 가능하도록 수정 : GW/Debug_STANDALONE 생성
2823 lines
101 KiB
C++
2823 lines
101 KiB
C++
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IPA constant propagation start:
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IPA structures before propagation:
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Jump functions:
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Jump functions of caller Sys_GetCoreID/77:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41:
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Jump functions of caller SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40:
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Jump functions of caller SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39:
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Jump functions of caller Spi_schm_read_msr/38:
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Propagating constants:
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 for cloning; -fipa-cp-clone disabled.
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Not considering SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 for cloning; -fipa-cp-clone disabled.
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Not considering Spi_schm_read_msr for cloning; -fipa-cp-clone disabled.
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overall_size: 650, max_new_size: 11001
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IPA lattices after all propagation:
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Lattices:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41:
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Node: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40:
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Node: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39:
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Node: Spi_schm_read_msr/38:
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IPA decision stage:
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IPA constant propagation end
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Reclaiming functions:
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Reclaiming variables:
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Clearing address taken flags:
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Symbol table:
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Sys_GetCoreID/77 (Sys_GetCoreID) @06c81ee0
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Type: function
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Visibility: external public
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References:
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Referring:
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Availability: not_available
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Function flags: optimize_size
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Called by: SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (1073741824 (estimated locally),1.00 per call) SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (1073741824 (estimated locally),1.00 per call) SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (1073741824 (estimated locally),1.00 per call)
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Calls:
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18) @06c819a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18) @06c81700
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)msr_SPI_EXCLUSIVE_AREA_18/36 (write)msr_SPI_EXCLUSIVE_AREA_18/36 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (read)reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17) @06c81460
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17) @06c811c0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)msr_SPI_EXCLUSIVE_AREA_17/34 (write)msr_SPI_EXCLUSIVE_AREA_17/34 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (read)reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16) @06c78d20
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16) @06c787e0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)msr_SPI_EXCLUSIVE_AREA_16/32 (write)msr_SPI_EXCLUSIVE_AREA_16/32 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (read)reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (write)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15) @06c782a0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)
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Referring:
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Availability: available
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Function flags: count:1073741824 (estimated locally) body optimize_size
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Called by:
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Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15) @06c78ee0
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Type: function definition analyzed
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Visibility: externally_visible public
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References: reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)msr_SPI_EXCLUSIVE_AREA_15/30 (write)msr_SPI_EXCLUSIVE_AREA_15/30 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (read)reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14) @06c78c40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14) @06c789a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)msr_SPI_EXCLUSIVE_AREA_14/28 (write)msr_SPI_EXCLUSIVE_AREA_14/28 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (read)reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13) @06c78700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13) @06c78460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)msr_SPI_EXCLUSIVE_AREA_13/26 (write)msr_SPI_EXCLUSIVE_AREA_13/26 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (read)reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12) @06c781c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12) @06c72d20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)msr_SPI_EXCLUSIVE_AREA_12/24 (write)msr_SPI_EXCLUSIVE_AREA_12/24 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (read)reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11) @06c727e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11) @06c722a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)msr_SPI_EXCLUSIVE_AREA_11/22 (write)msr_SPI_EXCLUSIVE_AREA_11/22 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (read)reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10) @06c72ee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10) @06c72c40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)msr_SPI_EXCLUSIVE_AREA_10/20 (write)msr_SPI_EXCLUSIVE_AREA_10/20 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (read)reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09) @06c729a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09) @06c72700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)msr_SPI_EXCLUSIVE_AREA_09/18 (write)msr_SPI_EXCLUSIVE_AREA_09/18 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (read)reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08) @06c72460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08) @06c721c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)msr_SPI_EXCLUSIVE_AREA_08/16 (write)msr_SPI_EXCLUSIVE_AREA_08/16 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (read)reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07) @06c6bd20
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07) @06c6b7e0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)msr_SPI_EXCLUSIVE_AREA_07/14 (write)msr_SPI_EXCLUSIVE_AREA_07/14 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (read)reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06) @06c6b2a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06) @06c6bee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)msr_SPI_EXCLUSIVE_AREA_06/12 (write)msr_SPI_EXCLUSIVE_AREA_06/12 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (read)reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05) @06c6bc40
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05) @06c6b9a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)msr_SPI_EXCLUSIVE_AREA_05/10 (write)msr_SPI_EXCLUSIVE_AREA_05/10 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (read)reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04) @06c6b700
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04) @06c6b460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)msr_SPI_EXCLUSIVE_AREA_04/8 (write)msr_SPI_EXCLUSIVE_AREA_04/8 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (read)reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03) @06c6b1c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03) @06b81ee0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)msr_SPI_EXCLUSIVE_AREA_03/6 (write)msr_SPI_EXCLUSIVE_AREA_03/6 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (read)reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02) @06b819a0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02) @06b81460
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)msr_SPI_EXCLUSIVE_AREA_02/4 (write)msr_SPI_EXCLUSIVE_AREA_02/4 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (read)reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01) @06b81e00
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01) @06b81b60
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)msr_SPI_EXCLUSIVE_AREA_01/2 (write)msr_SPI_EXCLUSIVE_AREA_01/2 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (read)reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00) @06b818c0
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00) @06b81620
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References: reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)msr_SPI_EXCLUSIVE_AREA_00/0 (write)msr_SPI_EXCLUSIVE_AREA_00/0 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (read)reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (write)
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls: Sys_GetCoreID/77 (1073741824 (estimated locally),1.00 per call)
|
|
Spi_schm_read_msr/38 (Spi_schm_read_msr) @06b81380
|
|
Type: function definition analyzed
|
|
Visibility: externally_visible public
|
|
References:
|
|
Referring:
|
|
Availability: available
|
|
Function flags: count:1073741824 (estimated locally) body optimize_size
|
|
Called by:
|
|
Calls:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_18/37 (reentry_guard_SPI_EXCLUSIVE_AREA_18) @06b7e1f8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_18/36 (msr_SPI_EXCLUSIVE_AREA_18) @06b7e168
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_17/35 (reentry_guard_SPI_EXCLUSIVE_AREA_17) @06b7e0d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_17/34 (msr_SPI_EXCLUSIVE_AREA_17) @06b7e048
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_16/33 (reentry_guard_SPI_EXCLUSIVE_AREA_16) @06b7af78
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_16/32 (msr_SPI_EXCLUSIVE_AREA_16) @06b7aee8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15/31 (reentry_guard_SPI_EXCLUSIVE_AREA_15) @06b7ae58
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_15/30 (msr_SPI_EXCLUSIVE_AREA_15) @06b7adc8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14/29 (reentry_guard_SPI_EXCLUSIVE_AREA_14) @06b7ad38
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_14/28 (msr_SPI_EXCLUSIVE_AREA_14) @06b7aca8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13/27 (reentry_guard_SPI_EXCLUSIVE_AREA_13) @06b7ac18
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_13/26 (msr_SPI_EXCLUSIVE_AREA_13) @06b7ab88
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12/25 (reentry_guard_SPI_EXCLUSIVE_AREA_12) @06b7aaf8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_12/24 (msr_SPI_EXCLUSIVE_AREA_12) @06b7aa68
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11/23 (reentry_guard_SPI_EXCLUSIVE_AREA_11) @06b7a9d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_11/22 (msr_SPI_EXCLUSIVE_AREA_11) @06b7a948
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10/21 (reentry_guard_SPI_EXCLUSIVE_AREA_10) @06b7a8b8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_10/20 (msr_SPI_EXCLUSIVE_AREA_10) @06b7a828
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09/19 (reentry_guard_SPI_EXCLUSIVE_AREA_09) @06b7a798
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_09/18 (msr_SPI_EXCLUSIVE_AREA_09) @06b7a708
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08/17 (reentry_guard_SPI_EXCLUSIVE_AREA_08) @06b7a678
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_08/16 (msr_SPI_EXCLUSIVE_AREA_08) @06b7a5e8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07/15 (reentry_guard_SPI_EXCLUSIVE_AREA_07) @06b7a558
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_07/14 (msr_SPI_EXCLUSIVE_AREA_07) @06b7a4c8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06/13 (reentry_guard_SPI_EXCLUSIVE_AREA_06) @06b7a438
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_06/12 (msr_SPI_EXCLUSIVE_AREA_06) @06b7a3a8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05/11 (reentry_guard_SPI_EXCLUSIVE_AREA_05) @06b7a318
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_05/10 (msr_SPI_EXCLUSIVE_AREA_05) @06b7a288
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04/9 (reentry_guard_SPI_EXCLUSIVE_AREA_04) @06b7a1f8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_04/8 (msr_SPI_EXCLUSIVE_AREA_04) @06b7a168
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03/7 (reentry_guard_SPI_EXCLUSIVE_AREA_03) @06b7a0d8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_03/6 (msr_SPI_EXCLUSIVE_AREA_03) @06b7a048
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02/5 (reentry_guard_SPI_EXCLUSIVE_AREA_02) @06b72f78
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_02/4 (msr_SPI_EXCLUSIVE_AREA_02) @06b72ee8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01/3 (reentry_guard_SPI_EXCLUSIVE_AREA_01) @06b72e58
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_01/2 (msr_SPI_EXCLUSIVE_AREA_01) @06b72dc8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00/1 (reentry_guard_SPI_EXCLUSIVE_AREA_00) @06b72d38
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
msr_SPI_EXCLUSIVE_AREA_00/0 (msr_SPI_EXCLUSIVE_AREA_00) @06b72ca8
|
|
Type: variable definition analyzed
|
|
Visibility: force_output prevailing_def_ironly
|
|
References:
|
|
Referring: SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (read)SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39 (write)SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40 (read)
|
|
Availability: available
|
|
Varpool flags:
|
|
|
|
;; Function Spi_schm_read_msr (Spi_schm_read_msr, funcdef_no=0, decl_uid=4192, cgraph_uid=1, symbol_order=38)
|
|
|
|
Modification phase of node Spi_schm_read_msr/38
|
|
Spi_schm_read_msr ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_1);
|
|
# DEBUG reg_tmp => reg_tmp_1
|
|
# DEBUG BEGIN_STMT
|
|
return reg_tmp_1;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00, funcdef_no=1, decl_uid=4076, cgraph_uid=2, symbol_order=39)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00/39
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00, funcdef_no=2, decl_uid=4078, cgraph_uid=3, symbol_order=40)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00/40
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01, funcdef_no=3, decl_uid=4080, cgraph_uid=4, symbol_order=41)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01/41
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01, funcdef_no=4, decl_uid=4082, cgraph_uid=5, symbol_order=42)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01/42
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02, funcdef_no=5, decl_uid=4084, cgraph_uid=6, symbol_order=43)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02/43
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02, funcdef_no=6, decl_uid=4086, cgraph_uid=7, symbol_order=44)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02/44
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03, funcdef_no=7, decl_uid=4088, cgraph_uid=8, symbol_order=45)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03/45
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03, funcdef_no=8, decl_uid=4090, cgraph_uid=9, symbol_order=46)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03/46
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04, funcdef_no=9, decl_uid=4092, cgraph_uid=10, symbol_order=47)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04/47
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04, funcdef_no=10, decl_uid=4094, cgraph_uid=11, symbol_order=48)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04/48
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05, funcdef_no=11, decl_uid=4096, cgraph_uid=12, symbol_order=49)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05/49
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05, funcdef_no=12, decl_uid=4098, cgraph_uid=13, symbol_order=50)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05/50
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06, funcdef_no=13, decl_uid=4100, cgraph_uid=14, symbol_order=51)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06/51
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06, funcdef_no=14, decl_uid=4102, cgraph_uid=15, symbol_order=52)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06/52
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07, funcdef_no=15, decl_uid=4104, cgraph_uid=16, symbol_order=53)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07/53
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07, funcdef_no=16, decl_uid=4106, cgraph_uid=17, symbol_order=54)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07/54
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08, funcdef_no=17, decl_uid=4108, cgraph_uid=18, symbol_order=55)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08/55
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08, funcdef_no=18, decl_uid=4110, cgraph_uid=19, symbol_order=56)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08/56
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09, funcdef_no=19, decl_uid=4112, cgraph_uid=20, symbol_order=57)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09/57
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09, funcdef_no=20, decl_uid=4114, cgraph_uid=21, symbol_order=58)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09/58
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10, funcdef_no=21, decl_uid=4116, cgraph_uid=22, symbol_order=59)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10/59
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10, funcdef_no=22, decl_uid=4118, cgraph_uid=23, symbol_order=60)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10/60
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11, funcdef_no=23, decl_uid=4120, cgraph_uid=24, symbol_order=61)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11/61
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11, funcdef_no=24, decl_uid=4122, cgraph_uid=25, symbol_order=62)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11/62
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12, funcdef_no=25, decl_uid=4124, cgraph_uid=26, symbol_order=63)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12/63
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_12[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12, funcdef_no=26, decl_uid=4126, cgraph_uid=27, symbol_order=64)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12/64
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13, funcdef_no=27, decl_uid=4128, cgraph_uid=28, symbol_order=65)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13/65
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_13[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13, funcdef_no=28, decl_uid=4130, cgraph_uid=29, symbol_order=66)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13/66
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14, funcdef_no=29, decl_uid=4132, cgraph_uid=30, symbol_order=67)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14/67
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_14[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14, funcdef_no=30, decl_uid=4134, cgraph_uid=31, symbol_order=68)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14/68
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15, funcdef_no=31, decl_uid=4136, cgraph_uid=32, symbol_order=69)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15/69
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_15[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15, funcdef_no=32, decl_uid=4138, cgraph_uid=33, symbol_order=70)
|
|
|
|
Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15/70
|
|
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15 ()
|
|
{
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
_3 = _2 + 4294967295;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10] ={v} _3;
|
|
# DEBUG BEGIN_STMT
|
|
_4 ={v} msr_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
_5 = _4 & 1;
|
|
if (_5 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId_10];
|
|
if (_6 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsie i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16, funcdef_no=33, decl_uid=4140, cgraph_uid=34, symbol_order=71)
|
|
|
|
Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16/71
|
|
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16 ()
|
|
{
|
|
register uint32 reg_tmp;
|
|
uint32 u32CoreId;
|
|
unsigned char _1;
|
|
long unsigned int _2;
|
|
long unsigned int _3;
|
|
long unsigned int _4;
|
|
long unsigned int _5;
|
|
long unsigned int _6;
|
|
|
|
<bb 2> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_1 = Sys_GetCoreID ();
|
|
u32CoreId_10 = (uint32) _1;
|
|
# DEBUG u32CoreId => u32CoreId_10
|
|
# DEBUG BEGIN_STMT
|
|
_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
|
|
if (_2 == 0)
|
|
goto <bb 3>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 3> [local count: 536870913]:
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG INLINE_ENTRY Spi_schm_read_msr
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
|
|
# DEBUG reg_tmp => reg_tmp_14
|
|
# DEBUG BEGIN_STMT
|
|
# DEBUG reg_tmp => NULL
|
|
msr_SPI_EXCLUSIVE_AREA_16[u32CoreId_10] ={v} reg_tmp_14;
|
|
# DEBUG BEGIN_STMT
|
|
_3 ={v} msr_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
|
|
_4 = _3 & 1;
|
|
if (_4 == 0)
|
|
goto <bb 4>; [50.00%]
|
|
else
|
|
goto <bb 5>; [50.00%]
|
|
|
|
<bb 4> [local count: 268435456]:
|
|
# DEBUG BEGIN_STMT
|
|
__asm__ __volatile__(" cpsid i");
|
|
|
|
<bb 5> [local count: 1073741824]:
|
|
# DEBUG BEGIN_STMT
|
|
_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
|
|
_6 = _5 + 1;
|
|
reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10] ={v} _6;
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16, funcdef_no=34, decl_uid=4142, cgraph_uid=35, symbol_order=72)
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Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16/72
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16 ()
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{
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uint32 u32CoreId;
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unsigned char _1;
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long unsigned int _2;
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long unsigned int _3;
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long unsigned int _4;
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long unsigned int _5;
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long unsigned int _6;
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<bb 2> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_1 = Sys_GetCoreID ();
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u32CoreId_10 = (uint32) _1;
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# DEBUG u32CoreId => u32CoreId_10
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# DEBUG BEGIN_STMT
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_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
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_3 = _2 + 4294967295;
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reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10] ={v} _3;
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# DEBUG BEGIN_STMT
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_4 ={v} msr_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
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_5 = _4 & 1;
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if (_5 == 0)
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goto <bb 3>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 3> [local count: 536870913]:
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_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId_10];
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if (_6 == 0)
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goto <bb 4>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 4> [local count: 268435456]:
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" cpsie i");
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<bb 5> [local count: 1073741824]:
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return;
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}
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;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17, funcdef_no=35, decl_uid=4144, cgraph_uid=36, symbol_order=73)
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Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17/73
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17 ()
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{
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register uint32 reg_tmp;
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uint32 u32CoreId;
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unsigned char _1;
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long unsigned int _2;
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long unsigned int _3;
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long unsigned int _4;
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long unsigned int _5;
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long unsigned int _6;
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<bb 2> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_1 = Sys_GetCoreID ();
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u32CoreId_10 = (uint32) _1;
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# DEBUG u32CoreId => u32CoreId_10
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# DEBUG BEGIN_STMT
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_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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if (_2 == 0)
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goto <bb 3>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 3> [local count: 536870913]:
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# DEBUG BEGIN_STMT
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# DEBUG INLINE_ENTRY Spi_schm_read_msr
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# DEBUG BEGIN_STMT
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
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# DEBUG reg_tmp => reg_tmp_14
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# DEBUG BEGIN_STMT
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# DEBUG reg_tmp => NULL
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msr_SPI_EXCLUSIVE_AREA_17[u32CoreId_10] ={v} reg_tmp_14;
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# DEBUG BEGIN_STMT
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_3 ={v} msr_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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_4 = _3 & 1;
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if (_4 == 0)
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goto <bb 4>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 4> [local count: 268435456]:
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" cpsid i");
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<bb 5> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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_6 = _5 + 1;
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reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10] ={v} _6;
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return;
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}
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;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17, funcdef_no=36, decl_uid=4146, cgraph_uid=37, symbol_order=74)
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Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17/74
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17 ()
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{
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uint32 u32CoreId;
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unsigned char _1;
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long unsigned int _2;
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long unsigned int _3;
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long unsigned int _4;
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long unsigned int _5;
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long unsigned int _6;
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<bb 2> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_1 = Sys_GetCoreID ();
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u32CoreId_10 = (uint32) _1;
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# DEBUG u32CoreId => u32CoreId_10
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# DEBUG BEGIN_STMT
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_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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_3 = _2 + 4294967295;
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reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10] ={v} _3;
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# DEBUG BEGIN_STMT
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_4 ={v} msr_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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_5 = _4 & 1;
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if (_5 == 0)
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goto <bb 3>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 3> [local count: 536870913]:
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_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId_10];
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if (_6 == 0)
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goto <bb 4>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 4> [local count: 268435456]:
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" cpsie i");
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<bb 5> [local count: 1073741824]:
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return;
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}
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;; Function SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 (SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18, funcdef_no=37, decl_uid=4148, cgraph_uid=38, symbol_order=75)
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Modification phase of node SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18/75
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SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18 ()
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{
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register uint32 reg_tmp;
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uint32 u32CoreId;
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unsigned char _1;
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long unsigned int _2;
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long unsigned int _3;
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long unsigned int _4;
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long unsigned int _5;
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long unsigned int _6;
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<bb 2> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_1 = Sys_GetCoreID ();
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u32CoreId_10 = (uint32) _1;
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# DEBUG u32CoreId => u32CoreId_10
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# DEBUG BEGIN_STMT
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_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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if (_2 == 0)
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goto <bb 3>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 3> [local count: 536870913]:
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# DEBUG BEGIN_STMT
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# DEBUG INLINE_ENTRY Spi_schm_read_msr
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# DEBUG BEGIN_STMT
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" mrs %0, primask " : "=r" reg_tmp_14);
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# DEBUG reg_tmp => reg_tmp_14
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# DEBUG BEGIN_STMT
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# DEBUG reg_tmp => NULL
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msr_SPI_EXCLUSIVE_AREA_18[u32CoreId_10] ={v} reg_tmp_14;
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# DEBUG BEGIN_STMT
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_3 ={v} msr_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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_4 = _3 & 1;
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if (_4 == 0)
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goto <bb 4>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 4> [local count: 268435456]:
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" cpsid i");
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<bb 5> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_5 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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_6 = _5 + 1;
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reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10] ={v} _6;
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return;
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}
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;; Function SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 (SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18, funcdef_no=38, decl_uid=4150, cgraph_uid=39, symbol_order=76)
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Modification phase of node SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18/76
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SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18 ()
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{
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uint32 u32CoreId;
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unsigned char _1;
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long unsigned int _2;
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long unsigned int _3;
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long unsigned int _4;
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long unsigned int _5;
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long unsigned int _6;
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<bb 2> [local count: 1073741824]:
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# DEBUG BEGIN_STMT
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_1 = Sys_GetCoreID ();
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u32CoreId_10 = (uint32) _1;
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# DEBUG u32CoreId => u32CoreId_10
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# DEBUG BEGIN_STMT
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_2 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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_3 = _2 + 4294967295;
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reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10] ={v} _3;
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# DEBUG BEGIN_STMT
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_4 ={v} msr_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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_5 = _4 & 1;
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if (_5 == 0)
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goto <bb 3>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 3> [local count: 536870913]:
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_6 ={v} reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId_10];
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if (_6 == 0)
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goto <bb 4>; [50.00%]
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else
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goto <bb 5>; [50.00%]
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<bb 4> [local count: 268435456]:
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# DEBUG BEGIN_STMT
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__asm__ __volatile__(" cpsie i");
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<bb 5> [local count: 1073741824]:
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return;
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}
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