/*================================================================================================== * Project : RTD AUTOSAR 4.4 * Platform : CORTEXM * Peripheral : DMA,CACHE,TRGMUX,LCU,EMIOS,FLEXIO * Dependencies : none * * Autosar Version : 4.4.0 * Autosar Revision : ASR_REL_4_4_REV_0000 * Autosar Conf.Variant : * SW Version : 0.9.0 * Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326 * * (c) Copyright 2020 - 2021 NXP Semiconductors * All Rights Reserved. * * NXP Confidential. This software is owned or controlled by NXP and may only be * used strictly in accordance with the applicable license terms. By expressly * accepting such terms or by downloading, installing, activating and/or otherwise * using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms. If you do not agree to be * bound by the applicable license terms, then you may not retain, install, * activate or otherwise use the software. ==================================================================================================*/ /* Prevention from multiple including the same header */ #ifndef FLEXIO_IP_CFG_DEFINES_H_ #define FLEXIO_IP_CFG_DEFINES_H_ #include "StandardTypes.h" #include "BasicTypes.h" /*=============================================================================================== DEFINES AND MACROS ===============================================================================================*/ /*-----------------------------------------------/ / FLEXIO HARDWARE INSTANCES / /-----------------------------------------------*/ #define FLEXIO_0 ((uint8)(0U)) /*-----------------------------------------------/ / FLEXIO HARDWARE CHANNELS / /-----------------------------------------------*/ #define CHANNEL_0 ((uint8)(0U)) #define CHANNEL_1 ((uint8)(1U)) #define CHANNEL_2 ((uint8)(2U)) #define CHANNEL_3 ((uint8)(3U)) #define CHANNEL_4 ((uint8)(4U)) #define CHANNEL_5 ((uint8)(5U)) #define CHANNEL_6 ((uint8)(6U)) #define CHANNEL_7 ((uint8)(7U)) /*-----------------------------------------------/ / FLEXIO PINS / /-----------------------------------------------*/ #define PIN_0 ((uint8)(0U)) #define PIN_1 ((uint8)(1U)) #define PIN_2 ((uint8)(2U)) #define PIN_3 ((uint8)(3U)) #define PIN_4 ((uint8)(4U)) #define PIN_5 ((uint8)(5U)) #define PIN_6 ((uint8)(6U)) #define PIN_7 ((uint8)(7U)) #define PIN_8 ((uint8)(8U)) #define PIN_9 ((uint8)(9U)) #define PIN_10 ((uint8)(10U)) #define PIN_11 ((uint8)(11U)) #define PIN_12 ((uint8)(12U)) #define PIN_13 ((uint8)(13U)) #define PIN_14 ((uint8)(14U)) #define PIN_15 ((uint8)(15U)) #define PIN_16 ((uint8)(16U)) #define PIN_17 ((uint8)(17U)) #define PIN_18 ((uint8)(18U)) #define PIN_19 ((uint8)(19U)) #define PIN_20 ((uint8)(20U)) #define PIN_21 ((uint8)(21U)) #define PIN_22 ((uint8)(22U)) #define PIN_23 ((uint8)(23U)) #define PIN_24 ((uint8)(24U)) #define PIN_25 ((uint8)(25U)) #define PIN_26 ((uint8)(26U)) #define PIN_27 ((uint8)(27U)) #define PIN_28 ((uint8)(28U)) #define PIN_29 ((uint8)(29U)) #define PIN_30 ((uint8)(30U)) #define PIN_31 ((uint8)(31U)) #endif /* #ifndef DMA_IP_CFG_DEFINES_H_ */ /*================================================================================================== * END OF FILE ==================================================================================================*/