/*================================================================================================== * Project : RTD AUTOSAR 4.4 * Platform : CORTEXM * Peripheral : * Dependencies : none * * Autosar Version : 4.4.0 * Autosar Revision : ASR_REL_4_4_REV_0000 * Autosar Conf.Variant : * SW Version : 0.9.0 * Build Version : S32K3_RTD_0_9_0_D2102_ASR_REL_4_4_REV_0000_20201127 * * (c) Copyright 2020 NXP Semiconductors * All Rights Reserved. * * NXP Confidential. This software is owned or controlled by NXP and may only be * used strictly in accordance with the applicable license terms. By expressly * accepting such terms or by downloading, installing, activating and/or otherwise * using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms. If you do not agree to be * bound by the applicable license terms, then you may not retain, install, * activate or otherwise use the software. ==================================================================================================*/ /** * @file Clock_Ip_Cfg_Defines.h * @version 0.9.0 * * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. * @details Code template for Post-Build(PB) configuration file generation. * * @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver * @{ */ #ifndef CLOCK_IP_CFG_DEFINES_H #define CLOCK_IP_CFG_DEFINES_H #ifdef __cplusplus extern "C"{ #endif /*================================================================================================== INCLUDE FILES 1) system and project includes 2) needed interfaces from external units 3) internal and external interfaces from this unit ==================================================================================================*/ /*================================================================================================== SOURCE FILE VERSION INFORMATION ==================================================================================================*/ #define CLOCK_IP_CFG_DEFINES_VENDOR_ID 43 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 4 #define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 #define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION 0 #define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION 9 #define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION 0 /*================================================================================================== DEFINES AND MACROS ==================================================================================================*/ /** * @brief Max number of internal oscillators */ #define FEATURE_CLOCK_IRCOSCS_COUNT (2U) /** * @brief Max number of external oscillators */ #define FEATURE_CLOCK_XOSCS_COUNT (2U) /** * @brief Max number of pll devices */ #define FEATURE_CLOCK_PLLS_COUNT (1U) /** * @brief Max number of selectors */ #define FEATURE_CLOCK_SELECTORS_COUNT (12U) /** * @brief Max number of dividers */ #define FEATURE_CLOCK_DIVIDERS_COUNT (21U) /** * @brief Max number of divider triggers */ #define FEATURE_CLOCK_DIVIDER_TRIGGERS_COUNT (1U) /** * @brief Max number of fractional dividers */ #define FEATURE_CLOCK_FRACTIONAL_DIVIDERS_COUNT (0U) /** * @brief Max number of external clocks */ #define FEATURE_CLOCK_EXT_CLKS_COUNT (2U) /** * @brief Max number of pcfs */ #define FEATURE_CLOCK_PCFS_COUNT (0U) /** * @brief Max number of clock gates */ #define FEATURE_CLOCK_GATES_COUNT (105U) /** * @brief Max number of clock monitoring units */ #define FEATURE_CLOCK_CMUS_COUNT (4U) /** * @brief Max number of specific peripheral (eMIOS) units */ #define FEATURE_CLOCK_SPECIFIC_PERIPH_COUNT (0U) /** * @brief Max number of consumer clocks */ #define FEATURE_CLOCK_CONSUMER_COUNT (123U) /** * @brief Supported power mode. */ #define FEATURE_CLOCK_IP_HAS_RUN_MODE 0U /** * @brief Supported clocks. */ #define FEATURE_CLOCK_IP_HAS_FIRC_CLK 0U #define FEATURE_CLOCK_IP_HAS_FIRC_STANDBY_CLK 1U #define FEATURE_CLOCK_IP_HAS_SIRC_CLK 2U #define FEATURE_CLOCK_IP_HAS_SIRC_STANDBY_CLK 3U #define FEATURE_CLOCK_IP_HAS_FXOSC_CLK 4U #define FEATURE_CLOCK_IP_HAS_SXOSC_CLK 5U #define FEATURE_CLOCK_IP_HAS_PLL_CLK 6U #define FEATURE_CLOCK_IP_HAS_PLL_POSTDIV_CLK 7U #define FEATURE_CLOCK_IP_HAS_PLL_PHI0_CLK 8U #define FEATURE_CLOCK_IP_HAS_PLL_PHI1_CLK 9U #define FEATURE_CLOCK_IP_HAS_EMAC_MII_RX_CLK 10U #define FEATURE_CLOCK_IP_HAS_EMAC_MII_RMII_TX_CLK 11U #define FEATURE_CLOCK_IP_HAS_SCS_CLK 12U #define FEATURE_CLOCK_IP_HAS_CORE_CLK 13U #define FEATURE_CLOCK_IP_HAS_AIPS_PLAT_CLK 14U #define FEATURE_CLOCK_IP_HAS_AIPS_SLOW_CLK 15U #define FEATURE_CLOCK_IP_HAS_HSE_CLK 16U #define FEATURE_CLOCK_IP_HAS_DCM_CLK 17U #define FEATURE_CLOCK_IP_HAS_LBIST_CLK 18U #define FEATURE_CLOCK_IP_HAS_QSPI_MEM_CLK 19U #define FEATURE_CLOCK_IP_HAS_CLKOUT_RUN_CLK 20U #define FEATURE_CLOCK_PRODUCERS_NO 21U #define FEATURE_CLOCK_IP_HAS_ADC0_CLK 22U #define FEATURE_CLOCK_IP_HAS_ADC1_CLK 23U #define FEATURE_CLOCK_IP_HAS_ADC2_CLK 24U #define FEATURE_CLOCK_IP_HAS_BCTU0_CLK 25U #define FEATURE_CLOCK_IP_HAS_CLKOUT_STANDBY_CLK 26U #define FEATURE_CLOCK_IP_HAS_CMP0_CLK 27U #define FEATURE_CLOCK_IP_HAS_CMP1_CLK 28U #define FEATURE_CLOCK_IP_HAS_CMP2_CLK 29U #define FEATURE_CLOCK_IP_HAS_CRC0_CLK 30U #define FEATURE_CLOCK_IP_HAS_DCM0_CLK 31U #define FEATURE_CLOCK_IP_HAS_DMAMUX0_CLK 32U #define FEATURE_CLOCK_IP_HAS_DMAMUX1_CLK 33U #define FEATURE_CLOCK_IP_HAS_EDMA0_CLK 34U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD0_CLK 35U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD10_CLK 36U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD11_CLK 37U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD12_CLK 38U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD13_CLK 39U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD14_CLK 40U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD15_CLK 41U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD16_CLK 42U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD17_CLK 43U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD18_CLK 44U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD19_CLK 45U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD1_CLK 46U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD20_CLK 47U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD21_CLK 48U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD22_CLK 49U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD23_CLK 50U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD24_CLK 51U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD25_CLK 52U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD26_CLK 53U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD27_CLK 54U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD28_CLK 55U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD29_CLK 56U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD2_CLK 57U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD30_CLK 58U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD31_CLK 59U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD3_CLK 60U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD4_CLK 61U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD5_CLK 62U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD6_CLK 63U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD7_CLK 64U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD8_CLK 65U #define FEATURE_CLOCK_IP_HAS_EDMA0_TCD9_CLK 66U #define FEATURE_CLOCK_IP_HAS_EIM0_CLK 67U #define FEATURE_CLOCK_IP_HAS_EMAC_RX_CLK 68U #define FEATURE_CLOCK_IP_HAS_EMAC0_RX_CLK 69U #define FEATURE_CLOCK_IP_HAS_EMAC_TS_CLK 70U #define FEATURE_CLOCK_IP_HAS_EMAC0_TS_CLK 71U #define FEATURE_CLOCK_IP_HAS_EMAC_TX_CLK 72U #define FEATURE_CLOCK_IP_HAS_EMAC0_TX_CLK 73U #define FEATURE_CLOCK_IP_HAS_EMIOS0_CLK 74U #define FEATURE_CLOCK_IP_HAS_EMIOS1_CLK 75U #define FEATURE_CLOCK_IP_HAS_EMIOS2_CLK 76U #define FEATURE_CLOCK_IP_HAS_ERM0_CLK 77U #define FEATURE_CLOCK_IP_HAS_FLASH0_CLK 78U #define FEATURE_CLOCK_IP_HAS_FLEXCANA_CLK 79U #define FEATURE_CLOCK_IP_HAS_FLEXCAN0_CLK 80U #define FEATURE_CLOCK_IP_HAS_FLEXCAN1_CLK 81U #define FEATURE_CLOCK_IP_HAS_FLEXCAN2_CLK 82U #define FEATURE_CLOCK_IP_HAS_FLEXCANB_CLK 83U #define FEATURE_CLOCK_IP_HAS_FLEXCAN3_CLK 84U #define FEATURE_CLOCK_IP_HAS_FLEXCAN4_CLK 85U #define FEATURE_CLOCK_IP_HAS_FLEXCAN5_CLK 86U #define FEATURE_CLOCK_IP_HAS_FLEXIO0_CLK 87U #define FEATURE_CLOCK_IP_HAS_INTM_CLK 88U #define FEATURE_CLOCK_IP_HAS_LCU0_CLK 89U #define FEATURE_CLOCK_IP_HAS_LCU1_CLK 90U #define FEATURE_CLOCK_IP_HAS_LPI2C0_CLK 91U #define FEATURE_CLOCK_IP_HAS_LPI2C1_CLK 92U #define FEATURE_CLOCK_IP_HAS_LPSPI0_CLK 93U #define FEATURE_CLOCK_IP_HAS_LPSPI1_CLK 94U #define FEATURE_CLOCK_IP_HAS_LPSPI2_CLK 95U #define FEATURE_CLOCK_IP_HAS_LPSPI3_CLK 96U #define FEATURE_CLOCK_IP_HAS_LPSPI4_CLK 97U #define FEATURE_CLOCK_IP_HAS_LPSPI5_CLK 98U #define FEATURE_CLOCK_IP_HAS_LPUART0_CLK 99U #define FEATURE_CLOCK_IP_HAS_LPUART10_CLK 100U #define FEATURE_CLOCK_IP_HAS_LPUART11_CLK 101U #define FEATURE_CLOCK_IP_HAS_LPUART12_CLK 102U #define FEATURE_CLOCK_IP_HAS_LPUART13_CLK 103U #define FEATURE_CLOCK_IP_HAS_LPUART14_CLK 104U #define FEATURE_CLOCK_IP_HAS_LPUART15_CLK 105U #define FEATURE_CLOCK_IP_HAS_LPUART1_CLK 106U #define FEATURE_CLOCK_IP_HAS_LPUART2_CLK 107U #define FEATURE_CLOCK_IP_HAS_LPUART3_CLK 108U #define FEATURE_CLOCK_IP_HAS_LPUART4_CLK 109U #define FEATURE_CLOCK_IP_HAS_LPUART5_CLK 110U #define FEATURE_CLOCK_IP_HAS_LPUART6_CLK 111U #define FEATURE_CLOCK_IP_HAS_LPUART7_CLK 112U #define FEATURE_CLOCK_IP_HAS_LPUART8_CLK 113U #define FEATURE_CLOCK_IP_HAS_LPUART9_CLK 114U #define FEATURE_CLOCK_IP_HAS_MSCM_CLK 115U #define FEATURE_CLOCK_IP_HAS_MUA_CLK 116U #define FEATURE_CLOCK_IP_HAS_MUB_CLK 117U #define FEATURE_CLOCK_IP_HAS_PIT0_CLK 118U #define FEATURE_CLOCK_IP_HAS_PIT1_CLK 119U #define FEATURE_CLOCK_IP_HAS_PIT2_CLK 120U #define FEATURE_CLOCK_IP_HAS_QSPI0_RAM_CLK 121U #define FEATURE_CLOCK_IP_HAS_QSPI_SFCK_CLK 122U #define FEATURE_CLOCK_IP_HAS_QSPI0_SFCK_CLK 123U #define FEATURE_CLOCK_IP_HAS_QSPI0_TX_MEM_CLK 124U #define FEATURE_CLOCK_IP_HAS_RTC_CLK 125U #define FEATURE_CLOCK_IP_HAS_RTC0_CLK 126U #define FEATURE_CLOCK_IP_HAS_SAI0_CLK 127U #define FEATURE_CLOCK_IP_HAS_SAI1_CLK 128U #define FEATURE_CLOCK_IP_HAS_SEMA42_CLK 129U #define FEATURE_CLOCK_IP_HAS_SIUL0_CLK 130U #define FEATURE_CLOCK_IP_HAS_STCU0_CLK 131U #define FEATURE_CLOCK_IP_HAS_STMA_CLK 132U #define FEATURE_CLOCK_IP_HAS_STM0_CLK 133U #define FEATURE_CLOCK_IP_HAS_STMB_CLK 134U #define FEATURE_CLOCK_IP_HAS_STM1_CLK 135U #define FEATURE_CLOCK_IP_HAS_SWT0_CLK 136U #define FEATURE_CLOCK_IP_HAS_SWT1_CLK 137U #define FEATURE_CLOCK_IP_HAS_TCM_CM7_0_CLK 138U #define FEATURE_CLOCK_IP_HAS_TCM_CM7_1_CLK 139U #define FEATURE_CLOCK_IP_HAS_TEMPSENSE_CLK 140U #define FEATURE_CLOCK_IP_HAS_TRACE_CLK 141U #define FEATURE_CLOCK_IP_HAS_TRGMUX0_CLK 142U #define FEATURE_CLOCK_IP_HAS_TSENSE0_CLK 143U #define FEATURE_CLOCK_IP_HAS_WKPU0_CLK 144U #define FEATURE_CLOCKS_NO 145U /*================================================================================================== ENUMS ==================================================================================================*/ /*================================================================================================== STRUCTURES AND OTHER TYPEDEFS ==================================================================================================*/ #ifdef __cplusplus } #endif #endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */ /** @} */