/*================================================================================================== * Project : RTD AUTOSAR 4.4 * Platform : CORTEXM * Peripheral : * Dependencies : none * * Autosar Version : 4.4.0 * Autosar Revision : ASR_REL_4_4_REV_0000 * Autosar Conf.Variant : * SW Version : 0.9.0 * Build Version : S32K3_RTD_0_9_0_P02_D2107_ASR_REL_4_4_REV_0000_20210716 * * (c) Copyright 2020 - 2021 NXP Semiconductors * All Rights Reserved. * * NXP Confidential. This software is owned or controlled by NXP and may only be * used strictly in accordance with the applicable license terms. By expressly * accepting such terms or by downloading, installing, activating and/or otherwise * using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms. If you do not agree to be * bound by the applicable license terms, then you may not retain, install, * activate or otherwise use the software. ==================================================================================================*/ /* * GCC Linker Command File: * 0x20400000 0x20408000 32768 Standby RAM_0 (32K) * 0x20400000 0x20427FFF 163840 SRAM_0 * 0x20428000 0x2044FFFF 163840 SRAM_1 * Last 48 KB of SRAM_1 reserved by HSE Firmware */ HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00002000; ENTRY(Reset_Handler) MEMORY { int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32K */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* 64K */ int_sram : ORIGIN = 0x20400000, LENGTH = 0x0002E000 /* 184K */ int_sram_stack_c0 : ORIGIN = 0x2042E000, LENGTH = 0x00001000 /* 4KB */ int_sram_stack_c1 : ORIGIN = 0x2042F000, LENGTH = 0x00001000 /* 4KB */ int_sram_no_cacheable : ORIGIN = 0x20430000, LENGTH = 0x00010000 /* 64KB, needs to include int_results */ int_sram_shareable : ORIGIN = 0x20440000, LENGTH = 0x00004000 /* 16KB */ ram_rsvd2 : ORIGIN = 0x20444000, LENGTH = 0 /* End of SRAM */ } SECTIONS { .sram : { . = ALIGN(4); KEEP(*(.core_loop)) . = ALIGN(4); *(.startup) . = ALIGN(4); *(.text.startup) . = ALIGN(4); *(.text) *(.text*) . = ALIGN(4); *(.mcal_text) . = ALIGN(4); KEEP(*(.init)) . = ALIGN(4); KEEP(*(.fini)) . = ALIGN(4); *(.rodata) *(.rodata*) . = ALIGN(4); *(.mcal_const_cfg) . = ALIGN(4); *(.mcal_const) . = ALIGN(4); __init_table = .; KEEP(*(.init_table)) . = ALIGN(4); __zero_table = .; KEEP(*(.zero_table)) . = ALIGN(4); *(.acmcu_code_rom) . = ALIGN(4); *(.ramcode) . = ALIGN(4); *(.data) *(.data*) . = ALIGN(4); *(.mcal_data) . = ALIGN(16); __sram_bss_start = .; *(.bss) *(.bss*) . = ALIGN(16); *(.mcal_bss) . = ALIGN(4); __sram_bss_end = .; } > int_sram /* heap section */ .heap (NOLOAD): { . += ALIGN(4); _end = .; end = .; _heap_start = .; . += HEAP_SIZE; _heap_end = .; } > int_sram .acfls_code_rom : { acfls_code_rom_start = .; . = ALIGN(0x4); *(.acfls_code_rom) acfls_code_rom_end = .; } > int_sram .acfls_code_ram : { . += (acfls_code_rom_end - acfls_code_rom_start ); } > int_sram .non_cacheable : { . = ALIGN(4); KEEP(*(.int_results)) . += 0x100; . = ALIGN(4096); __interrupts_ram_start = .; KEEP(*(.intc_vector)) . = ALIGN(4); __interrupts_ram_end = .; . = ALIGN(16); __non_cacheable_bss_start = .; *(.mcal_bss_no_cacheable) . = ALIGN(4); __non_cacheable_bss_end = .; . = ALIGN(4); *(.mcal_data_no_cacheable) . = ALIGN(4); *(.mcal_const_no_cacheable) HSE_LOOP_ADDR = .; LONG(0x0); } > int_sram_no_cacheable .shareable_ram : { . = ALIGN(16); __shareable_bss_start = .; KEEP(*(.mcal_shared_bss)) . = ALIGN(4); __shareable_bss_end = .; . = ALIGN(16); KEEP(*(.mcal_shared_data)) } > int_sram_shareable __Stack_end_c0 = ORIGIN(int_sram_stack_c0); __Stack_start_c0 = ORIGIN(int_sram_stack_c0) + LENGTH(int_sram_stack_c0); __Stack_end_c1 = ORIGIN(int_sram_stack_c1); __Stack_start_c1 = ORIGIN(int_sram_stack_c1) + LENGTH(int_sram_stack_c1); __INT_SRAM_START = ORIGIN(int_sram); __INT_SRAM_END = ORIGIN(ram_rsvd2); __INT_ITCM_START = ORIGIN(int_itcm); __INT_ITCM_END = ORIGIN(int_itcm) + LENGTH(int_itcm); __INT_DTCM_START = ORIGIN(int_dtcm); __INT_DTCM_END = ORIGIN(int_dtcm) + LENGTH(int_dtcm); __RAM_SHAREABLE_START = ORIGIN(int_sram_shareable); __RAM_SHAREABLE_END = ORIGIN(int_sram_shareable) + LENGTH(int_sram_shareable) - 1; __ROM_SHAREABLE_START = 0; __ROM_SHAREABLE_END = 0; __RAM_NO_CACHEABLE_START = ORIGIN(int_sram_no_cacheable); __RAM_NO_CACHEABLE_END = ORIGIN(int_sram_no_cacheable) + LENGTH(int_sram_no_cacheable) - 1; __ROM_NO_CACHEABLE_START = 0; __ROM_NO_CACHEABLE_END = 0; __RAM_CACHEABLE_START = ORIGIN(int_sram); __RAM_CACHEABLE_END = ORIGIN(int_sram) + LENGTH(int_sram) - 1; __ROM_CACHEABLE_START = 0; __ROM_CACHEABLE_END = 0; __BSS_SRAM_START = __sram_bss_start; __BSS_SRAM_END = __sram_bss_end; __BSS_SRAM_SIZE = __sram_bss_end - __sram_bss_start; __BSS_SRAM_NC_START = __non_cacheable_bss_start; __BSS_SRAM_NC_SIZE = __non_cacheable_bss_end - __non_cacheable_bss_start; __BSS_SRAM_NC_END = __non_cacheable_bss_end; __BSS_SRAM_SH_START = __shareable_bss_start; __BSS_SRAM_SH_SIZE = __shareable_bss_end - __shareable_bss_start; __BSS_SRAM_SH_END = __shareable_bss_end; __RAM_INTERRUPT_START = __interrupts_ram_start; __ROM_INTERRUPT_START = 0; __ROM_INTERRUPT_END = 0; __INIT_TABLE = __init_table; __ZERO_TABLE = __zero_table; __RAM_INIT = 0; __ITCM_INIT = 1; __DTCM_INIT = 1; /* Discard boot header in RAM */ /DISCARD/ : { *(.boot_header) } /* Fls module access code support */ Fls_ACEraseRomStart = ADDR(.acfls_code_rom); Fls_ACEraseRomEnd = ADDR(.acfls_code_rom) + SIZEOF(.acfls_code_rom); Fls_ACEraseSize = (SIZEOF(.acfls_code_rom)+3) / 4; /* Copy 4 bytes at a time*/ Fls_ACWriteRomStart = ADDR(.acfls_code_rom); Fls_ACWriteRomEnd = ADDR(.acfls_code_rom) + SIZEOF(.acfls_code_rom); Fls_ACWriteSize = (SIZEOF(.acfls_code_rom)+3) / 4; /* Copy 4 bytes at a time*/ _ERASE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram); _WRITE_FUNC_ADDRESS_ = ADDR(.acfls_code_ram); __ENTRY_VTABLE = __RAM_INTERRUPT_START; }