/*================================================================================================== * Project : RTD AUTOSAR 4.4 * Platform : CORTEXM * Peripheral : FLEXCAN * Dependencies : * * Autosar Version : 4.4.0 * Autosar Revision : ASR_REL_4_4_REV_0000 * Autosar Conf.Variant : * SW Version : 0.9.0 * Build Version : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326 * * (c) Copyright 2020 - 2021 NXP Semiconductors * All Rights Reserved. * * NXP Confidential. This software is owned or controlled by NXP and may only be * used strictly in accordance with the applicable license terms. By expressly * accepting such terms or by downloading, installing, activating and/or otherwise * using the software, you are agreeing that you have read, and that you agree to * comply with and are bound by, such license terms. If you do not agree to be * bound by the applicable license terms, then you may not retain, install, * activate or otherwise use the software. ==================================================================================================*/ /** * @file * * @brief FlexCAN Registers and Default Reg Values * @details * * @addtogroup FlexCAN * @{ */ #ifndef FLEXCAN_IP_DEVICEREG_H_ #define FLEXCAN_IP_DEVICEREG_H_ /*================================================================================================== * INCLUDE FILES * 1) system and project includes * 2) needed interfaces from external units * 3) internal and external interfaces from this unit ==================================================================================================*/ #include "Platform_Types.h" #include "S32K344_FLEXCAN.h" #include "S32K344_DCM_GPR.h" /*================================================================================================== * SOURCE FILE VERSION INFORMATION ==================================================================================================*/ #define FLEXCAN_IP_DEVICEREG_VENDOR_ID_H 43 #define FLEXCAN_IP_DEVICEREG_AR_RELEASE_MAJOR_VERSION_H 4 #define FLEXCAN_IP_DEVICEREG_AR_RELEASE_MINOR_VERSION_H 4 #define FLEXCAN_IP_DEVICEREG_AR_RELEASE_REVISION_VERSION_H 0 #define FLEXCAN_IP_DEVICEREG_SW_MAJOR_VERSION_H 0 #define FLEXCAN_IP_DEVICEREG_SW_MINOR_VERSION_H 9 #define FLEXCAN_IP_DEVICEREG_SW_PATCH_VERSION_H 0 /*================================================================================================== * FILE VERSION CHECKS ==================================================================================================*/ #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK /* Check if current file and Platform_Types header file are of the same version */ /* Check if current file and S32K344_FLEXCAN header file are of the same version */ #endif /*================================================================================================== * CONSTANTS ==================================================================================================*/ /*================================================================================================== * DEFINES AND MACROS ==================================================================================================*/ /* Default value for register */ /** * @brief Default value for the MCR register */ #define FLEXCAN_MCR_DEFAULT_VALUE_U32 ((uint32)0xD890000FU) /** * @brief Default value for the CTRL1 register */ #define FLEXCAN_CTRL1_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the TIMER register */ #define FLEXCAN_TIMER_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ECR register */ #define FLEXCAN_ECR_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ESR1 register */ #define FLEXCAN_ESR1_DEFAULT_VALUE_U32 ((uint32)0x0003B006U) /** * @brief Default value for the IMASK2 register */ #define FLEXCAN_IMASK_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the IFLAG4 register */ #define FLEXCAN_IFLAG_DEFAULT_VALUE_U32 ((uint32)0xFFFFFFFFU) /** * @brief Default value for the CTRL2 register */ #define FLEXCAN_CTRL2_DEFAULT_VALUE_U32 ((uint32)0x00100000U) /** * @brief Default value for the CTRL2 register */ #define FLEXCAN_CBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the MECR register */ #define FLEXCAN_MECR_DEFAULT_VALUE_U32 ((uint32)0x000C0080U) /** * @brief Default value for the ERRIAR register */ #define FLEXCAN_ERRIAR_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERRIDPR register */ #define FLEXCAN_ERRIDPR_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERRIPPR register */ #define FLEXCAN_ERRIPPR_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERRSR register */ #define FLEXCAN_ERRSR_DEFAULT_VALUE_U32 ((uint32)0x000D000DU) /** * @brief Default value for the FDCTRL register */ #define FLEXCAN_FDCTRL_DEFAULT_VALUE_U32 ((uint32)0x80004100U) /** * @brief Default value for the FDCBT register */ #define FLEXCAN_FDCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERFCR register */ #define FLEXCAN_ERFCR_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERFIER register */ #define FLEXCAN_ERFIER_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ERFSR register */ #define FLEXCAN_ERFSR_DEFAULT_VALUE_U32 ((uint32)0xF8000000U) /** * @brief Default value for the EPRS register */ #define FLEXCAN_EPRS_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ENCBT register */ #define FLEXCAN_ENCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the EDCBT register */ #define FLEXCAN_EDCBT_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /** * @brief Default value for the ETDC register */ #define FLEXCAN_ETDC_DEFAULT_VALUE_U32 ((uint32)0x00000000U) /* @brief number of CAN peripheral has Enhanced Rx FIFO mode */ #define FEATURE_CAN_ENHANCED_RX_FIFO_NUM (1u) /** Array initializer of CAN peripheral base addresses has Enhanced Rx FIFO mode*/ #define CAN_BASE_PTRS_HAS_ENHANCED_RX_FIFO { CAN_0 } #define FEATURE_CAN_BUSOFF_ERROR_INTERRUPT_UNIFIED (STD_ON) /* Workaround for difference base address naming defined in BASE */ /** Peripheral FLEXCAN_0 base address */ #define FLEXCAN_0_BASE CAN_0_BASE /** Peripheral FLEXCAN_1 base address */ #define FLEXCAN_1_BASE CAN_1_BASE /** Peripheral FLEXCAN_2 base address */ #define FLEXCAN_2_BASE CAN_2_BASE /** Peripheral FLEXCAN_3 base address */ #define FLEXCAN_3_BASE CAN_3_BASE /** Peripheral FLEXCAN_4 base address */ #define FLEXCAN_4_BASE CAN_4_BASE /** Peripheral FLEXCAN_5 base address */ #define FLEXCAN_5_BASE CAN_5_BASE #define CAN_RAMn_COUNT 384u #define CAN_RAM2n_COUNT 20u /* Registers used By Timestamp HR source in FlexCAN_ConfigTimestampModule */ #define TIMESTAMP_REG DCM_GPR->DCMRWF1 #define CAN_TIMESTAMP_SEL(x) DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL(x) #define CAN_TIMESTAMP_EN_MASK DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN_MASK #endif /* FLEXCAN_IP_DEVICEREG_H_ */ /** @} */