Simulink 통합 제어 로직 업로드

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic.bat

@@ -0,0 +1,16 @@
+
+set skipSetupArg=%2
+if "%skipSetupArg%" NEQ "skip_setup_msvc" (
+call "setup_msvc.bat"
+)
+
+cd .
+
+if "%1"=="" (nmake  -f ADM_Integrated_Logic.mk all) else (nmake  -f ADM_Integrated_Logic.mk %1)
+@if errorlevel 1 goto error_exit
+
+exit /B 0
+
+:error_exit
+echo The make command returned an error of %errorlevel%
+exit /B 1

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic.h

@@ -0,0 +1,287 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: ADM_Integrated_Logic.h
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#ifndef ADM_Integrated_Logic_h_
+#define ADM_Integrated_Logic_h_
+#ifndef ADM_Integrated_Logic_COMMON_INCLUDES_
+#define ADM_Integrated_Logic_COMMON_INCLUDES_
+#include <stdbool.h>
+#include <stdint.h>
+#include "complex_types.h"
+#endif                               /* ADM_Integrated_Logic_COMMON_INCLUDES_ */
+
+#include "ADM_Integrated_Logic_types.h"
+
+/* Block signals and states (default storage) for system '<Root>' */
+typedef struct {
+  double Delay_DSTATE[2];              /* '<S34>/Delay' */
+  double Delay3_DSTATE[2];             /* '<S34>/Delay3' */
+  double Delay_DSTATE_p[2];            /* '<S26>/Delay' */
+  double Delay3_DSTATE_h[2];           /* '<S26>/Delay3' */
+  double Saturation;                   /* '<S7>/Saturation' */
+  double DelayInput2_DSTATE;           /* '<S46>/Delay Input2' */
+  double DelayInput2_DSTATE_m;         /* '<S47>/Delay Input2' */
+  double Integrator_2_DSTATE;          /* '<S7>/Integrator_2' */
+  double Memory_DSTATE;                /* '<S6>/Memory' */
+  double DiscreteTransferFcn_states;   /* '<S1>/Discrete Transfer Fcn' */
+  double d1_DSTATE;                    /* '<S20>/d1' */
+  double d_DSTATE;                     /* '<S20>/d' */
+  double d_DSTATE_i;                   /* '<S30>/d' */
+  double d1_DSTATE_p;                  /* '<S30>/d1' */
+  double d_DSTATE_c;                   /* '<S31>/d' */
+  double d1_DSTATE_h;                  /* '<S31>/d1' */
+  double d_DSTATE_d;                   /* '<S32>/d' */
+  double d1_DSTATE_l;                  /* '<S32>/d1' */
+  double Delay1_DSTATE;                /* '<S34>/Delay1' */
+  double Delay2_DSTATE;                /* '<S34>/Delay2' */
+  double d1_DSTATE_e;                  /* '<S33>/d1' */
+  double d_DSTATE_ij;                  /* '<S33>/d' */
+  double d_DSTATE_ir;                  /* '<S22>/d' */
+  double d1_DSTATE_o;                  /* '<S22>/d1' */
+  double d_DSTATE_m;                   /* '<S23>/d' */
+  double d1_DSTATE_hm;                 /* '<S23>/d1' */
+  double d_DSTATE_mw;                  /* '<S24>/d' */
+  double d1_DSTATE_g;                  /* '<S24>/d1' */
+  double d1_DSTATE_ej;                 /* '<S25>/d1' */
+  double d_DSTATE_j;                   /* '<S25>/d' */
+  double Delay1_DSTATE_c;              /* '<S26>/Delay1' */
+  double Delay2_DSTATE_n;              /* '<S26>/Delay2' */
+  double d1_DSTATE_ob;                 /* '<S40>/d1' */
+  double d_DSTATE_e;                   /* '<S40>/d' */
+  double d1_DSTATE_i;                  /* '<S41>/d1' */
+  double d_DSTATE_p;                   /* '<S41>/d' */
+  double d1_DSTATE_o1;                 /* '<S42>/d1' */
+  double d_DSTATE_n;                   /* '<S42>/d' */
+  double Integrator_1_DSTATE;          /* '<S7>/Integrator_1' */
+  double d1_DSTATE_a;                  /* '<S43>/d1' */
+  double d_DSTATE_d1;                  /* '<S43>/d' */
+  double DelayInput2_DSTATE_c;         /* '<S12>/Delay Input2' */
+  double DelayInput2_DSTATE_i;         /* '<S13>/Delay Input2' */
+  double PrevY;                        /* '<S1>/Input_Vx_RateLimiter' */
+  double PrevY_o;                      /* '<S3>/Brake_Out_RateLimiter' */
+  double PrevY_a;                      /* '<S3>/TargetSpd_RateLimiter' */
+  double Memory_PreviousInput;         /* '<S3>/Memory' */
+  double HAC_ON_FLAG;                  /* '<S7>/HAC_OFF_OK_Func' */
+  double Smoothed_Torque;              /* '<S7>/HAC_OFF_OK_Func' */
+  double HAC_Desired_Torque;           /* '<S7>/HAC_OFF_OK_Func' */
+  double HAC_ON_Timer;                 /* '<S7>/HAC_OFF_OK_Func' */
+  uint8_t is_active_c6_ADM_Integrated_Log;/* '<S7>/Chart' */
+  uint8_t is_c6_ADM_Integrated_Logic;  /* '<S7>/Chart' */
+} DW_ADM_Integrated_Logic_T;
+
+/* Invariant block signals (default storage) */
+typedef struct {
+  const double W_value;                /* '<S39>/Multiply' */
+  const double W_Value_for_Brake;      /* '<S39>/Multiply4' */
+} ConstB_ADM_Integrated_Logic_T;
+
+/* External inputs (root inport signals with default storage) */
+typedef struct {
+  double GV_MCU_RPM;                   /* '<Root>/GV_MCU_RPM' */
+  double GV_BrakeTorqueCommand;        /* '<Root>/GV_BrakeTorqueCommand' */
+  double GV_IMU_AX_Val;                /* '<Root>/GV_IMU_AX_Val' */
+  double GV_IMU_AY_Val;                /* '<Root>/GV_IMU_AY_Val' */
+  double GV_IMU_AZ_Val;                /* '<Root>/GV_IMU_AZ_Val' */
+  double GV_IMU_PitchRtVal;            /* '<Root>/GV_IMU_PitchRtVal' */
+  double GV_Vx_Command;                /* '<Root>/GV_Vx_Command' */
+  double GV_VCU_GearSelStat;           /* '<Root>/GV_VCU_GearSelStat' */
+  double GV_MCU_EstTrq;                /* '<Root>/GV_MCU_EstTrq' */
+  double GV_Vx_Limit;                  /* '<Root>/GV_Vx_Limit' */
+  double GV_Vx_Fbk;                    /* '<Root>/GV_Vx_Fbk' */
+  double GV_RWA_RackAngleCommand;      /* '<Root>/GV_RWA_RackAngleCommand' */
+  double GV_RWS_RackAngleCommand;      /* '<Root>/GV_RWS_RackAngleCommand' */
+  double GV_RWA_Fault_Flag;            /* '<Root>/GV_RWA_Fault_Flag' */
+  double GV_Operation_Mode;            /* '<Root>/GV_Operation_Mode' */
+} ExtU_ADM_Integrated_Logic_T;
+
+/* External outputs (root outports fed by signals with default storage) */
+typedef struct {
+  double GV_Brake_Command;             /* '<Root>/GV_Brake_Command' */
+  double GV_Master_Rack_Angle_Cmd;     /* '<Root>/GV_Master_Rack_Angle_Cmd' */
+  double GV_Hill_Torque_Assist;        /* '<Root>/GV_Hill_Torque_Assist' */
+  double GV_Motor_Torque_Cmd;          /* '<Root>/GV_Motor_Torque_Cmd' */
+  double Debug_HAC_FLAG;               /* '<Root>/Debug_HAC_FLAG' */
+  double Debug_HAC_RPM_Decision;       /* '<Root>/Debug_HAC_RPM_Decision' */
+  double Debug_HAC_Pitch_angle;        /* '<Root>/Debug_HAC_Pitch_angle' */
+  double Debug_HAC_Brake_Output;       /* '<Root>/Debug_HAC_Brake_Output' */
+  double Debug_CC_Brake_Output;        /* '<Root>/Debug_CC_Brake_Output' */
+  double GV_RWS_RackAngleCmd1;         /* '<Root>/GV_RWS_RackAngleCmd1' */
+  double GV_Speed_Limit;               /* '<Root>/GV_Speed_Limit' */
+  double GV_Gear_Postion_Out;          /* '<Root>/GV_Gear_Postion_Out' */
+} ExtY_ADM_Integrated_Logic_T;
+
+/* Real-time Model Data Structure */
+struct tag_RTM_ADM_Integrated_Logic_T {
+  /*
+   * Timing:
+   * The following substructure contains information regarding
+   * the timing information for the model.
+   */
+  struct {
+    uint32_t clockTick1;
+    struct {
+      uint16_t TID[2];
+    } TaskCounters;
+  } Timing;
+};
+
+/* Block signals and states (default storage) */
+extern DW_ADM_Integrated_Logic_T ADM_Integrated_Logic_DW;
+
+/* External inputs (root inport signals with default storage) */
+extern ExtU_ADM_Integrated_Logic_T ADM_Integrated_Logic_U;
+
+/* External outputs (root outports fed by signals with default storage) */
+extern ExtY_ADM_Integrated_Logic_T ADM_Integrated_Logic_Y;
+extern const ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB;/* constant block i/o */
+
+/* Model entry point functions */
+extern void ADM_Integrated_Logic_initialize(void);
+extern void ADM_Integrated_Logic_step(void);
+extern void ADM_Integrated_Logic_terminate(void);
+
+/* Real-time Model object */
+extern RT_MODEL_ADM_Integrated_Logic_T *const ADM_Integrated_Logic_M;
+
+/*-
+ * These blocks were eliminated from the model due to optimizations:
+ *
+ * Block '<S17>/BW_PI' : Unused code path elimination
+ * Block '<S17>/Constant1' : Unused code path elimination
+ * Block '<S17>/Constant16' : Unused code path elimination
+ * Block '<S17>/Constant17' : Unused code path elimination
+ * Block '<S17>/Constant2' : Unused code path elimination
+ * Block '<S1>/Data Type Conversion2' : Unused code path elimination
+ * Block '<S1>/Gain2' : Unused code path elimination
+ * Block '<S39>/Abs' : Unused code path elimination
+ * Block '<S39>/Brake_Saturation' : Unused code path elimination
+ * Block '<S39>/Multiply5' : Unused code path elimination
+ * Block '<S39>/Radius1' : Unused code path elimination
+ * Block '<S46>/FixPt Data Type Duplicate' : Unused code path elimination
+ * Block '<S51>/Data Type Duplicate' : Unused code path elimination
+ * Block '<S51>/Data Type Propagation' : Unused code path elimination
+ * Block '<S47>/FixPt Data Type Duplicate' : Unused code path elimination
+ * Block '<S52>/Data Type Duplicate' : Unused code path elimination
+ * Block '<S52>/Data Type Propagation' : Unused code path elimination
+ * Block '<S7>/Scope2' : Unused code path elimination
+ * Block '<S12>/FixPt Data Type Duplicate' : Unused code path elimination
+ * Block '<S53>/Data Type Duplicate' : Unused code path elimination
+ * Block '<S53>/Data Type Propagation' : Unused code path elimination
+ * Block '<S13>/FixPt Data Type Duplicate' : Unused code path elimination
+ * Block '<S54>/Data Type Duplicate' : Unused code path elimination
+ * Block '<S54>/Data Type Propagation' : Unused code path elimination
+ * Block '<S3>/ControlFlag' : Eliminated nontunable gain of 1
+ * Block '<S17>/FBGain' : Eliminated nontunable gain of 1
+ * Block '<S28>/FFGain' : Eliminated nontunable gain of 1
+ * Block '<S1>/Data Type Conversion1' : Eliminate redundant data type conversion
+ * Block '<S1>/Data Type Conversion3' : Eliminate redundant data type conversion
+ * Block '<S39>/HAC_Gain' : Eliminated nontunable gain of 1
+ * Block '<S46>/Zero-Order Hold' : Eliminated since input and output rates are identical
+ * Block '<S47>/Zero-Order Hold' : Eliminated since input and output rates are identical
+ * Block '<S12>/Zero-Order Hold' : Eliminated since input and output rates are identical
+ * Block '<S13>/Zero-Order Hold' : Eliminated since input and output rates are identical
+ */
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model.  The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model.  For example,
+ *
+ * hilite_system('<S3>')    - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'ADM_Integrated_Logic'
+ * '<S1>'   : 'ADM_Integrated_Logic/Delivery_Mobility'
+ * '<S2>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant'
+ * '<S3>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1'
+ * '<S4>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Brake_Func'
+ * '<S5>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Motor_Func'
+ * '<S6>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position'
+ * '<S7>'   : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1'
+ * '<S8>'   : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function1'
+ * '<S9>'   : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function2'
+ * '<S10>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function5'
+ * '<S11>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function6'
+ * '<S12>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic'
+ * '<S13>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1'
+ * '<S14>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic'
+ * '<S15>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB'
+ * '<S16>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB_Gain'
+ * '<S17>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller'
+ * '<S18>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/GearCondition_Brake'
+ * '<S19>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Gear_pos_out'
+ * '<S20>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/LPFM'
+ * '<S21>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Target_RPM'
+ * '<S22>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot3'
+ * '<S23>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot4'
+ * '<S24>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot5'
+ * '<S25>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/LPFM'
+ * '<S26>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Second order LPF'
+ * '<S27>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB'
+ * '<S28>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF'
+ * '<S29>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB/P'
+ * '<S30>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot'
+ * '<S31>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot2'
+ * '<S32>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot3'
+ * '<S33>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/LPFM'
+ * '<S34>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Second order LPF'
+ * '<S35>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Compare To Constant'
+ * '<S36>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Gear_FUNCTION1'
+ * '<S37>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Chart'
+ * '<S38>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/HAC_OFF_OK_Func'
+ * '<S39>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2'
+ * '<S40>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM'
+ * '<S41>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM1'
+ * '<S42>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM2'
+ * '<S43>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM3'
+ * '<S44>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Pitch_calculate'
+ * '<S45>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Ramp'
+ * '<S46>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic'
+ * '<S47>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1'
+ * '<S48>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_R'
+ * '<S49>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c'
+ * '<S50>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c1'
+ * '<S51>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic/Saturation Dynamic'
+ * '<S52>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1/Saturation Dynamic'
+ * '<S53>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic/Saturation Dynamic'
+ * '<S54>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1/Saturation Dynamic'
+ * '<S55>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Compare To Constant'
+ * '<S56>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Vx_OutPut_Function'
+ */
+
+/*-
+ * Requirements for '<Root>': ADM_Integrated_Logic
+
+ */
+#endif                                 /* ADM_Integrated_Logic_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic.mk

@@ -0,0 +1,474 @@
+###########################################################################
+## Makefile generated for component 'ADM_Integrated_Logic'. 
+## 
+## Makefile     : ADM_Integrated_Logic.mk
+## Generated on : Tue Apr 29 10:59:09 2025
+## Final product: $(RELATIVE_PATH_TO_ANCHOR)\ADM_Integrated_Logic.exe
+## Product type : executable
+## 
+###########################################################################
+
+###########################################################################
+## MACROS
+###########################################################################
+
+# Macro Descriptions:
+# PRODUCT_NAME            Name of the system to build
+# MAKEFILE                Name of this makefile
+# COMPILER_COMMAND_FILE   Compiler command listing model reference header paths
+# CMD_FILE                Command file
+
+PRODUCT_NAME              = ADM_Integrated_Logic
+MAKEFILE                  = ADM_Integrated_Logic.mk
+MATLAB_ROOT               = C:\PROGRA~1\MATLAB\R2024a
+MATLAB_BIN                = C:\PROGRA~1\MATLAB\R2024a\bin
+MATLAB_ARCH_BIN           = $(MATLAB_BIN)\win64
+START_DIR                 = C:\Users\MSI\SYNOLO~1\3min_be\한자연\!과제\배송모~1\!진행~1\2025\25-04-~4
+SOLVER                    = 
+SOLVER_OBJ                = 
+CLASSIC_INTERFACE         = 0
+TGT_FCN_LIB               = None
+MODEL_HAS_DYNAMICALLY_LOADED_SFCNS = 0
+RELATIVE_PATH_TO_ANCHOR   = ..
+COMPILER_COMMAND_FILE     = ADM_Integrated_Logic_comp.rsp
+CMD_FILE                  = ADM_Integrated_Logic.rsp
+C_STANDARD_OPTS           = 
+CPP_STANDARD_OPTS         = 
+NODEBUG                   = 1
+
+###########################################################################
+## TOOLCHAIN SPECIFICATIONS
+###########################################################################
+
+# Toolchain Name:          Microsoft Visual C++ 2022 v17.0 | nmake (64-bit Windows)
+# Supported Version(s):    17.0
+# ToolchainInfo Version:   2024a
+# Specification Revision:  1.0
+# 
+#-------------------------------------------
+# Macros assumed to be defined elsewhere
+#-------------------------------------------
+
+# NODEBUG
+# cvarsdll
+# cvarsmt
+# conlibsmt
+# ldebug
+# conflags
+# cflags
+
+#-----------
+# MACROS
+#-----------
+
+MW_EXTERNLIB_DIR    = $(MATLAB_ROOT)\extern\lib\win64\microsoft
+MW_LIB_DIR          = $(MATLAB_ROOT)\lib\win64
+CPU                 = AMD64
+APPVER              = 5.02
+CVARSFLAG           = $(cvarsmt)
+CFLAGS_ADDITIONAL   = -D_CRT_SECURE_NO_WARNINGS
+CPPFLAGS_ADDITIONAL = -EHs -D_CRT_SECURE_NO_WARNINGS /wd4251 /Zc:__cplusplus
+LIBS_TOOLCHAIN      = $(conlibs)
+
+TOOLCHAIN_SRCS = 
+TOOLCHAIN_INCS = 
+TOOLCHAIN_LIBS = 
+
+#------------------------
+# BUILD TOOL COMMANDS
+#------------------------
+
+# C Compiler: Microsoft Visual C Compiler
+CC = cl
+
+# Linker: Microsoft Visual C Linker
+LD = link
+
+# C++ Compiler: Microsoft Visual C++ Compiler
+CPP = cl
+
+# C++ Linker: Microsoft Visual C++ Linker
+CPP_LD = link
+
+# Archiver: Microsoft Visual C/C++ Archiver
+AR = lib
+
+# MEX Tool: MEX Tool
+MEX_PATH = $(MATLAB_ARCH_BIN)
+MEX = "$(MEX_PATH)\mex"
+
+# Download: Download
+DOWNLOAD =
+
+# Execute: Execute
+EXECUTE = $(PRODUCT)
+
+# Builder: NMAKE Utility
+MAKE = nmake
+
+
+#-------------------------
+# Directives/Utilities
+#-------------------------
+
+CDEBUG              = -Zi
+C_OUTPUT_FLAG       = -Fo
+LDDEBUG             = /DEBUG
+OUTPUT_FLAG         = -out:
+CPPDEBUG            = -Zi
+CPP_OUTPUT_FLAG     = -Fo
+CPPLDDEBUG          = /DEBUG
+OUTPUT_FLAG         = -out:
+ARDEBUG             =
+STATICLIB_OUTPUT_FLAG = -out:
+MEX_DEBUG           = -g
+RM                  = @del
+ECHO                = @echo
+MV                  = @ren
+RUN                 = @cmd /C
+
+#--------------------------------------
+# "Faster Runs" Build Configuration
+#--------------------------------------
+
+ARFLAGS              = /nologo
+CFLAGS               = $(cflags) $(CVARSFLAG) $(CFLAGS_ADDITIONAL) \
+                       /O2 /Oy-
+CPPFLAGS             = /TP $(cflags) $(CVARSFLAG) $(CPPFLAGS_ADDITIONAL) \
+                       /O2 /Oy-
+CPP_LDFLAGS          = $(ldebug) $(conflags) $(LIBS_TOOLCHAIN)
+CPP_SHAREDLIB_LDFLAGS  = $(ldebug) $(conflags) $(LIBS_TOOLCHAIN) \
+                         -dll -def:$(DEF_FILE)
+DOWNLOAD_FLAGS       =
+EXECUTE_FLAGS        =
+LDFLAGS              = $(ldebug) $(conflags) $(LIBS_TOOLCHAIN)
+MEX_CPPFLAGS         =
+MEX_CPPLDFLAGS       =
+MEX_CFLAGS           =
+MEX_LDFLAGS          =
+MAKE_FLAGS           = -f $(MAKEFILE)
+SHAREDLIB_LDFLAGS    = $(ldebug) $(conflags) $(LIBS_TOOLCHAIN) \
+                       -dll -def:$(DEF_FILE)
+
+
+
+###########################################################################
+## OUTPUT INFO
+###########################################################################
+
+PRODUCT = $(RELATIVE_PATH_TO_ANCHOR)\ADM_Integrated_Logic.exe
+PRODUCT_TYPE = "executable"
+BUILD_TYPE = "Top-Level Standalone Executable"
+
+###########################################################################
+## INCLUDE PATHS
+###########################################################################
+
+INCLUDES_BUILDINFO = 
+
+INCLUDES = $(INCLUDES_BUILDINFO)
+
+###########################################################################
+## DEFINES
+###########################################################################
+
+DEFINES_BUILD_ARGS = -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0
+DEFINES_CUSTOM = 
+DEFINES_OPTS = -DTID01EQ=0
+DEFINES_STANDARD = -DMODEL=ADM_Integrated_Logic -DNUMST=2 -DNCSTATES=0 -DHAVESTDIO -DMODEL_HAS_DYNAMICALLY_LOADED_SFCNS=0
+
+DEFINES = $(DEFINES_BUILD_ARGS) $(DEFINES_CUSTOM) $(DEFINES_OPTS) $(DEFINES_STANDARD)
+
+###########################################################################
+## SOURCE FILES
+###########################################################################
+
+SRCS = $(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic.c $(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic_data.c
+
+MAIN_SRC = $(START_DIR)\ADM_Integrated_Logic_ert_rtw\ert_main.c
+
+ALL_SRCS = $(SRCS) $(MAIN_SRC)
+
+###########################################################################
+## OBJECTS
+###########################################################################
+
+OBJS = ADM_Integrated_Logic.obj ADM_Integrated_Logic_data.obj
+
+MAIN_OBJ = ert_main.obj
+
+ALL_OBJS = $(OBJS) $(MAIN_OBJ)
+
+###########################################################################
+## PREBUILT OBJECT FILES
+###########################################################################
+
+PREBUILT_OBJS = 
+
+###########################################################################
+## LIBRARIES
+###########################################################################
+
+LIBS = 
+
+###########################################################################
+## SYSTEM LIBRARIES
+###########################################################################
+
+SYSTEM_LIBS = 
+
+###########################################################################
+## ADDITIONAL TOOLCHAIN FLAGS
+###########################################################################
+
+#---------------
+# C Compiler
+#---------------
+
+CFLAGS_BASIC = $(DEFINES) @$(COMPILER_COMMAND_FILE)
+
+CFLAGS = $(CFLAGS) $(CFLAGS_BASIC)
+
+#-----------------
+# C++ Compiler
+#-----------------
+
+CPPFLAGS_BASIC = $(DEFINES) @$(COMPILER_COMMAND_FILE)
+
+CPPFLAGS = $(CPPFLAGS) $(CPPFLAGS_BASIC)
+
+###########################################################################
+## INLINED COMMANDS
+###########################################################################
+
+
+!include $(MATLAB_ROOT)\rtw\c\tools\vcdefs.mak
+
+
+###########################################################################
+## PHONY TARGETS
+###########################################################################
+
+.PHONY : all build buildobj clean info prebuild download execute set_environment_variables
+
+
+all : build
+	@cmd /C "@echo ### Successfully generated all binary outputs."
+
+
+build : set_environment_variables prebuild $(PRODUCT)
+
+
+buildobj : set_environment_variables prebuild $(OBJS) $(PREBUILT_OBJS)
+	@cmd /C "@echo ### Successfully generated all binary outputs."
+
+
+prebuild : 
+
+
+download : $(PRODUCT)
+
+
+execute : download
+	@cmd /C "@echo ### Invoking postbuild tool "Execute" ..."
+	$(EXECUTE) $(EXECUTE_FLAGS)
+	@cmd /C "@echo ### Done invoking postbuild tool."
+
+
+set_environment_variables : 
+	@set INCLUDE=$(INCLUDES);$(INCLUDE)
+	@set LIB=$(LIB)
+
+
+###########################################################################
+## FINAL TARGET
+###########################################################################
+
+#-------------------------------------------
+# Create a standalone executable            
+#-------------------------------------------
+
+$(PRODUCT) : $(OBJS) $(PREBUILT_OBJS) $(MAIN_OBJ)
+	@cmd /C "@echo ### Creating standalone executable "$(PRODUCT)" ..."
+	$(LD) $(LDFLAGS) -out:$(PRODUCT) @$(CMD_FILE) $(SYSTEM_LIBS) $(TOOLCHAIN_LIBS)
+	@cmd /C "@echo ### Created: $(PRODUCT)"
+
+
+###########################################################################
+## INTERMEDIATE TARGETS
+###########################################################################
+
+#---------------------
+# SOURCE-TO-OBJECT
+#---------------------
+
+.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(RELATIVE_PATH_TO_ANCHOR)}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(RELATIVE_PATH_TO_ANCHOR)}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(RELATIVE_PATH_TO_ANCHOR)}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(RELATIVE_PATH_TO_ANCHOR)}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)\ADM_Integrated_Logic_ert_rtw}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)\ADM_Integrated_Logic_ert_rtw}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)\ADM_Integrated_Logic_ert_rtw}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(START_DIR)\ADM_Integrated_Logic_ert_rtw}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\rtw\c\src}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\rtw\c\src}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\rtw\c\src}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\rtw\c\src}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\simulink\src}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\simulink\src}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\simulink\src}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\simulink\src}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\toolbox\simulink\blocks\src}.c.obj :
+	$(CC) $(CFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\toolbox\simulink\blocks\src}.cpp.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\toolbox\simulink\blocks\src}.cc.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+{$(MATLAB_ROOT)\toolbox\simulink\blocks\src}.cxx.obj :
+	$(CPP) $(CPPFLAGS) -Fo"$@" "$<"
+
+
+ADM_Integrated_Logic.obj : "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic.c"
+	$(CC) $(CFLAGS) -Fo"$@" "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic.c"
+
+
+ADM_Integrated_Logic_data.obj : "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic_data.c"
+	$(CC) $(CFLAGS) -Fo"$@" "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ADM_Integrated_Logic_data.c"
+
+
+ert_main.obj : "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ert_main.c"
+	$(CC) $(CFLAGS) -Fo"$@" "$(START_DIR)\ADM_Integrated_Logic_ert_rtw\ert_main.c"
+
+
+###########################################################################
+## DEPENDENCIES
+###########################################################################
+
+$(ALL_OBJS) : rtw_proj.tmw $(COMPILER_COMMAND_FILE) $(MAKEFILE)
+
+
+###########################################################################
+## MISCELLANEOUS TARGETS
+###########################################################################
+
+info : 
+	@cmd /C "@echo ### PRODUCT = $(PRODUCT)"
+	@cmd /C "@echo ### PRODUCT_TYPE = $(PRODUCT_TYPE)"
+	@cmd /C "@echo ### BUILD_TYPE = $(BUILD_TYPE)"
+	@cmd /C "@echo ### INCLUDES = $(INCLUDES)"
+	@cmd /C "@echo ### DEFINES = $(DEFINES)"
+	@cmd /C "@echo ### ALL_SRCS = $(ALL_SRCS)"
+	@cmd /C "@echo ### ALL_OBJS = $(ALL_OBJS)"
+	@cmd /C "@echo ### LIBS = $(LIBS)"
+	@cmd /C "@echo ### MODELREF_LIBS = $(MODELREF_LIBS)"
+	@cmd /C "@echo ### SYSTEM_LIBS = $(SYSTEM_LIBS)"
+	@cmd /C "@echo ### TOOLCHAIN_LIBS = $(TOOLCHAIN_LIBS)"
+	@cmd /C "@echo ### CFLAGS = $(CFLAGS)"
+	@cmd /C "@echo ### LDFLAGS = $(LDFLAGS)"
+	@cmd /C "@echo ### SHAREDLIB_LDFLAGS = $(SHAREDLIB_LDFLAGS)"
+	@cmd /C "@echo ### CPPFLAGS = $(CPPFLAGS)"
+	@cmd /C "@echo ### CPP_LDFLAGS = $(CPP_LDFLAGS)"
+	@cmd /C "@echo ### CPP_SHAREDLIB_LDFLAGS = $(CPP_SHAREDLIB_LDFLAGS)"
+	@cmd /C "@echo ### ARFLAGS = $(ARFLAGS)"
+	@cmd /C "@echo ### MEX_CFLAGS = $(MEX_CFLAGS)"
+	@cmd /C "@echo ### MEX_CPPFLAGS = $(MEX_CPPFLAGS)"
+	@cmd /C "@echo ### MEX_LDFLAGS = $(MEX_LDFLAGS)"
+	@cmd /C "@echo ### MEX_CPPLDFLAGS = $(MEX_CPPLDFLAGS)"
+	@cmd /C "@echo ### DOWNLOAD_FLAGS = $(DOWNLOAD_FLAGS)"
+	@cmd /C "@echo ### EXECUTE_FLAGS = $(EXECUTE_FLAGS)"
+	@cmd /C "@echo ### MAKE_FLAGS = $(MAKE_FLAGS)"
+
+
+clean : 
+	$(ECHO) "### Deleting all derived files ..."
+	@if exist $(PRODUCT) $(RM) $(PRODUCT)
+	$(RM) $(ALL_OBJS)
+	$(ECHO) "### Deleted all derived files."
+
+

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic.rsp

@@ -0,0 +1,3 @@
+ADM_Integrated_Logic.obj
+ADM_Integrated_Logic_data.obj
+ert_main.obj

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic_comp.rsp

@@ -0,0 +1,7 @@
+-I"C:\Users\MSI\SynologyDrive\3min_be\한자연\!과제\배송모빌리티\!진행상황\2025\25-04-28-월 통합 로직 수정본 수신(시뮬링크)"
+-I"C:\Users\MSI\SynologyDrive\3min_be\한자연\!과제\배송모빌리티\!진행상황\2025\25-04-28-월 통합 로직 수정본 수신(시뮬링크)\ADM_Integrated_Logic_ert_rtw"
+-I"C:\Program Files\MATLAB\R2024a\extern\include"
+-I"C:\Program Files\MATLAB\R2024a\simulink\include"
+-I"C:\Program Files\MATLAB\R2024a\rtw\c\src"
+-I"C:\Program Files\MATLAB\R2024a\rtw\c\src\ext_mode\common"
+-I"C:\Program Files\MATLAB\R2024a\rtw\c\ert"

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic_data.c

@@ -0,0 +1,35 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: ADM_Integrated_Logic_data.c
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#include "ADM_Integrated_Logic.h"
+
+/* Invariant block signals (default storage) */
+const ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB = {
+  12753.0,                             /* '<S39>/Multiply' */
+  12753.0                              /* '<S39>/Multiply4' */
+};
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic_private.h

@@ -0,0 +1,42 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: ADM_Integrated_Logic_private.h
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#ifndef ADM_Integrated_Logic_private_h_
+#define ADM_Integrated_Logic_private_h_
+#include <stdbool.h>
+#include <stdint.h>
+#include "complex_types.h"
+#include "ADM_Integrated_Logic_types.h"
+#include "ADM_Integrated_Logic.h"
+
+extern void ADM_Integrated_Lo_Calculate_F_c(double rtu_W, double rtu_theta,
+  double *rty_F_c);
+extern void ADM_Integrated__MATLABFunction1(double rtu_u, double *rty_y);
+extern void ADM_Integrated__MATLABFunction2(double rtu_u, double *rty_y);
+
+#endif                                 /* ADM_Integrated_Logic_private_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic_ref.rsp

@@ -0,0 +1 @@
+

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ADM_Integrated_Logic_types.h

@@ -0,0 +1,35 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: ADM_Integrated_Logic_types.h
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#ifndef ADM_Integrated_Logic_types_h_
+#define ADM_Integrated_Logic_types_h_
+
+/* Forward declaration for rtModel */
+typedef struct tag_RTM_ADM_Integrated_Logic_T RT_MODEL_ADM_Integrated_Logic_T;
+
+#endif                                 /* ADM_Integrated_Logic_types_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/complex_types.h

@@ -0,0 +1,106 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: complex_types.h
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#ifndef COMPLEX_TYPES_H
+#define COMPLEX_TYPES_H
+#include <stdint.h>
+
+/*===========================================================================*
+ * Complex number type definitions                                           *
+ *===========================================================================*/
+#define CREAL_T
+
+typedef struct {
+  float re;
+  float im;
+} creal32_T;
+
+typedef struct {
+  double re;
+  double im;
+} creal_T;
+
+typedef creal_T creal64_T;
+
+#define CINT8_T
+
+typedef struct {
+  int8_t re;
+  int8_t im;
+} cint8_T;
+
+#define CUINT8_T
+
+typedef struct {
+  uint8_t re;
+  uint8_t im;
+} cuint8_T;
+
+#define CINT16_T
+
+typedef struct {
+  int16_t re;
+  int16_t im;
+} cint16_T;
+
+#define CUINT16_T
+
+typedef struct {
+  uint16_t re;
+  uint16_t im;
+} cuint16_T;
+
+#define CINT32_T
+
+typedef struct {
+  int32_t re;
+  int32_t im;
+} cint32_T;
+
+#define CUINT32_T
+
+typedef struct {
+  uint32_t re;
+  uint32_t im;
+} cuint32_T;
+
+#define CINT64_T
+
+typedef struct {
+  int64_t re;
+  int64_t im;
+} cint64_T;
+
+#define CUINT64_T
+
+typedef struct {
+  uint64_t re;
+  uint64_t im;
+} cuint64_T;
+
+#endif                                 /* COMPLEX_TYPES_H */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/ert_main.c

@@ -0,0 +1,111 @@
+/*
+ * Academic License - for use in teaching, academic research, and meeting
+ * course requirements at degree granting institutions only.  Not for
+ * government, commercial, or other organizational use.
+ *
+ * File: ert_main.c
+ *
+ * Code generated for Simulink model 'ADM_Integrated_Logic'.
+ *
+ * Model version                  : 13.55
+ * Simulink Coder version         : 24.1 (R2024a) 19-Nov-2023
+ * C/C++ source code generated on : Wed May  7 21:12:17 2025
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: NXP->Cortex-M4
+ * Code generation objectives:
+ *    1. Execution efficiency
+ *    2. RAM efficiency
+ *    3. Debugging
+ * Validation result: Not run
+ */
+
+#include <stddef.h>
+#include <stdio.h>            /* This example main program uses printf/fflush */
+#include "ADM_Integrated_Logic.h"      /* Model header file */
+
+/*
+ * Associating rt_OneStep with a real-time clock or interrupt service routine
+ * is what makes the generated code "real-time".  The function rt_OneStep is
+ * always associated with the base rate of the model.  Subrates are managed
+ * by the base rate from inside the generated code.  Enabling/disabling
+ * interrupts and floating point context switches are target specific.  This
+ * example code indicates where these should take place relative to executing
+ * the generated code step function.  Overrun behavior should be tailored to
+ * your application needs.  This example simply sets an error status in the
+ * real-time model and returns from rt_OneStep.
+ */
+void rt_OneStep(void);
+void rt_OneStep(void)
+{
+  static bool OverrunFlag = false;
+
+  /* Disable interrupts here */
+
+  /* Check for overrun */
+  if (OverrunFlag) {
+    return;
+  }
+
+  OverrunFlag = true;
+
+  /* Save FPU context here (if necessary) */
+  /* Re-enable timer or interrupt here */
+  /* Set model inputs here */
+
+  /* Step the model */
+  ADM_Integrated_Logic_step();
+
+  /* Get model outputs here */
+
+  /* Indicate task complete */
+  OverrunFlag = false;
+
+  /* Disable interrupts here */
+  /* Restore FPU context here (if necessary) */
+  /* Enable interrupts here */
+}
+
+/*
+ * The example main function illustrates what is required by your
+ * application code to initialize, execute, and terminate the generated code.
+ * Attaching rt_OneStep to a real-time clock is target specific. This example
+ * illustrates how you do this relative to initializing the model.
+ */
+int main(int argc, const char *argv[])
+{
+  /* Unused arguments */
+  (void)(argc);
+  (void)(argv);
+
+  /* Initialize model */
+  ADM_Integrated_Logic_initialize();
+
+  /* Attach rt_OneStep to a timer or interrupt service routine with
+   * period 0.002 seconds (base rate of the model) here.
+   * The call syntax for rt_OneStep is
+   *
+   *  rt_OneStep();
+   */
+  printf("Warning: The simulation will run forever. "
+         "Generated ERT main won't simulate model step behavior. "
+         "To change this behavior select the 'MAT-file logging' option.\n");
+  fflush((NULL));
+  while (1) {
+    /*  Perform application tasks here */
+  }
+
+  /* The option 'Remove error status field in real-time model data structure'
+   * is selected, therefore the following code does not need to execute.
+   */
+
+  /* Terminate model */
+  ADM_Integrated_Logic_terminate();
+  return 0;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/html/_internal.html

@@ -0,0 +1,57 @@
+<!doctype html>
+<html>
+<head>
+    <meta charset="utf-8">
+    <meta http-equiv="cache-control" content="no-cache">
+    <meta http-equiv="pragma" content="no-cache">
+    <meta http-equiv="expires" content="-1">
+    <!-- Always force latest IE rendering engine (even in intranet) & Chrome Frame -->
+    <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1">
+
+    <title>Code Generation Report</title>
+
+    <link rel="stylesheet" href="lib/index-css.css" type="text/css" /> 
+	
+</head>
+<body class="tundra reportV2">
+    <script src="data/data.js"></script>
+    <script src="data/pages.js"></script>
+    <script src="data/model.js"></script>
+    <script src="lib/slcoderRpt/dojoConfig-release-global.js"></script>
+
+    <div class="reportPage_root_container" data-dojo-type="dijit/layout/BorderContainer"
+         data-dojo-props="design: 'headline'">
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+</html>
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[ADM] Integrated Logic/ADM_Integrated_Logic_ert_rtw/html/data/model.js

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+var reportPages = [["Summary","ADM_Integrated_Logic_survey.html"],["Subsystem Report","ADM_Integrated_Logic_subsystems.html"],["Code Interface Report","ADM_Integrated_Logic_interface.html"],["Traceability Report","ADM_Integrated_Logic_trace.html"],["Static Code Metrics Report","ADM_Integrated_Logic_metrics.html"],["Eliminated Blocks","ADM_Integrated_Logic_reducedblocks.html"],["Code Replacements Report","ADM_Integrated_Logic_replacements.html"],["Coder Assumptions","ADM_Integrated_Logic_coderassumptions.html"]];

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