CgmXPcfsSdurDivcDiveDivs (const struct Clock_Ip_PcfsConfigType * config)
{
  uint32 swIndex;
  uint32 hwIndex;
  uint32 instance;
  <unnamed type> _1;
  int _2;
  unsigned char _3;
  <unnamed type> _4;
  int _5;
  unsigned char _6;
  <unnamed type> _7;
  int _8;
  unsigned char _9;
  long unsigned int _10;
  volatile struct cgmPcfs_Type * _11;
  long unsigned int _12;
  long unsigned int _13;
  long unsigned int _14;
  long unsigned int _15;
  long unsigned int _16;
  volatile struct cgmPcfs_Type * _17;
  long unsigned int _18;
  long unsigned int _19;
  volatile struct cgmPcfs_Type * _20;
  long unsigned int _21;
  long unsigned int _22;
  volatile struct cgmPcfs_Type * _23;
  long unsigned int _24;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = config_26(D)->name;
  _2 = (int) _1;
  _3 = clockFeatures[_2][2];
  instance_27 = (uint32) _3;
  # DEBUG instance => instance_27
  # DEBUG BEGIN_STMT
  _4 = config_26(D)->name;
  _5 = (int) _4;
  _6 = clockFeatures[_5][4];
  hwIndex_28 = (uint32) _6;
  # DEBUG hwIndex => hwIndex_28
  # DEBUG BEGIN_STMT
  _7 = config_26(D)->name;
  _8 = (int) _7;
  _9 = clockFeatures[_8][5];
  swIndex_29 = (uint32) _9;
  # DEBUG swIndex => swIndex_29
  # DEBUG BEGIN_STMT
  _10 = pcfsEntries[swIndex_29].sdur;
  _11 = cgmPcfs[instance_27];
  _12 = _10 & 65535;
  _11->PCFS_SDUR ={v} _12;
  # DEBUG BEGIN_STMT
  _13 = pcfsEntries[swIndex_29].divc_rate;
  _14 = _13 & 255;
  _15 = pcfsEntries[swIndex_29].divc_init;
  _16 = _15 << 16;
  _17 = cgmPcfs[instance_27];
  _18 = _14 | _16;
  _17->PCFS[hwIndex_28].DIVC ={v} _18;
  # DEBUG BEGIN_STMT
  _19 = pcfsEntries[swIndex_29].div_endValue;
  _20 = cgmPcfs[instance_27];
  _21 = _19 & 1048575;
  _20->PCFS[hwIndex_28].DIVE ={v} _21;
  # DEBUG BEGIN_STMT
  _22 = pcfsEntries[swIndex_29].div_startValue;
  _23 = cgmPcfs[instance_27];
  _24 = _22 & 1048575;
  _23->PCFS[hwIndex_28].DIVS ={v} _24;
  return;

}


ProgressiveFrequencyClockSwitchEmpty (const struct Clock_Ip_PcfsConfigType * config)
{
  <bb 2> :
  # DEBUG BEGIN_STMT
  return;

}


