/*
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * File: ADM_Integrated_Logic.h
 *
 * Code generated for Simulink model 'ADM_Integrated_Logic'.
 *
 * Model version                  : 14.11
 * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024
 * C/C++ source code generated on : Wed Oct  1 13:12:45 2025
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: NXP->Cortex-M4
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 *    3. Debugging
 * Validation result: Not run
 */

#ifndef ADM_Integrated_Logic_h_
#define ADM_Integrated_Logic_h_
#ifndef ADM_Integrated_Logic_COMMON_INCLUDES_
#define ADM_Integrated_Logic_COMMON_INCLUDES_
#include <stdbool.h>
#include <stdint.h>
#endif                               /* ADM_Integrated_Logic_COMMON_INCLUDES_ */

/* Macros for accessing real-time model data structure */
#ifndef rtmGetErrorStatus
#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
#endif

#ifndef rtmSetErrorStatus
#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
#endif

/* Forward declaration for rtModel */
typedef struct tag_RTM_ADM_Integrated_Logic_T RT_MODEL_ADM_Integrated_Logic_T;

/* Block signals and states (default storage) for system '<Root>' */
typedef struct {
  double Delay_DSTATE_c[2];            /* '<S38>/Delay' */
  double Delay3_DSTATE[2];             /* '<S38>/Delay3' */
  double Delay_DSTATE_p[2];            /* '<S30>/Delay' */
  double Delay3_DSTATE_h[2];           /* '<S30>/Delay3' */
  double Memory_DSTATE;                /* '<S7>/Memory' */
  double Integrator_2_DSTATE;          /* '<S8>/Integrator_2' */
  double Delay_DSTATE;                 /* '<S50>/Delay' */
  double Delay_DSTATE_i;               /* '<S49>/Delay' */
  double DiscreteTransferFcn_states;   /* '<S1>/Discrete Transfer Fcn' */
  double d1_DSTATE;                    /* '<S44>/d1' */
  double d_DSTATE;                     /* '<S44>/d' */
  double d1_DSTATE_i;                  /* '<S45>/d1' */
  double d_DSTATE_p;                   /* '<S45>/d' */
  double d1_DSTATE_o;                  /* '<S46>/d1' */
  double d_DSTATE_n;                   /* '<S46>/d' */
  double Integrator_1_DSTATE;          /* '<S8>/Integrator_1' */
  double d1_DSTATE_a;                  /* '<S47>/d1' */
  double d_DSTATE_d;                   /* '<S47>/d' */
  double d1_DSTATE_c;                  /* '<S24>/d1' */
  double d_DSTATE_l;                   /* '<S24>/d' */
  double d_DSTATE_i;                   /* '<S34>/d' */
  double d1_DSTATE_p;                  /* '<S34>/d1' */
  double d_DSTATE_c;                   /* '<S35>/d' */
  double d1_DSTATE_h;                  /* '<S35>/d1' */
  double d_DSTATE_db;                  /* '<S36>/d' */
  double d1_DSTATE_l;                  /* '<S36>/d1' */
  double Delay1_DSTATE;                /* '<S38>/Delay1' */
  double Delay2_DSTATE;                /* '<S38>/Delay2' */
  double d1_DSTATE_e;                  /* '<S37>/d1' */
  double d_DSTATE_ij;                  /* '<S37>/d' */
  double d_DSTATE_ir;                  /* '<S26>/d' */
  double d1_DSTATE_of;                 /* '<S26>/d1' */
  double d_DSTATE_m;                   /* '<S27>/d' */
  double d1_DSTATE_hm;                 /* '<S27>/d1' */
  double d_DSTATE_mw;                  /* '<S28>/d' */
  double d1_DSTATE_g;                  /* '<S28>/d1' */
  double d1_DSTATE_ej;                 /* '<S29>/d1' */
  double d_DSTATE_j;                   /* '<S29>/d' */
  double Delay1_DSTATE_c;              /* '<S30>/Delay1' */
  double Delay2_DSTATE_n;              /* '<S30>/Delay2' */
  double Delay_DSTATE_c4;              /* '<S16>/Delay' */
  double Delay_DSTATE_i1;              /* '<S17>/Delay' */
  double PrevY;                        /* '<S18>/Input_Vx_RateLimiter' */
  double PrevY_o;                      /* '<S4>/Brake_Out_RateLimiter' */
  double PrevY_a;                      /* '<S4>/TargetSpd_RateLimiter' */
  double Memory_PreviousInput;         /* '<S4>/Memory' */
  double HAC_ON_FLAG;                  /* '<S8>/HAC_OFF_OK_Func' */
  double Smoothed_Torque;              /* '<S8>/HAC_OFF_OK_Func' */
  double HAC_Desired_Torque;           /* '<S8>/HAC_OFF_OK_Func' */
  double HAC_ON_Timer;                 /* '<S8>/HAC_OFF_OK_Func' */
  uint8_t is_active_c6_ADM_Integrated_Log;/* '<S8>/Chart' */
  uint8_t is_c6_ADM_Integrated_Logic;  /* '<S8>/Chart' */
  bool icLoad;                         /* '<S50>/Delay' */
  bool icLoad_e;                       /* '<S49>/Delay' */
  bool icLoad_l;                       /* '<S16>/Delay' */
  bool icLoad_d;                       /* '<S17>/Delay' */
} DW_ADM_Integrated_Logic_T;

/* Invariant block signals (default storage) */
typedef struct {
  const double W_value;                /* '<S43>/Multiply' */
  const double W_Value_for_Brake;      /* '<S43>/Multiply4' */
} ConstB_ADM_Integrated_Logic_T;

/* External inputs (root inport signals with default storage) */
typedef struct {
  double GV_MCU_RPM;                   /* '<Root>/GV_MCU_RPM' */
  double GV_BrakeTorqueCommand;        /* '<Root>/GV_BrakeTorqueCommand' */
  double GV_IMU_AX_Val;                /* '<Root>/GV_IMU_AX_Val' */
  double GV_IMU_AY_Val;                /* '<Root>/GV_IMU_AY_Val' */
  double GV_IMU_AZ_Val;                /* '<Root>/GV_IMU_AZ_Val' */
  double GV_IMU_PitchRtVal;            /* '<Root>/GV_IMU_PitchRtVal' */
  double GV_Vx_Command;                /* '<Root>/GV_Vx_Command' */
  double GV_VCU_GearSelStat;           /* '<Root>/GV_VCU_GearSelStat' */
  double GV_MCU_EstTrq;                /* '<Root>/GV_MCU_EstTrq' */
  double GV_Vx_Limit;                  /* '<Root>/GV_Vx_Limit' */
  double GV_Vx_Fbk;                    /* '<Root>/GV_Vx_Fbk' */
  double GV_RWA_RackAngleCommand;      /* '<Root>/GV_RWA_RackAngleCommand' */
  double GV_RWS_RackAngleCommand;      /* '<Root>/GV_RWS_RackAngleCommand' */
  double GV_Drive_Mode;                /* '<Root>/GV_Drive_Mode' */
  double GV_ACU_Fault_Flag;            /* '<Root>/GV_ACU_Fault_Flag' */
  double GV_MCU_Actuator_Fault_Flag;   /* '<Root>/GV_MCU_Actuator_Fault_Flag' */
  double GV_IDB_ECU_Fault_Flag;        /* '<Root>/GV_IDB_ECU_Fault_Flag' */
  double GV_RCU_ECU_Fault_Flag;        /* '<Root>/GV_RCU_ECU_Fault_Flag' */
  double GV_RWA1_ECU_Fault_Flag;       /* '<Root>/GV_RWA1_ECU_Fault_Flag' */
  double GV_RWA2_ECU_Fault_Flag;       /* '<Root>/GV_RWA2_ECU_Fault_Flag' */
  double GV_RWA_Actuator_Fault;        /* '<Root>/GV_RWA_Actuator_Fault' */
  double GV_ACU_ECU_Fault_Flag;        /* '<Root>/GV_ACU_ECU_Fault_Flag' */
  double GV_ACU_ECU_Fault_Flag1;       /* '<Root>/GV_ACU_ECU_Fault_Flag1' */
  double GV_ACU_ECU_Fault_Flag2;       /* '<Root>/GV_ACU_ECU_Fault_Flag2' */
  double GV_ACU_ECU_Fault_Flag3;       /* '<Root>/GV_ACU_ECU_Fault_Flag3' */
} ExtU_ADM_Integrated_Logic_T;

/* External outputs (root outports fed by signals with default storage) */
typedef struct {
  double GV_Brake_Command;             /* '<Root>/GV_Brake_Command' */
  double GV_Master_Rack_Angle_Cmd;     /* '<Root>/GV_Master_Rack_Angle_Cmd' */
  double GV_Hill_Torque_Assist;        /* '<Root>/GV_Hill_Torque_Assist' */
  double GV_Motor_Torque_Cmd;          /* '<Root>/GV_Motor_Torque_Cmd' */
  double Debug_HAC_FLAG;               /* '<Root>/Debug_HAC_FLAG' */
  double Debug_HAC_RPM_Decision;       /* '<Root>/Debug_HAC_RPM_Decision' */
  double Debug_HAC_Pitch_angle;        /* '<Root>/Debug_HAC_Pitch_angle' */
  double Debug_HAC_Brake_Output;       /* '<Root>/Debug_HAC_Brake_Output' */
  double Debug_CC_Brake_Output;        /* '<Root>/Debug_CC_Brake_Output' */
  double GV_RWS_RackAngleCmd1;         /* '<Root>/GV_RWS_RackAngleCmd1' */
  double GV_Speed_Limit;               /* '<Root>/GV_Speed_Limit' */
  double GV_Gear_Postion_Out;          /* '<Root>/GV_Gear_Postion_Out' */
  double Act_Fault_Exist;              /* '<Root>/Act_Fault_Exist' */
  double Target_RWA_Out;               /* '<Root>/Target_RWA_Out' */
  double Target_IDB_Out;               /* '<Root>/Target_IDB_Out' */
  double Target_MCU_Out;               /* '<Root>/Target_MCU_Out' */
} ExtY_ADM_Integrated_Logic_T;

/* Real-time Model Data Structure */
struct tag_RTM_ADM_Integrated_Logic_T {
  const char * volatile errorStatus;
};

/* Block signals and states (default storage) */
extern DW_ADM_Integrated_Logic_T ADM_Integrated_Logic_DW;

/* External inputs (root inport signals with default storage) */
extern ExtU_ADM_Integrated_Logic_T ADM_Integrated_Logic_U;

/* External outputs (root outports fed by signals with default storage) */
extern ExtY_ADM_Integrated_Logic_T ADM_Integrated_Logic_Y;
extern const ConstB_ADM_Integrated_Logic_T ADM_Integrated_Logic_ConstB;/* constant block i/o */

/* Model entry point functions */
extern void ADM_Integrated_Logic_initialize(void);
extern void ADM_Integrated_Logic_step(void);

/* Real-time Model object */
extern RT_MODEL_ADM_Integrated_Logic_T *const ADM_Integrated_Logic_M;

/*-
 * These blocks were eliminated from the model due to optimizations:
 *
 * Block '<S21>/BW_PI' : Unused code path elimination
 * Block '<S21>/Constant1' : Unused code path elimination
 * Block '<S21>/Constant16' : Unused code path elimination
 * Block '<S21>/Constant17' : Unused code path elimination
 * Block '<S21>/Constant2' : Unused code path elimination
 * Block '<S43>/Brake_Saturation' : Unused code path elimination
 * Block '<S43>/Multiply5' : Unused code path elimination
 * Block '<S43>/Radius1' : Unused code path elimination
 * Block '<S49>/FixPt Data Type Duplicate' : Unused code path elimination
 * Block '<S54>/Data Type Duplicate' : Unused code path elimination
 * Block '<S54>/Data Type Propagation' : Unused code path elimination
 * Block '<S50>/FixPt Data Type Duplicate' : Unused code path elimination
 * Block '<S55>/Data Type Duplicate' : Unused code path elimination
 * Block '<S55>/Data Type Propagation' : Unused code path elimination
 * Block '<S8>/Scope2' : Unused code path elimination
 * Block '<S16>/FixPt Data Type Duplicate' : Unused code path elimination
 * Block '<S56>/Data Type Duplicate' : Unused code path elimination
 * Block '<S56>/Data Type Propagation' : Unused code path elimination
 * Block '<S17>/FixPt Data Type Duplicate' : Unused code path elimination
 * Block '<S57>/Data Type Duplicate' : Unused code path elimination
 * Block '<S57>/Data Type Propagation' : Unused code path elimination
 * Block '<S4>/ControlFlag' : Eliminated nontunable gain of 1
 * Block '<S21>/FBGain' : Eliminated nontunable gain of 1
 * Block '<S32>/FFGain' : Eliminated nontunable gain of 1
 * Block '<S1>/Data Type Conversion1' : Eliminate redundant data type conversion
 * Block '<S1>/Data Type Conversion3' : Eliminate redundant data type conversion
 * Block '<S43>/HAC_Gain' : Eliminated nontunable gain of 1
 * Block '<S49>/Zero-Order Hold' : Eliminated since input and output rates are identical
 * Block '<S50>/Zero-Order Hold' : Eliminated since input and output rates are identical
 * Block '<S16>/Zero-Order Hold' : Eliminated since input and output rates are identical
 * Block '<S17>/Zero-Order Hold' : Eliminated since input and output rates are identical
 */

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'ADM_Integrated_Logic'
 * '<S1>'   : 'ADM_Integrated_Logic/Delivery_Mobility'
 * '<S2>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Actuator_Fault_Decision'
 * '<S3>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Compare To Constant'
 * '<S4>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1'
 * '<S5>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Brake_Func'
 * '<S6>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Emergency_Motor_Func'
 * '<S7>'   : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position'
 * '<S8>'   : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1'
 * '<S9>'   : 'ADM_Integrated_Logic/Delivery_Mobility/IDB_Fault_Injection'
 * '<S10>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function1'
 * '<S11>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function2'
 * '<S12>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function5'
 * '<S13>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MATLAB Function6'
 * '<S14>'  : 'ADM_Integrated_Logic/Delivery_Mobility/MCU_Fault_Injection'
 * '<S15>'  : 'ADM_Integrated_Logic/Delivery_Mobility/RWA_Actuator_Fault_Injection'
 * '<S16>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic'
 * '<S17>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1'
 * '<S18>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic'
 * '<S19>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB'
 * '<S20>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB_Gain'
 * '<S21>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller'
 * '<S22>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/GearCondition_Brake'
 * '<S23>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Gear_pos_out'
 * '<S24>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/LPFM'
 * '<S25>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/Target_RPM'
 * '<S26>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot3'
 * '<S27>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot4'
 * '<S28>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Dot5'
 * '<S29>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/LPFM'
 * '<S30>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/DOB/Second order LPF'
 * '<S31>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB'
 * '<S32>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF'
 * '<S33>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FB/P'
 * '<S34>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot'
 * '<S35>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot2'
 * '<S36>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Dot3'
 * '<S37>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/LPFM'
 * '<S38>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Cruise_Control1/FF_PID_Controller/FF/Second order LPF'
 * '<S39>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Compare To Constant'
 * '<S40>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Gear_Position/Gear_FUNCTION1'
 * '<S41>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Chart'
 * '<S42>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/HAC_OFF_OK_Func'
 * '<S43>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2'
 * '<S44>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM'
 * '<S45>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM1'
 * '<S46>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM2'
 * '<S47>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/LPFM3'
 * '<S48>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Pitch_calculate'
 * '<S49>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic'
 * '<S50>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1'
 * '<S51>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_R'
 * '<S52>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c'
 * '<S53>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Hill_Required_Torque2/Calculate_F_c1'
 * '<S54>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic/Saturation Dynamic'
 * '<S55>'  : 'ADM_Integrated_Logic/Delivery_Mobility/HAC_Logic1/Rate Limiter Dynamic1/Saturation Dynamic'
 * '<S56>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic/Saturation Dynamic'
 * '<S57>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Rate Limiter Dynamic1/Saturation Dynamic'
 * '<S58>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Compare To Constant'
 * '<S59>'  : 'ADM_Integrated_Logic/Delivery_Mobility/Vx_Logic/Vx_OutPut_Function'
 */

/*-
 * Requirements for '<Root>': ADM_Integrated_Logic

 */
#endif                                 /* ADM_Integrated_Logic_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
