/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : 
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 0.9.0
*   Build Version        : S32K3_RTD_0_9_0__ASR_REL_4_4_REV_0000_20210326
*
*   (c) Copyright 2020 - 2021 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

/**
*   @file
*
*   @addtogroup RTE_MODULE
*   @{
*/

#ifdef __cplusplus
extern "C"{
#endif

/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Std_Types.h"
#include "Mcal.h"
#include "OsIf.h"
#include "SchM_Adc.h"
#ifdef MCAL_TESTING_ENVIRONMENT
#include "EUnit.h" /* EUnit Test Suite */
#endif

/*==================================================================================================
*                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define SCHM_ADC_AR_RELEASE_MAJOR_VERSION_C     4
#define SCHM_ADC_AR_RELEASE_MINOR_VERSION_C     4
#define SCHM_ADC_AR_RELEASE_REVISION_VERSION_C  0
#define SCHM_ADC_SW_MAJOR_VERSION_C             0
#define SCHM_ADC_SW_MINOR_VERSION_C             9
#define SCHM_ADC_SW_PATCH_VERSION_C             0

/*==================================================================================================
*                                       LOCAL CONSTANTS
==================================================================================================*/
#ifdef MCAL_PLATFORM_ARM
    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
        #define ISR_STATE_MASK     ((uint32)0x00000002UL)   /**< @brief DAIF bit I and F */
    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
        #define ISR_STATE_MASK     ((uint32)0x00000080UL)   /**< @brief CPSR bit I */
    #else
        #ifdef MCAL_ENABLE_USER_MODE_SUPPORT
            #define ISR_STATE_MASK     ((uint32)0x000000FFUL)   /**< @brief BASEPRI[7:0] mask */
        #else
            #define ISR_STATE_MASK     ((uint32)0x00000001UL)   /**< @brief PRIMASK bit 0 */
        #endif
    #endif 
#else
    #ifdef MCAL_PLATFORM_S12
        #define ISR_STATE_MASK     ((uint32)0x00000010UL)   /**< @brief I bit of CCR */
    #else
        #define ISR_STATE_MASK     ((uint32)0x00008000UL)   /**< @brief EE bit of MSR */
    #endif
#endif
/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/
#ifdef MCAL_PLATFORM_ARM
    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)3)
    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
    #else
        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
    #endif    
#else
    #ifdef MCAL_PLATFORM_S12
        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
    #else
        #define ISR_ON(msr)            (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
    #endif
#endif

/*==================================================================================================
*                                      FILE VERSION CHECKS
==================================================================================================*/

/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/


/*==================================================================================================
*                                       LOCAL VARIABLES
==================================================================================================*/
#define RTE_START_SEC_VAR_NO_INIT_32_NO_CACHEABLE
#include "Rte_MemMap.h"
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_00[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_00[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_01[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_01[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_02[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_02[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_03[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_03[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_04[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_04[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_05[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_05[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_10[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_10[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_11[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_11[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_12[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_12[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_13[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_13[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_14[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_14[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_15[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_15[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_16[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_16[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_17[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_17[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_18[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_18[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_19[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_19[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_20[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_20[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_21[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_21[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_22[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_22[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_23[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_23[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_24[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_24[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_25[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_25[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_26[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_26[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_27[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_27[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_28[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_28[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_29[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_29[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_30[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_30[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_31[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_31[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_32[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_32[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_33[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_33[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_34[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_34[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_35[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_35[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_36[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_36[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_37[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_37[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_38[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_38[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_39[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_39[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_40[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_40[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_41[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_41[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_42[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_42[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_43[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_43[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_44[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_44[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_45[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_45[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_46[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_46[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_47[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_47[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_48[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_48[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_49[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_49[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_50[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_50[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_54[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_54[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_55[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_55[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_56[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_56[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_57[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_57[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_58[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_58[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_59[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_59[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_60[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_60[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_61[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_61[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_62[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_62[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_63[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_63[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_64[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_64[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_65[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_65[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_66[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_66[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_67[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_67[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_68[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_68[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_69[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_69[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_70[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_70[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_71[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_71[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_72[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_72[10U];
static volatile uint32 msr_ADC_EXCLUSIVE_AREA_73[10U];
static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_73[10U];

#define RTE_STOP_SEC_VAR_NO_INIT_32_NO_CACHEABLE
#include "Rte_MemMap.h"
/*==================================================================================================
*                                       GLOBAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                       GLOBAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/

#ifndef _COSMIC_C_S32K3XX_
/*================================================================================================*/
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
uint32 Adc_schm_read_msr(void); 
#endif /*ifndef _COSMIC_C_S32K3XX_*/
/*==================================================================================================
*                                       LOCAL FUNCTIONS
==================================================================================================*/
#define RTE_START_SEC_CODE
#include "Rte_MemMap.h"

#if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
/*================================================================================================*/
/** 
* @brief   This macro returns the MSR register value (32 bits). 
* @details This macro function implementation returns the MSR register value in r3 (32 bits). 
*     
* @pre  None
* @post None
* 
*/
#ifdef MCAL_PLATFORM_ARM
#if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
    mrs x0, S3_3_c4_c2_1
}
#elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
    mrs r0, CPSR
}
#else
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
    mrs r0, BASEPRI
#else
    mrs r0, PRIMASK
#endif
}
#endif
#else
#ifdef MCAL_PLATFORM_S12
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
   tfr ccr, d6
}
#else
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
    mfmsr r3
}
#endif
#endif
#endif /*#ifdef GHS||CW*/

#ifdef _DIABDATA_C_S32K3XX_
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
#ifdef MCAL_PLATFORM_ARM
uint32 Adc_schm_read_msr(void)
{
    register uint32 reg_tmp;
    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
    #else
        #ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
        #else
        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
        #endif
    #endif
    return (uint32)reg_tmp;
}
#else
ASM_KEYWORD uint32 Adc_schm_read_msr(void)
{
    mfmsr r3
}    
#endif  /* MCAL_PLATFORM_ARM */

#endif   /* _DIABDATA_C_S32K3XX_*/

#ifdef _COSMIC_C_S32K3XX_
/*================================================================================================*/
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/

#ifdef MCAL_PLATFORM_S12
    #define Adc_schm_read_msr()  ASM_KEYWORD("tfr ccr, d6")
#else
    #define Adc_schm_read_msr() ASM_KEYWORD("mfmsr r3")
#endif

#endif  /*Cosmic compiler only*/


#ifdef _HITECH_C_S32K3XX_
/*================================================================================================*/
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
uint32 Adc_schm_read_msr(void)
{
    uint32 result;
    __asm volatile("mfmsr %0" : "=r" (result) :);
    return result;
}

#endif  /*HighTec compiler only*/
 /*================================================================================================*/
#ifdef _LINARO_C_S32K3XX_
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
uint32 Adc_schm_read_msr(void)
{
    register uint32 reg_tmp;
    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
    #else
        #ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
        #else
        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
        #endif
    #endif
    return (uint32)reg_tmp;
}
#endif   /* _LINARO_C_S32K3XX_*/
/*================================================================================================*/

#ifdef _ARM_DS5_C_S32K3XX_
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
uint32 Adc_schm_read_msr(void)
{
    register uint32 reg_tmp;
    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
    #else
        #ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
        #else
        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
        #endif
    #endif
    return (uint32)reg_tmp;
}
#endif   /* _ARM_DS5_C_S32K3XX_ */

#ifdef _IAR_C_S32K3XX_
/** 
* @brief   This function returns the MSR register value (32 bits). 
* @details This function returns the MSR register value (32 bits). 
*     
* @param[in]     void        No input parameters
* @return        uint32 msr  This function returns the MSR register value (32 bits). 
* 
* @pre  None
* @post None
* 
*/
uint32 Adc_schm_read_msr(void)
{
    register uint32 reg_tmp;

#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
   __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
#else
   __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
#endif

    return (uint32)reg_tmp;
}
#endif   /* _IAR_C_S32K3XX_ */

#define RTE_STOP_SEC_CODE
#include "Rte_MemMap.h"

/*==================================================================================================
*                                        GLOBAL FUNCTIONS
==================================================================================================*/
#define RTE_START_SEC_CODE
#include "Rte_MemMap.h"

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_00[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_00[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_00[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_01[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_01[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_01[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_02[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_02[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_02[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_03[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_03[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_03[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_04[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_04[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_04[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_05[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_05[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_05[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_10[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_10[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_10[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_11[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_11[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_11[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_12[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_12[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_12[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_13[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_13[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_13[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_14[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_14[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_14[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_15[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_15[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_15[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_16[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_16[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_16[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_17[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_17[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_17[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_18[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_18[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_18[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_19[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_19[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_19[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_20[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_20[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_20[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_21[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_21[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_21[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_22[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_22[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_22[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_23[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_23[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_23[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_24[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_24[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_24[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_25[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_25[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_25[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_26[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_26[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_26[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_27[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_27[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_27[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_28[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_28[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_28[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_29[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_29[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_29[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_30[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_30[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_30[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_31[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_31[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_31[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_32[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_32[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_32[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_33[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_33[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_33[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_34[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_34[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_34[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_35[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_35[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_35[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_36[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_36[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_36[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_37[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_37[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_37[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_37[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_38[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_38[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_38[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_39[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_39[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_39[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_40[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_40[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_40[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_41[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_41[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_41[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_42[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_42[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_42[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_43[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_43[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_43[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_44[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_44[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_44[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_45[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_45[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_45[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_46[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_46[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_46[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_47[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_47[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_47[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_48[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_48[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_48[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_49[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_49[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_49[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_50[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_50[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_50[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_54(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_54[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_54[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_54[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_54(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_55(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_55[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_55[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_55[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_55(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_56(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_56[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_56[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_56[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_56(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_57(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_57[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_57[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_57[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_57(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_58(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_58[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_58[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_58[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_58(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_59(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_59[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_59[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_59[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_59(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_60(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_60[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_60[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_60[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_60(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_61(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_61[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_61[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_61[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_61(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_62(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_62[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_62[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_62[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_62(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_63(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_63[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_63[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_63[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_63(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_64(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_64[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_64[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_64[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_64(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_64[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_65[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_65[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_65[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_65[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_66(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_66[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_66[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_66[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_66(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_66[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_67(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_67[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_67[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_67[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_67(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_67[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_68(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_68[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_68[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_68[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_68(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_68[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_69(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_69[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_69[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_69[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_69(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_69[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_70(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_70[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_70[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_70[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_70(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_70[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_71(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_71[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_71[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_71[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_71(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_71[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_72(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_72[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_72[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_72[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_72(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_72[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}

void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_73(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId])
    {
#ifdef MCAL_ENABLE_USER_MODE_SUPPORT
        msr_ADC_EXCLUSIVE_AREA_73[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
#else
        msr_ADC_EXCLUSIVE_AREA_73[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_73[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
        {
            OsIf_SuspendAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
        }
    }
    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]++;
}

void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_73(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]--;
    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_73[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]))         /*if interrupts were enabled*/
    {
        OsIf_ResumeAllInterrupts();
#ifdef _ARM_DS5_C_S32K3XX_
        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
#endif
    }
}


#ifdef MCAL_TESTING_ENVIRONMENT
/** 
@brief   This function checks that all entered exclusive areas were also exited. 
@details This function checks that all entered exclusive areas were also exited. The check
         is done by verifying that all reentry_guard_* static variables are back to the
         zero value.
    
@param[in]     void       No input parameters
@return        void       This function does not return a value. Test asserts are used instead. 

@pre  None
@post None

@remarks Covers 
@remarks Implements 
*/
void SchM_Check_adc(void)
{
    uint32 u32CoreId = (uint32)OsIf_GetCoreID();

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_00 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_01 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_02 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_03 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_04 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_05 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_10 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_11 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_12 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_13 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_14 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_15 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_16 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_17 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_18 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_19 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_20 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_21 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_22 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_23 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_24 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_25 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_26 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_27 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_28 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_29 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_30 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_31 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_32 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_33 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_34 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_35 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_36 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_37 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_38 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_39 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_40 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_41 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_42 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_43 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_44 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_45 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_46 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_47 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_48 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_49 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_50 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_54 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_55 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_56 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_57 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_58 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_59 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_60 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_61 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_62 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_63 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_64 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_65 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_66 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_67 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_68 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_69 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_70 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_71 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_72 for the next test in the suite*/

    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]);
    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_73 for the next test in the suite*/


}
#endif /*MCAL_TESTING_ENVIRONMENT*/

#define RTE_STOP_SEC_CODE
#include "Rte_MemMap.h"

#ifdef __cplusplus
}
#endif

/** @} */
