#ifndef SIUL2_PORT_IP_CFG_H
#define SIUL2_PORT_IP_CFG_H

#include "S32K344_SIUL2.h"
#include "Siul2_Port_Ip_Types.h"

/***********************************************************************************************************************
 * Definitions
 **********************************************************************************************************************/

/***********************************************************************************************************************
 * SOURCE FILE VERSION INFORMATION
 **********************************************************************************************************************/
#define SIUL2_PORT_IP_VENDOR_ID_CFG_H                       43
#define SIUL2_PORT_IP_AR_RELEASE_MAJOR_VERSION_CFG_H        4
#define SIUL2_PORT_IP_AR_RELEASE_MINOR_VERSION_CFG_H        4
#define SIUL2_PORT_IP_AR_RELEASE_REVISION_VERSION_CFG_H     0
#define SIUL2_PORT_IP_SW_MAJOR_VERSION_CFG_H                0
#define SIUL2_PORT_IP_SW_MINOR_VERSION_CFG_H                9
#define SIUL2_PORT_IP_SW_PATCH_VERSION_CFG_H                0

/*!
 * @addtogroup Siul2_Port_Ip_Cfg
 * @{
 */

/***********************************************************************************************************************
 * API
 **********************************************************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

/*! @brief Definitions for BOARD_InitPins Functional Group */

#define SIUL2_MSCR_SSS_MASK                      (0x7U)
#define SIUL2_MSCR_SSS_SHIFT                     (0U)
#define SIUL2_MSCR_SSS_WIDTH                     (3U)
#define SIUL2_MSCR_SSS(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SSS_SHIFT)) & SIUL2_MSCR_SSS_MASK)

#define SIUL2_MSCR_SRE_MASK                      (0x4000U)
#define SIUL2_MSCR_SRE_SHIFT                     (14U)
#define SIUL2_MSCR_SRE_WIDTH                     (1U)
#define SIUL2_MSCR_SRE(x)                        (((uint32)(((uint32)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK)

#define DEV_ASSERT(par)
/*! @brief User number of configured pins */
#define NUM_OF_CONFIGURED_PINS0 78
/*! @brief User configuration structure */
extern Siul2_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr0[NUM_OF_CONFIGURED_PINS0];


/*! @brief Defines for user pin and port configurations */
#define UART0_RX_PIN            2u
#define UART0_RX_PORT           PTA_L_HALF
#define UART0_TX_PIN            3u
#define UART0_TX_PORT           PTA_L_HALF
#define CAN0_RX_PIN             6u
#define CAN0_RX_PORT            PTA_L_HALF
#define CAN0_TX_PIN             7u
#define CAN0_TX_PORT            PTA_L_HALF
#define CAN0_EN_PIN             8u
#define CAN0_EN_PORT            PTC_H_HALF
#define CAN0_STB_N_PIN          5u
#define CAN0_STB_N_PORT         PTC_H_HALF
#define CAN1_TX_PIN             8u
#define CAN1_TX_PORT            PTC_L_HALF
#define CAN1_RX_PIN             9u
#define CAN1_RX_PORT            PTC_L_HALF
#define CAN1_EN_PIN             7u
#define CAN1_EN_PORT            PTD_H_HALF
#define CAN1_STB_N_PIN          2u
#define CAN1_STB_N_PORT         PTD_L_HALF
#define CAN2_TX_PIN             8u
#define CAN2_TX_PORT            PTE_H_HALF
#define CAN3_TX_PIN             12u
#define CAN3_TX_PORT            PTC_H_HALF
#define CAN3_RX_PIN             13u
#define CAN3_RX_PORT            PTC_H_HALF
#define CAN4_TX_PIN             14u
#define CAN4_TX_PORT            PTC_H_HALF
#define CAN4_RX_PIN             15u
#define CAN4_RX_PORT            PTC_H_HALF
#define CAN5_TX_PIN             10u
#define CAN5_TX_PORT            PTC_L_HALF
#define CAN5_RX_PIN             11u
#define CAN5_RX_PORT            PTC_L_HALF
#define CAN2_EN_PIN             4u
#define CAN2_EN_PORT            PTD_L_HALF
#define CAN3_EN_PIN             0u
#define CAN3_EN_PORT            PTB_L_HALF
#define CAN4_EN_PIN             10u
#define CAN4_EN_PORT            PTC_H_HALF
#define CAN5_EN_PIN             14u
#define CAN5_EN_PORT            PTD_H_HALF
#define CAN2_STB_N_PIN          6u
#define CAN2_STB_N_PORT         PTD_H_HALF
#define CAN3_STB_N_PIN          1u
#define CAN3_STB_N_PORT         PTB_L_HALF
#define CAN4_STB_N_PIN          9u
#define CAN4_STB_N_PORT         PTC_H_HALF
#define CAN5_STB_N_PIN          1u
#define CAN5_STB_N_PORT         PTE_H_HALF
#define UART1_TX_PIN            7u
#define UART1_TX_PORT           PTC_L_HALF
#define UART1_RX_PIN            6u
#define UART1_RX_PORT           PTC_L_HALF
#define UART10_RX_PIN           12u
#define UART10_RX_PORT          PTC_L_HALF
#define AIN_2_PIN               5u
#define AIN_2_PORT              PTE_H_HALF
#define AIN_3_PIN               6u
#define AIN_3_PORT              PTE_H_HALF
#define AIN_4_PIN               7u
#define AIN_4_PORT              PTE_H_HALF
#define DOUT_2_PIN              12u
#define DOUT_2_PORT             PTA_L_HALF
#define PWM_1_PIN               13u
#define PWM_1_PORT              PTB_L_HALF
#define PWM_2_PIN               14u
#define PWM_2_PORT              PTB_L_HALF
#define PWM_3_PIN               15u
#define PWM_3_PORT              PTB_L_HALF
#define PWM_0_PIN               12u
#define PWM_0_PORT              PTB_L_HALF
#define AIN_1_PIN               0u
#define AIN_1_PORT              PTE_L_HALF
#define TEST_LED_PIN            2u
#define TEST_LED_PORT           PTC_H_HALF
#define DOUT_0_PIN              0u
#define DOUT_0_PORT             PTA_L_HALF
#define UART2_RX_PIN            8u
#define UART2_RX_PORT           PTA_L_HALF
#define UART2_TX_PIN            9u
#define UART2_TX_PORT           PTA_L_HALF
#define DOUT_5_PIN              14u
#define DOUT_5_PORT             PTA_L_HALF
#define SPI1_CS0_PIN            5u
#define SPI1_CS0_PORT           PTA_H_HALF
#define SPI1_SCK_PIN            12u
#define SPI1_SCK_PORT           PTA_H_HALF
#define SPI1_MISO_PIN           14u
#define SPI1_MISO_PORT          PTA_H_HALF
#define UART10_TX_PIN           13u
#define UART10_TX_PORT          PTC_L_HALF
#define SPI2_CS1_PIN            3u
#define SPI2_CS1_PORT           PTC_H_HALF
#define SPI1_CS1_PIN            4u
#define SPI1_CS1_PORT           PTE_L_HALF
#define UART9_RX_PIN            2u
#define UART9_RX_PORT           PTB_L_HALF
#define UART9_TX_PIN            3u
#define UART9_TX_PORT           PTB_L_HALF
#define DIN_0_PIN               8u
#define DIN_0_PORT              PTB_L_HALF
#define DIN_3_PIN               11u
#define DIN_3_PORT              PTB_L_HALF
#define UART13_TX_PIN           2u
#define UART13_TX_PORT          PTB_H_HALF
#define UART13_RX_PIN           3u
#define UART13_RX_PORT          PTB_H_HALF
#define DIN_4_PIN               4u
#define DIN_4_PORT              PTB_H_HALF
#define DIN_5_PIN               5u
#define DIN_5_PORT              PTB_H_HALF
#define DIN_6_PIN               8u
#define DIN_6_PORT              PTB_H_HALF
#define SPI2_CS0_PIN            9u
#define SPI2_CS0_PORT           PTB_H_HALF
#define DIN_7_PIN               10u
#define DIN_7_PORT              PTB_H_HALF
#define SPI2_MISO_PIN           11u
#define SPI2_MISO_PORT          PTB_H_HALF
#define SPI2_MOSI_PIN           12u
#define SPI2_MOSI_PORT          PTB_H_HALF
#define SPI2_SCK_PIN            13u
#define SPI2_SCK_PORT           PTB_H_HALF
#define I2C1_SDA_PIN            8u
#define I2C1_SDA_PORT           PTD_L_HALF
#define I2C1_SCL_PIN            9u
#define I2C1_SCL_PORT           PTD_L_HALF
#define DOUT_4_PIN              13u
#define DOUT_4_PORT             PTA_L_HALF
#define DOUT_6_PIN              15u
#define DOUT_6_PORT             PTA_L_HALF
#define DOUT_7_PIN              0u
#define DOUT_7_PORT             PTA_H_HALF
#define CAN2_RX_PIN             9u
#define CAN2_RX_PORT            PTE_H_HALF
#define I2C0_SCL_PIN            14u
#define I2C0_SCL_PORT           PTD_L_HALF
#define I2C0_SDA_PIN            13u
#define I2C0_SDA_PORT           PTD_L_HALF
#define DIN_1_PIN               11u
#define DIN_1_PORT              PTA_L_HALF
#define DOUT_3_PIN              2u
#define DOUT_3_PORT             PTA_H_HALF
#define DIN_2_PIN               1u
#define DIN_2_PORT              PTE_L_HALF
#define DOUT_1_PIN              10u
#define DOUT_1_PORT             PTE_H_HALF
#define AIN_0_PIN               11u
#define AIN_0_PORT              PTE_L_HALF
#define VRC_CTRL_PIN            10u
#define VRC_CTRL_PORT           PTE_L_HALF
#define AIN_BAT_PIN             13u
#define AIN_BAT_PORT            PTE_L_HALF
#define SPI1_MOSI_PIN           13u
#define SPI1_MOSI_PORT          PTA_H_HALF

#ifdef __cplusplus
}
#endif

/*!
 * @}
 */
#endif /* _SIUL2_PORT_IP_CFG_H_ */

/***********************************************************************************************************************
 * EOF
 **********************************************************************************************************************/

