generate/src/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.o: \
 ../generate/src/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.c \
 C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.h \
 ../RTD/include/Adc_Sar_Ip_Types.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/StandardTypes.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Platform_Types.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/PlatformTypes.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Compiler.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Compiler_Cfg.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/CompilerDefinition.h \
 C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/Adc_Sar_Ip_CfgDefines.h \
 ../RTD/include/OsIf.h ../RTD/include/OsIf_Internal.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Soc_Ips.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/IpVersionMacros.h \
 C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/OsIf_Cfg.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Base_MemMap.h \
 ../RTD/include/Adc_Sar_Ip_DeviceRegisters.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Devassert.h \
 ../RTD/include/Adc_Sar_Ip_HeaderWrapper_S32K3.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_ADC.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_COMMON.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/BasicTypes.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_TEMPSENSE.h \
 C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Adc_MemMap.h

C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/Adc_Sar_Ip_BOARD_InitPeripherals_PBcfg.h:

../RTD/include/Adc_Sar_Ip_Types.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/StandardTypes.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Platform_Types.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/PlatformTypes.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Compiler.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Compiler_Cfg.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/CompilerDefinition.h:

C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/Adc_Sar_Ip_CfgDefines.h:

../RTD/include/OsIf.h:

../RTD/include/OsIf_Internal.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Soc_Ips.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/IpVersionMacros.h:

C:/Users/MSI/Documents/WorkSpace/git/ADM/GW/generate/include/OsIf_Cfg.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Base_MemMap.h:

../RTD/include/Adc_Sar_Ip_DeviceRegisters.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Devassert.h:

../RTD/include/Adc_Sar_Ip_HeaderWrapper_S32K3.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_ADC.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_COMMON.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/BasicTypes.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/header/S32K344_TEMPSENSE.h:

C:/NXP/S32DS.3.4/S32DS/software/PlatformSDK_S32K3_2021_03/SW32K3_RTD_4_4_0_9_0_D2103/Base_TS_T40D34M9I0R0/include/Adc_MemMap.h:
