Flexio_Mcl_Ip_ClearPinStatus (struct FLEXIO_Type * baseAddr, uint8 pin)
{
  long unsigned int _1;
  int _2;
  unsigned int _3;
  unsigned char _4;
  long unsigned int _5;
  long unsigned int _6;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 ={v} baseAddr_8(D)->PINSTAT;
  _2 = (int) pin_9(D);
  _3 = 1 << _2;
  _4 = (unsigned char) _3;
  _5 = (long unsigned int) _4;
  _6 = _1 | _5;
  baseAddr_8(D)->PINSTAT ={v} _6;
  return;

}


Flexio_Mcl_Ip_SetTimerDMARequest (struct FLEXIO_Type * baseAddr, uint8 requestMask, boolean enable)
{
  uint32 tmp;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_46 ();
  # DEBUG BEGIN_STMT
  tmp_8 ={v} baseAddr_7(D)->TIMERSDEN;
  # DEBUG tmp => tmp_8
  # DEBUG BEGIN_STMT
  if (enable_9(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _1 = (long unsigned int) requestMask_10(D);
  tmp_12 = tmp_8 | _1;
  # DEBUG tmp => tmp_12
  goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  _2 = (long unsigned int) requestMask_10(D);
  _3 = ~_2;
  tmp_11 = tmp_8 & _3;
  # DEBUG tmp => tmp_11

  <bb 5> :
  # tmp_4 = PHI <tmp_12(3), tmp_11(4)>
  # DEBUG tmp => tmp_4
  # DEBUG BEGIN_STMT
  baseAddr_7(D)->TIMERSDEN ={v} tmp_4;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_46 ();
  return;

}


Flexio_Mcl_Ip_Init (struct FLEXIO_Type * baseAddr)
{
  <bb 2> :
  # DEBUG BEGIN_STMT
  Flexio_Mcl_Ip_SetSoftwareReset (baseAddr_2(D), 1);
  # DEBUG BEGIN_STMT
  baseAddr_2(D)->CTRL ={v} 0;
  return;

}


Flexio_Mcl_Ip_SetTimerInterrupt (struct FLEXIO_Type * baseAddr, uint8 interruptMask, boolean enable)
{
  uint32 tmp;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_45 ();
  # DEBUG BEGIN_STMT
  tmp_8 ={v} baseAddr_7(D)->TIMIEN;
  # DEBUG tmp => tmp_8
  # DEBUG BEGIN_STMT
  if (enable_9(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _1 = (long unsigned int) interruptMask_10(D);
  tmp_12 = tmp_8 | _1;
  # DEBUG tmp => tmp_12
  goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  _2 = (long unsigned int) interruptMask_10(D);
  _3 = ~_2;
  tmp_11 = tmp_8 & _3;
  # DEBUG tmp => tmp_11

  <bb 5> :
  # tmp_4 = PHI <tmp_12(3), tmp_11(4)>
  # DEBUG tmp => tmp_4
  # DEBUG BEGIN_STMT
  baseAddr_7(D)->TIMIEN ={v} tmp_4;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_45 ();
  return;

}


Flexio_Mcl_Ip_GetAllTimerInterrupt (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->TIMIEN;
  return _3;

}


Flexio_Mcl_Ip_SetShifterDMARequest (struct FLEXIO_Type * baseAddr, uint8 requestMask, boolean enable)
{
  uint32 tmp;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_44 ();
  # DEBUG BEGIN_STMT
  tmp_8 ={v} baseAddr_7(D)->SHIFTSDEN;
  # DEBUG tmp => tmp_8
  # DEBUG BEGIN_STMT
  if (enable_9(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _1 = (long unsigned int) requestMask_10(D);
  tmp_12 = tmp_8 | _1;
  # DEBUG tmp => tmp_12
  goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  _2 = (long unsigned int) requestMask_10(D);
  _3 = ~_2;
  tmp_11 = tmp_8 & _3;
  # DEBUG tmp => tmp_11

  <bb 5> :
  # tmp_4 = PHI <tmp_12(3), tmp_11(4)>
  # DEBUG tmp => tmp_4
  # DEBUG BEGIN_STMT
  baseAddr_7(D)->SHIFTSDEN ={v} tmp_4;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_44 ();
  return;

}


Flexio_Mcl_Ip_GetAllPinsInterrupt (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->PINIEN;
  return _3;

}


Flexio_Mcl_Ip_GetAllPinsStatus (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->PINSTAT;
  return _3;

}


Flexio_Mcl_Ip_SetShifterInterrupt (struct FLEXIO_Type * baseAddr, uint8 interruptMask, boolean enable)
{
  uint32 tmp;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_43 ();
  # DEBUG BEGIN_STMT
  tmp_8 ={v} baseAddr_7(D)->SHIFTSIEN;
  # DEBUG tmp => tmp_8
  # DEBUG BEGIN_STMT
  if (enable_9(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _1 = (long unsigned int) interruptMask_10(D);
  tmp_12 = tmp_8 | _1;
  # DEBUG tmp => tmp_12
  goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  _2 = (long unsigned int) interruptMask_10(D);
  _3 = ~_2;
  tmp_11 = tmp_8 & _3;
  # DEBUG tmp => tmp_11

  <bb 5> :
  # tmp_4 = PHI <tmp_12(3), tmp_11(4)>
  # DEBUG tmp => tmp_4
  # DEBUG BEGIN_STMT
  baseAddr_7(D)->SHIFTSIEN ={v} tmp_4;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_43 ();
  return;

}


Flexio_Mcl_Ip_SetShifterErrorInterrupt (struct FLEXIO_Type * baseAddr, uint8 interruptMask, boolean enable)
{
  uint32 tmp;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_42 ();
  # DEBUG BEGIN_STMT
  tmp_8 ={v} baseAddr_7(D)->SHIFTEIEN;
  # DEBUG tmp => tmp_8
  # DEBUG BEGIN_STMT
  if (enable_9(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _1 = (long unsigned int) interruptMask_10(D);
  tmp_12 = tmp_8 | _1;
  # DEBUG tmp => tmp_12
  goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  _2 = (long unsigned int) interruptMask_10(D);
  _3 = ~_2;
  tmp_11 = tmp_8 & _3;
  # DEBUG tmp => tmp_11

  <bb 5> :
  # tmp_4 = PHI <tmp_12(3), tmp_11(4)>
  # DEBUG tmp => tmp_4
  # DEBUG BEGIN_STMT
  baseAddr_7(D)->SHIFTEIEN ={v} tmp_4;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_42 ();
  return;

}


Flexio_Mcl_Ip_GetAllShifterErrorInterrupt (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->SHIFTEIEN;
  return _3;

}


Flexio_Mcl_Ip_GetAllShifterInterrupt (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->SHIFTSIEN;
  return _3;

}


Flexio_Mcl_Ip_ClearTimerStatus (struct FLEXIO_Type * baseAddr, uint8 timer)
{
  int _1;
  long unsigned int _2;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = (int) timer_3(D);
  _2 = 1 << _1;
  baseAddr_5(D)->TIMSTAT ={v} _2;
  return;

}


Flexio_Mcl_Ip_GetAllTimerStatus (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->TIMSTAT;
  return _3;

}


Flexio_Mcl_Ip_GetTimerInterruptEnable (const struct FLEXIO_Type * baseAddr, uint8 timer)
{
  long unsigned int _1;
  int _2;
  long unsigned int _3;
  long unsigned int _4;
  boolean _8;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 ={v} baseAddr_6(D)->TIMIEN;
  _2 = (int) timer_7(D);
  _3 = _1 >> _2;
  _4 = _3 & 1;
  _8 = _4 != 0;
  return _8;

}


Flexio_Mcl_Ip_GetTimerStatus (const struct FLEXIO_Type * baseAddr, uint8 timer)
{
  long unsigned int _1;
  int _2;
  long unsigned int _3;
  long unsigned int _4;
  boolean _8;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 ={v} baseAddr_6(D)->TIMSTAT;
  _2 = (int) timer_7(D);
  _3 = _1 >> _2;
  _4 = _3 & 1;
  _8 = _4 != 0;
  return _8;

}


Flexio_Mcl_Ip_ClearShifterErrorStatus (struct FLEXIO_Type * baseAddr, uint8 shifter)
{
  int _1;
  long unsigned int _2;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = (int) shifter_3(D);
  _2 = 1 << _1;
  baseAddr_5(D)->SHIFTERR ={v} _2;
  return;

}


Flexio_Mcl_Ip_GetAllShifterErrorStatus (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->SHIFTERR;
  return _3;

}


Flexio_Mcl_Ip_GetShifterErrorStatus (const struct FLEXIO_Type * baseAddr, uint8 shifter)
{
  long unsigned int _1;
  int _2;
  long unsigned int _3;
  long unsigned int _4;
  boolean _8;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 ={v} baseAddr_6(D)->SHIFTERR;
  _2 = (int) shifter_7(D);
  _3 = _1 >> _2;
  _4 = _3 & 1;
  _8 = _4 != 0;
  return _8;

}


Flexio_Mcl_Ip_ClearShifterStatus (struct FLEXIO_Type * baseAddr, uint8 shifter)
{
  int _1;
  long unsigned int _2;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = (int) shifter_3(D);
  _2 = 1 << _1;
  baseAddr_5(D)->SHIFTSTAT ={v} _2;
  return;

}


Flexio_Mcl_Ip_GetAllShifterStatus (const struct FLEXIO_Type * baseAddr)
{
  uint32 _3;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _3 ={v} baseAddr_2(D)->SHIFTSTAT;
  return _3;

}


Flexio_Mcl_Ip_GetShifterStatus (const struct FLEXIO_Type * baseAddr, uint8 shifter)
{
  long unsigned int _1;
  int _2;
  long unsigned int _3;
  long unsigned int _4;
  boolean _8;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 ={v} baseAddr_6(D)->SHIFTSTAT;
  _2 = (int) shifter_7(D);
  _3 = _1 >> _2;
  _4 = _3 & 1;
  _8 = _4 != 0;
  return _8;

}


Flexio_Mcl_Ip_SetEnable (struct FLEXIO_Type * baseAddr, boolean enable)
{
  uint32 regValue;
  long unsigned int iftmp.2_1;
  long unsigned int iftmp.2_8;
  long unsigned int iftmp.2_9;

  <bb 2> :
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_41 ();
  # DEBUG BEGIN_STMT
  regValue_5 ={v} baseAddr_4(D)->CTRL;
  # DEBUG regValue => regValue_5
  # DEBUG BEGIN_STMT
  regValue_6 = regValue_5 & 4294967294;
  # DEBUG regValue => regValue_6
  # DEBUG BEGIN_STMT
  if (enable_7(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  iftmp.2_9 = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  iftmp.2_8 = 0;

  <bb 5> :
  # iftmp.2_1 = PHI <iftmp.2_9(3), iftmp.2_8(4)>
  regValue_10 = iftmp.2_1 | regValue_6;
  # DEBUG regValue => regValue_10
  # DEBUG BEGIN_STMT
  baseAddr_4(D)->CTRL ={v} regValue_10;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_41 ();
  return;

}


Flexio_Mcl_Ip_SetDebugEnable (struct FLEXIO_Type * baseAddr, boolean enable)
{
  uint32 regValue;
  long unsigned int iftmp.1_1;
  long unsigned int iftmp.1_8;
  long unsigned int iftmp.1_9;

  <bb 2> :
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_40 ();
  # DEBUG BEGIN_STMT
  regValue_5 ={v} baseAddr_4(D)->CTRL;
  # DEBUG regValue => regValue_5
  # DEBUG BEGIN_STMT
  regValue_6 = regValue_5 & 3221225471;
  # DEBUG regValue => regValue_6
  # DEBUG BEGIN_STMT
  if (enable_7(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  iftmp.1_9 = 1073741824;
  goto <bb 5>; [INV]

  <bb 4> :
  iftmp.1_8 = 0;

  <bb 5> :
  # iftmp.1_1 = PHI <iftmp.1_9(3), iftmp.1_8(4)>
  regValue_10 = iftmp.1_1 | regValue_6;
  # DEBUG regValue => regValue_10
  # DEBUG BEGIN_STMT
  baseAddr_4(D)->CTRL ={v} regValue_10;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_40 ();
  return;

}


Flexio_Mcl_Ip_SetSoftwareReset (struct FLEXIO_Type * baseAddr, boolean enable)
{
  uint32 regValue;
  long unsigned int iftmp.0_1;
  long unsigned int iftmp.0_8;
  long unsigned int iftmp.0_9;

  <bb 2> :
  # DEBUG BEGIN_STMT
  SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_39 ();
  # DEBUG BEGIN_STMT
  regValue_5 ={v} baseAddr_4(D)->CTRL;
  # DEBUG regValue => regValue_5
  # DEBUG BEGIN_STMT
  regValue_6 = regValue_5 & 4294967293;
  # DEBUG regValue => regValue_6
  # DEBUG BEGIN_STMT
  if (enable_7(D) != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  iftmp.0_9 = 2;
  goto <bb 5>; [INV]

  <bb 4> :
  iftmp.0_8 = 0;

  <bb 5> :
  # iftmp.0_1 = PHI <iftmp.0_9(3), iftmp.0_8(4)>
  regValue_10 = iftmp.0_1 | regValue_6;
  # DEBUG regValue => regValue_10
  # DEBUG BEGIN_STMT
  baseAddr_4(D)->CTRL ={v} regValue_10;
  # DEBUG BEGIN_STMT
  SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_39 ();
  return;

}


