################################################################################
# Automatically-generated file. Do not edit!
################################################################################

# Add inputs and outputs from these tool invocations to the build variables 
C_SRCS += \
../RTD/src/Adc_Sar_Ip.c \
../RTD/src/Adc_Sar_Ip_Isr.c \
../RTD/src/Clock_Ip.c \
../RTD/src/Clock_Ip_Divider.c \
../RTD/src/Clock_Ip_DividerTrigger.c \
../RTD/src/Clock_Ip_ExtOsc.c \
../RTD/src/Clock_Ip_FracDiv.c \
../RTD/src/Clock_Ip_Gate.c \
../RTD/src/Clock_Ip_IntOsc.c \
../RTD/src/Clock_Ip_Irq.c \
../RTD/src/Clock_Ip_Monitor.c \
../RTD/src/Clock_Ip_Pll.c \
../RTD/src/Clock_Ip_ProgFreqSwitch.c \
../RTD/src/Clock_Ip_Selector.c \
../RTD/src/Clock_Ip_Specific.c \
../RTD/src/Det.c \
../RTD/src/Det_stub.c \
../RTD/src/Emios_Mcl_Ip.c \
../RTD/src/Emios_Mcl_Ip_Irq.c \
../RTD/src/Emios_Pwm_Ip.c \
../RTD/src/Emios_Pwm_Ip_Irq.c \
../RTD/src/FlexCAN_Ip.c \
../RTD/src/FlexCAN_Ip_HwAccess.c \
../RTD/src/FlexCAN_Ip_Irq.c \
../RTD/src/Flexio_Mcl_Ip.c \
../RTD/src/Flexio_Mcl_Ip_HwAccess.c \
../RTD/src/Flexio_Mcl_Ip_Irq.c \
../RTD/src/IntCtrl_Ip.c \
../RTD/src/Lin_Ip_Common.c \
../RTD/src/Lpi2c_Ip.c \
../RTD/src/Lpi2c_Ip_HwAccess.c \
../RTD/src/Lpi2c_Ip_Irq.c \
../RTD/src/Lpspi_Ip.c \
../RTD/src/Lpspi_Ip_Irq.c \
../RTD/src/Lpuart_Lin_Ip.c \
../RTD/src/Lpuart_Lin_Ip_Hw_Access.c \
../RTD/src/Lpuart_Lin_Ip_Irq.c \
../RTD/src/Lpuart_Uart_Ip.c \
../RTD/src/Lpuart_Uart_Ip_Irq.c \
../RTD/src/OsIf_Timer.c \
../RTD/src/OsIf_Timer_System.c \
../RTD/src/Os_counter_api.c \
../RTD/src/Os_multicore.c \
../RTD/src/Pit_Ip.c \
../RTD/src/SchM_Adc.c \
../RTD/src/SchM_Can.c \
../RTD/src/SchM_Gpt.c \
../RTD/src/SchM_Lin.c \
../RTD/src/SchM_Mcl.c \
../RTD/src/SchM_Mcu.c \
../RTD/src/SchM_Pwm.c \
../RTD/src/SchM_Spi.c \
../RTD/src/SchM_Uart.c \
../RTD/src/SchM_Wdg.c \
../RTD/src/Siul2_Dio_Ip.c \
../RTD/src/Siul2_Port_Ip.c \
../RTD/src/Swt_Ip.c \
../RTD/src/Swt_Ip_Irq.c 

OBJS += \
./RTD/src/Adc_Sar_Ip.o \
./RTD/src/Adc_Sar_Ip_Isr.o \
./RTD/src/Clock_Ip.o \
./RTD/src/Clock_Ip_Divider.o \
./RTD/src/Clock_Ip_DividerTrigger.o \
./RTD/src/Clock_Ip_ExtOsc.o \
./RTD/src/Clock_Ip_FracDiv.o \
./RTD/src/Clock_Ip_Gate.o \
./RTD/src/Clock_Ip_IntOsc.o \
./RTD/src/Clock_Ip_Irq.o \
./RTD/src/Clock_Ip_Monitor.o \
./RTD/src/Clock_Ip_Pll.o \
./RTD/src/Clock_Ip_ProgFreqSwitch.o \
./RTD/src/Clock_Ip_Selector.o \
./RTD/src/Clock_Ip_Specific.o \
./RTD/src/Det.o \
./RTD/src/Det_stub.o \
./RTD/src/Emios_Mcl_Ip.o \
./RTD/src/Emios_Mcl_Ip_Irq.o \
./RTD/src/Emios_Pwm_Ip.o \
./RTD/src/Emios_Pwm_Ip_Irq.o \
./RTD/src/FlexCAN_Ip.o \
./RTD/src/FlexCAN_Ip_HwAccess.o \
./RTD/src/FlexCAN_Ip_Irq.o \
./RTD/src/Flexio_Mcl_Ip.o \
./RTD/src/Flexio_Mcl_Ip_HwAccess.o \
./RTD/src/Flexio_Mcl_Ip_Irq.o \
./RTD/src/IntCtrl_Ip.o \
./RTD/src/Lin_Ip_Common.o \
./RTD/src/Lpi2c_Ip.o \
./RTD/src/Lpi2c_Ip_HwAccess.o \
./RTD/src/Lpi2c_Ip_Irq.o \
./RTD/src/Lpspi_Ip.o \
./RTD/src/Lpspi_Ip_Irq.o \
./RTD/src/Lpuart_Lin_Ip.o \
./RTD/src/Lpuart_Lin_Ip_Hw_Access.o \
./RTD/src/Lpuart_Lin_Ip_Irq.o \
./RTD/src/Lpuart_Uart_Ip.o \
./RTD/src/Lpuart_Uart_Ip_Irq.o \
./RTD/src/OsIf_Timer.o \
./RTD/src/OsIf_Timer_System.o \
./RTD/src/Os_counter_api.o \
./RTD/src/Os_multicore.o \
./RTD/src/Pit_Ip.o \
./RTD/src/SchM_Adc.o \
./RTD/src/SchM_Can.o \
./RTD/src/SchM_Gpt.o \
./RTD/src/SchM_Lin.o \
./RTD/src/SchM_Mcl.o \
./RTD/src/SchM_Mcu.o \
./RTD/src/SchM_Pwm.o \
./RTD/src/SchM_Spi.o \
./RTD/src/SchM_Uart.o \
./RTD/src/SchM_Wdg.o \
./RTD/src/Siul2_Dio_Ip.o \
./RTD/src/Siul2_Port_Ip.o \
./RTD/src/Swt_Ip.o \
./RTD/src/Swt_Ip_Irq.o 

C_DEPS += \
./RTD/src/Adc_Sar_Ip.d \
./RTD/src/Adc_Sar_Ip_Isr.d \
./RTD/src/Clock_Ip.d \
./RTD/src/Clock_Ip_Divider.d \
./RTD/src/Clock_Ip_DividerTrigger.d \
./RTD/src/Clock_Ip_ExtOsc.d \
./RTD/src/Clock_Ip_FracDiv.d \
./RTD/src/Clock_Ip_Gate.d \
./RTD/src/Clock_Ip_IntOsc.d \
./RTD/src/Clock_Ip_Irq.d \
./RTD/src/Clock_Ip_Monitor.d \
./RTD/src/Clock_Ip_Pll.d \
./RTD/src/Clock_Ip_ProgFreqSwitch.d \
./RTD/src/Clock_Ip_Selector.d \
./RTD/src/Clock_Ip_Specific.d \
./RTD/src/Det.d \
./RTD/src/Det_stub.d \
./RTD/src/Emios_Mcl_Ip.d \
./RTD/src/Emios_Mcl_Ip_Irq.d \
./RTD/src/Emios_Pwm_Ip.d \
./RTD/src/Emios_Pwm_Ip_Irq.d \
./RTD/src/FlexCAN_Ip.d \
./RTD/src/FlexCAN_Ip_HwAccess.d \
./RTD/src/FlexCAN_Ip_Irq.d \
./RTD/src/Flexio_Mcl_Ip.d \
./RTD/src/Flexio_Mcl_Ip_HwAccess.d \
./RTD/src/Flexio_Mcl_Ip_Irq.d \
./RTD/src/IntCtrl_Ip.d \
./RTD/src/Lin_Ip_Common.d \
./RTD/src/Lpi2c_Ip.d \
./RTD/src/Lpi2c_Ip_HwAccess.d \
./RTD/src/Lpi2c_Ip_Irq.d \
./RTD/src/Lpspi_Ip.d \
./RTD/src/Lpspi_Ip_Irq.d \
./RTD/src/Lpuart_Lin_Ip.d \
./RTD/src/Lpuart_Lin_Ip_Hw_Access.d \
./RTD/src/Lpuart_Lin_Ip_Irq.d \
./RTD/src/Lpuart_Uart_Ip.d \
./RTD/src/Lpuart_Uart_Ip_Irq.d \
./RTD/src/OsIf_Timer.d \
./RTD/src/OsIf_Timer_System.d \
./RTD/src/Os_counter_api.d \
./RTD/src/Os_multicore.d \
./RTD/src/Pit_Ip.d \
./RTD/src/SchM_Adc.d \
./RTD/src/SchM_Can.d \
./RTD/src/SchM_Gpt.d \
./RTD/src/SchM_Lin.d \
./RTD/src/SchM_Mcl.d \
./RTD/src/SchM_Mcu.d \
./RTD/src/SchM_Pwm.d \
./RTD/src/SchM_Spi.d \
./RTD/src/SchM_Uart.d \
./RTD/src/SchM_Wdg.d \
./RTD/src/Siul2_Dio_Ip.d \
./RTD/src/Siul2_Port_Ip.d \
./RTD/src/Swt_Ip.d \
./RTD/src/Swt_Ip_Irq.d 


# Each subdirectory must supply rules for building sources it contributes
RTD/src/%.o: ../RTD/src/%.c
	@echo 'Building file: $<'
	@echo 'Invoking: Standard S32DS C Compiler'
	arm-none-eabi-gcc "@RTD/src/Adc_Sar_Ip.args" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<"
	@echo 'Finished building: $<'
	@echo ' '


